UTMC 5962R-0050501VTBDX, 5962R-0050501VTBDC, 5962R-0050501VTBDA, 5962R-0050501QTBDC, 5962R-0050501QTBDA Datasheet

FEATURES

q Synchronous and asynchronous operation
q Synchronous 5-8 bit characters; internal or external

character synchronization; automatic synchronization
insertion

q Asynchronous 5-8 bit characters; Clock Rate - 1, 16,

or 64 Times Baud Rate; break character generation; 1,

1.5, or 2 stop bits; false start bit detection; automatic
break detect and handling

q Synchronous baud rate - 1 to 64K baud
q Asynchronous baud rate - 1 to 19.2K baud
q Full-Duplex, double-buffered transmitter and receiver
q Error detection - parity, overrun and framing errors
q Radiation-hardened process and design; total dose

iradiation testing to MIL-STD-883 Method 1019

- Total-dose: 300 krad(Si)

- SEL LET threshold: greater than 120MeV-cm2/mg

- Neutron Fluence: 3.0E14n/cm

2

q Packaging options:

- 36-lead Flatpack

- 68-lead Flatpack

q 5.0 and 3.3 volt operation
q Standard Microcircuit Drawing 5962-00505

- QML Q and V compliant part

q Available as core IP for ASIC applications

INTRODUCTION

The UT82CRH51A is an enhanced version of the industry
standard, Universal Synchronous/Asynchronous Receiver
Transmitter (USART), designed to provide data
communications between subsystem. The UT82CRH51A

USART is built using UTMC’s Commercial RadHard

TM

epitaxial CMOS technology and is ideal for space applications.
In a communication environment an interface device converts
parallel format system data into serial format for transmission,
and converts incoming serial format data into parallel system
data for reception. The UT82CRH51A is used as a peripheral
device and is programmed by a host CPU to operate using
virtually any serial data transmission technique. The USART
accepts data characters from the CPU in a parallel format and
then converts the data into a continuous serial data stream for
transmission. Simultaneously, the UT82CRH51A receives
serial data streams and converts the data into a parallel data
character for the host CPU. The USART signals the CPU
whenever it accepts a new character for transmission or
whenever it has received a character for the CPU. The CPU
reads the complete status of the USART at any time. These
include data transmission errors and control signals such as
SYNDET/BRKDET, TxEMPTY.

Figure 1. UT82CRH51A USART Block Diagram

D(7:0)

DATA

BUS

BUFFER

READ/WRITE

CONTROL

LOGIC

MODEM

CONTROL

TRANSMIT

BUFFER

(P-S)

TRANSMITTER

CONTROL

RECEIVE

BUFFER

(S-P)

RECEIVER

CONTROL

RESET

CLK
C/D
RD
WR

CS

DSR
DTR

CTS
RTS

TxRDY
TxEMPTY

TxC

TxD

RxD

RxRDY
RxC

SYNDET/
BRKDET

INTERNAL
DATA BUS

Standard Products

UT82CRH51A USART

Preliminary Data Sheet

December 9, 1999

2

1.0 Functional Description

The UT82CRH51A is designed for a wide range of
microcomputers. Like other I/O devices in a microcomputer
system, its functional configuration is programmed by the
system’s software for maximum flexibility. The UT82CRH51A
can support most serial data techniques in use.

In a communication environment an interface device must
convert parallel format system data into serial format for
transmission and convert incoming serial format data into
parallel system data for reception. The interface device must also
delete or insert bits or characters that are functionally unique to
the communication technique. Therefore, the interface should
appear "transparent" to the CPU, a simple input or output of byte­oriented system data (figure 7).

1.1 DATA BUS BUFFER

This three-state, bidirectional, 8-bit buffer is used to interface the
UT82CRH51A to the system Data Bus. Data is transmitted or
received by the buffer upon execution of INput or OUTput
instructions of the CPU. Control words, Command words and
Status information are also transferred through the Data Bus
Buffer. The Command Status, Data-In and Data-Out registers
are separate, 8-bit registers communicating with the system bus
through the Data Bus Buffer.

This functional block accepts inputs from the system Control bus
and generates control signals for overall device operation. It
contains the Control Word Register and Command Word
Register that store the various control formats for the device
functional definition.

1.2 READ/WRITE CONTROL LOGIC

1.2.1 RESET (Reset)

A "high" on this input forces the UT82CRH51A into an "Idle"
mode. The device remains at "Idle" until a new set of control
words is written into the UT82CRH51A to program its function­al definition. Minimum RESET pulse width is 6tCY (clock must
be running).

A command reset operation also puts the device into the "Idle"
state.

1.2.2 CLK (CLOCK)

The CLK input is used to generate internal device timing and is
normally connected to the Phase 2 (TTL) output of the Clock
Generator. No external inputs or outputs are referenced to CLK,
but the frequency of CLK must be greater than 30 times the Re­ceiver or Transmitter data bit rates.

1.2.3 WR (Write)

A "low" on this input informs the UT82CRH51A the CPU is
writing data or control words to the UT82CRH51A (figure 4).

1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19

Figure 2. UT82CRH51A Pinout (36)

V

SS

V

DD

D2
D1
D0
RxC
DTR
RTS
DSR
RESET
CLK
TxD
TxEMPTY
CTS
SYNDET
TxRDY
V

DD

V

SS

V

SS

V

DD

RxD

D4
NC
NC

D5

D6

D7

TxC

WR

CS

C/D

RD

RxRDY

D3

V

DD

V

SS

9
8
7
6
5
4
3
2
1
68
67
66
65
64
63

62

61

44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Top View

NC
NC

V

SS

NC
RxD

NC

D3

NC

D2

NC

D1

NC

D0

NC

V

DD

NC
NC

NC
NC

C/D

NC

RD
NC

RxDY

NC

TxRDY

NC

SYNDET

NC

CTS

NC

TxE

NC
NC

NC

NC

D4

NC

D5

NC

D6

NC

D7

NC

TxC

NC

WR

NC

CS

NC

NC

NC

NC

TxD

NC

CLK

NC

RESET

NC

DSR

NC

RTS

NC

DTR

NC

RxC

NC

NC

Figure 3. UT82CRH51A Pinout (68)

3

1.2.4 RD (Read)

A "low" on this input informs the UT82CRH51A the CPU is
reading data or status information from the UT82CRH51A (fig­ure 4).

1.2.5 C/D (Control/Data)

This input, in conjunction with the WR and RD inputs, informs
the UT82CRH51A the word on the Data Bus is either a data
character, control word or status information.

1 = CONTROL/STATUS; 0 = DATA

1.2.6 CS (Chip Select)

A "low" on this input selects the UT82CRH51A. No reading or
writing will occur unless the device is selected. When CS is
high, the Data Bus is in the float state and RD and WR have no
effect on the chip.

1.3 MODEM CONTROL

The UT82CRH51A has a set of control inputs and outputs that
can be used to simplify the interface to almost any modem. The
modem control signals are general purpose in nature and can be
used to functions, other than modem control, if necessary (figure

5).

1.3.1 DSR (Data Set Ready)

The DSR input signal is a general-purpose, 1-bit inverting input
port. Its condition can be tested by the CPU using a Status Read
operation. The DSR input is normally used to test modem con­ditions such as Data Set Ready.

1.3.2 DTR (Data Terminal Ready)

The DTR output signal is a general-purpose, 1-bit inverting out­put port. It can be set "low" by programming the appropriate bit
in the Command Instruction word. The DTR output signal is
normally used for modem control such as Data Terminal Ready.

1.3.3 RTS (Request to Send)

The RTS output signal is a general-purpose, 1-bit inverting out­put port. It can be set "low" by programming the appropriate bit
in the Command Instruction word. The RTS output signal is
normally used for modem control such as Request to Send.

1.3.4 CTS (Clear to Send)

A "low" on this input enables the UT82CRH51A to transmit se­rial data if the TxEnable bit in the Command byte is set to a
"one". If either a TxEnable off or CTS off condition occurs
while the Tx is in operation, the Tx transmits all the data in the
USART written prior to TxDisable command before shutting
down.

1.4 TRANSMIT BUFFER

The Transmit Buffer Accepts parallel data from the Data Bus
Buffer, converts it to a serial bit stream, inserts the appropriate
characters or bits (based on the communication technique) and
outputs a composite serial stream of data on the TxD output pin
on the falling edge of TxC. The transmitter begins transmission
upon being enabled if CTS = 0. The TxD line will be held in the
marking state immediately upon a master Reset or when TxEn­able or CTS is off or the transmitter is empty (figure 5).

1.5.TRANSMITTER CONTROL

The Transmitter Control manages all activities associated with
the transmission of serial data. It accepts and issues signals both
externally and internally to accomplish this function (figure 5).

1.5.1 TxRDY (Transmitter Ready)

This output signals the CPU the transmitter is ready to accept a
data character. The TxRDY output pin can be used as an inter­rupt to the system since it is masked by TxEnable; or, for Polled
operation, the CPU can check TxRDY using a Status Read op­eration. TxRDY is automatically reset by the leading edge of
WR when a data character is loaded from the CPU.

Note: When using the Polled operation, the TxRDY status bit
is not masked by TxEnable, but will only indicate the Empty/
Full Status of the Tx Data Input Register.

1.5.2 TxEMPTY (Transmitter Empty)

When the UT82CRH51A has no characters to send, the TxEMP­TY output will go "high". It resets upon receiving a character

C/D RD WR CS

0 0 1 0

DATA -> DATA BUS

0 1 0 0

DATA BUS -> DATA

1 0 1 0

STATUS -> DATA BUS

1 1 0 0

DATA BUS -> CONTROL

X 1 1 0

DATA BUS -> 3-STATE

X X X 1

DATA BUS -> 3-STATE

Figure 4. UT82CRH51A Block Diagram Showing Data Bus Buffer

and Read/Write Logic Functions

D(7:0)

DATA

BUS

BUFFER

READ/WRITE

CONTROL

LOGIC

MODEM

CONTROL

TRANSMIT

BUFFER

(P-S)

TRANS­MITTER

CONTROL

RECEIVE

BUFFER

(S-P)

RECEIVER

CONTROL

RESET

CLK

C/D
RD

WR

CS

DSR
DTR

CTS
RTS

TxRDY

TxEMPTY
TxC

TxD

RxD

RxRDY
RxC

SYNDET/
BRKDET

4

from the CPU if the transmitter is enabled. TxEMPTY remains
low when the transmitter is disabled even if it is actually empty.
TxEMPTY can be used to indicate the end of a transmission
mode, so the CPU knows when to turn the line around in the
half-duplex operational mode.

In the Synchronous mode, a "high" on this output indicates that
a character has not been loaded and the SYNC character or char­acters are about to be or are being transmitted automatically as
"fillers". TxEMPTY does not go low when the SYNC charac­ters are being shifted out.

1.5.3 TxC (Transmitter Clock)

The Transmitter Clock controls the rate at which the character is
to be transmitted. In the Synchronous transmission mode, the
Baud Rate (1x) is equal to the TxC frequency. In Asynchronous
transmission mode, the baud rate is a fraction of the actual TxC
frequency. A portion of the mode instruction selects this factor;
it can be 1, 1/16 or 1/64 the TxC.

For example:

If Baud Rate equals 110 Baud,
TxC equals 110 Hz in the 1x mode
TxC equals 1.72 kHz in the 16x mode
TxC equals 7.04 kHz in the 64x mode

The falling edge of TxC shifts the serial data out of the
UT82CRH51A.

1.6 RECEIVE BUFFER

The Receiver accepts serial data, converts this serial input to
parallel format, checks for bits or characters that are unique to
the communication technique and sends an "assembled" charac­ter to the CPU. Serial data is input to RxD pin, and is clocked
in on the rising edge of RxC (figure 6).

1.7 RECEIVER CONTROL

This functional block manages all receiver-related activities
which consists of the following features (figure 6).

• The RxD initialization circuit prevents the
UT82CRH51A from mistaking an unused input line for
an active low data line in the "break condition". Before
starting to receive serial characters on the RxD line, a
valid "1" must first be detected after a chip master Reset.
Once this has been determined, a search for a valid low
(Start bit) is enabled. This feature is only active in the
asynchronous mode, and is only done once for each mas­ter Reset.

• The False Start bit detection circuit prevents false starts
due to a transient noise spike by first detecting the falling
edge and then strobing the nominal center of the Start bit
(RxD = low).

• Parity error detection sets the corresponding status bit.

• The Framing Error status bit is set if the Stop bit is absent
at the end of the data byte (asynchronous mode).

1.7.1 RxRDY (Receiver Ready)

This output indicates the UT82CRH51A contains a character
ready to be input to the CPU. RxRDY can be connected to the
interrupt structure of the CPU or, for polled operation, the CPU
checks the condition of RxRDY using a Status Read operation.

RxEnable, when off, holds RxRDY in the Reset Condition. For
Asynchronous mode, to set RxRDY, the Receiver must be en­abled to sense a Start Bit and a complete character must be as­sembled and transferred to the Data Output Register. For
Synchronous mode, to set RxRDY, the Receiver must be en­abled and a character must finish assembly and be transferred to
the Data Output Register.

Failure to read the received character from the Rx Data Output
Register prior to the assembly of the next Rx Data character will
set overrun condition error and the previous character will be
written over and lost. If the Rx Data is being read by the CPU
when the internal transfer is occurring, overrun error will be set
and the old character will be lost.

1.7.2 RxC (Receiver Clock)

The Receiver Clock controls the rate at which the character is to
be received. In Synchronous Mode, the Baud Rate (1x) is equal
to the actual frequency of RxC. In Asynchronous Mode, the
Baud Rate is a fraction of the actual RxC frequency. A portion
of the mode instruction selects this factor: 1, 1/16 or 1/64 the
RxC.

For example:

Baud Rate Equals 300 Baud, if
RxC equals 300 Hz in the 1x mode
RxC equals 4800 Hz in the 16x mode
RxC equals 19.2 kHz in the 64x mode

Baude Rate equals 2400 Baude, if
RxC equals 2400 Hz in the 1x mode
RxC equals 38.4 kHz in the 16x mode
RxC equals 153.6 kHz in the 64x mode

Data is sampled into the UT82CRH51A on the rising edge of

Figure 5. UT82CRH51A Block Diagram Showing Modem

and Transmitter Buffer and Control Functions

D(7:0)

DATA

BUS

BUFFER

READ/WRITE

CONTROL

LOGIC

MODEM

CONTROL

TRANSMIT

BUFFER

(P-S)

TRANS-

MITTER

CONTROL

RECEIVER

BUFFER

(S-P)

RECEIVER

CONTROL

RESET

CLK

C/D
RD
WR

CS

DSR
DTR

CTS
RTS

TxRDY

TxEMPTY
TxC

TxD

RxD

RxRDY

RxC
SYNDET/

BRKDET

INTERNAL
DATA BUS

5

RxC.
NOTE: In most communications systems, the UT82CRH51A

handles both the transmission and reception operations of a sin­gle link. Consequently, the Receive and Transmit Baud Rates
will be the same. Both TxC and RxC requires identical frequen­cies for this operation and can be tied together and connected to
a single frequency source (Baud Rate Generator) to simplify the
interface.

1.7.3 SYNDET (SYNC Detect/BRKDET Break Detect)

This pin is used in Synchronous Mode for SYNDET and may be
used as either input or output programmable through the Control
Word. It is reset to output mode low upon RESET. When used
as an output (internal Sync mode), the SYNDET pin goes high
to indicate that the UT82CRH51A has located the SYNC char­acter in the Receive mode. If the UT82CRH51A is programmed
to use double Sync characters (bisync), then SYNDET goes high
in the middle of the last bit of the second Sync character. SYN­DET automatically resets upon a Status Read Operation.

When used as an input (external SYNC detect mode), a positive
going signal causes the UT82CRH51A to start assembling data
characters on the rising edge of the next RxC. Once in SYNC,
the "high" input signal can be removed. When External SYNC
Detect is programmed, Internal SYNC Detect is disabled.

1.7.4 BREAK (Async Mode Only)

This output goes high whenever the receiver remains low
through two consecutive stop bit sequences (including the start
bits, data bits, and parity bits). Break Detect may also be read
as a Status bit. It is reset only upon a master chip Reset or Rx
Data returning to a "one" state.

Figure 6. UT82CRH51A Block Diagram Showing

Receiver Buffer and Control Functions

D(7:0)

DATA

BUS

BUFFER

READ/WRITE

CONTROL

LOGIC

MODEM

CONTROL

TRANSMIT

BUFFER

(P-S)

TRANS-

MITTER

CONTROL

RECEIVER

BUFFER

(S-P)

RECEIVER
CONTROL

RESET

CLK
C/D

RD

WR

CS

DSR
DTR

CTS
RTS

TxRDY

TxEMPTY
TxC

TxD

RxD

RxRDY

RxC
SYNDET/

BRKDET

INTERNAL
DATA BUS

CONTROL BUS

ADDRESS BUS

DATA BUS

UT82CRH51A

C/D

CS

D7-D

0

RD

WR

CLKRESET

A

0

I/O R I/O W

RESET

0

2

(TTL)

8

Figure 7. UT82CRH51A Interface to Standard

System Bus

6

2.0 DETAILED OPERATION DESCRIPTION

2.1 General

The complete functional definition of the UT82CRH51A is pro­grammed by the system’s software. A set of control words must
be sent out by the CPU to initialize the UT82CRH51A to sup­port the desired communications format. These control words
will program the: BAUD RATE, CHARACTER LENGTH,
NUMBER OF STOP BITS, SYNCHRONOUS or ASYN­CHRONOUS OPERATION, EVEN/ODD/OFF PARITY, etc.
In the Synchronous Mode, options are also provided to select ei­ther internal or external character synchronization (figure 8).

Once programmed, the UT82CRH51A is ready to perform its
communication functions. The TxRDY output is raised "high"
to signal the CPU the UT82CRH51A is ready to receive a data
character from the CPU. This output (TxRDY) is reset automat­ically when the CPU writes a character into the UT82CRH51A.
On the other hand, the UT82CRH51A receives serial data from
the MODEM or I/O device. Upon receiving an entire character,
the RxRDY output is raised "high" to signal the CPU the
UT82CRH51A has completed character ready for the CPU to
fetch. RxRDY is reset automatically upon the CPU data read
operation.

The UT82CRH51A cannot begin transmission until the TxEn­able (Transmitter Enable) bit is set in the Command Instruction
and it has received a Clear to Send (CTS) input. The TxD output
is held in the marking state upon Reset.

2.2 Programming the UT82CRH51A

Prior to starting data transmission or reception, the
UT82CRH51A must be loaded with a set of control words gen­erated by the CPU. These control signals define the complete

functional definition of the UT82CRH51A and must immediate­ly follow a Reset operation (internal or external).

The control words are split into two formats:

1. Mode Instruction

2. Command Instruction

2.2.1 Mode Instruction

This instruction defines the general operational characteristics
of the UT82CRH51A. It must follow a Reset operation (internal
or external), once the Mode Instruction has been written into the
UT92CRH51A by the CPU, SYNC characters or Command In­structions (figure 8).

2.2.2 Command Instruction

This instruction defines a word that is used to control the actual
operation of the UT82CRH51A.

Both the Mode and Command Instructions must conform to a
specified sequence for proper device operation (see Figure 8).
The Mode Instruction must be written immediately following a
Reset operation prior to using the UT82CRH51A for data com­munication.

All control words written into the UT82CRH51A after the Mode
Instruction loads the Command Instruction. Command Instruc­tions can be written into the UT82CRH51A at any time in the
data block during the operation of the UT82CRH51A. To return
to the Mode Instruction format, the master Reset bit in the Com­mand Instruction word can be set to initiate an internal Reset op­eration which automatically places the UT82CRH51A back into
the Mode Instruction format. Command Instructions must fol­low the Mode Instructions or Sync characters.

2.2.3 Mode Instruction Definition

The UT82CRH51A can be used for either Asynchronous or
Synchronous data communication. To understand how the
Mode Instruction defines the functional operation of the
UT82CRH51A, the designer views the device as two separate
components, one Asynchronous and the other Synchronous,
sharing the same package. The format definition can be
changed only after a master chip Reset. For explanation purpos­es the two formats will be isolated.

NOTE: When parity is enabled it is not considered as one of the
data bits for the purpose of programming the word length. The
actual parity bit received on the Rx Data line cannot be read on
the Data bus. In the case of a programmed character length of
less than 8 bits, the least significant Data Bus bits holds the data;
unused bits are "don’t care" when writing data to the
UT82CRH51A and will be "zeroes" when reading the data from
the UT82CRH51A.

2.2.4 Asynchronous Mode (Transmission)

Whenever a data character is sent by the CPU the
UT82CRH51A automatically adds a Start bit (low level) fol­lowed by the data bits (least significant bit first), and the pro­grammed number of Stop bits to each character. Also, an even
or odd Parity bit is inserted prior to the Stop bit(s) as defined by

MODE INSTRUCTION

SYNC CHARACTER 1

SYNC CHARACTER 2

COMMAND INSTRUCTION

DATA

DATA

COMMAND INSTRUCTION

COMMAND INSTRUCTION

C/D = 1

C/D = 1

C/D = 1

C/D = 1

C/D = 0

C/D = 1

C/D = 0

C/D = 1

SYNC

MODE

ONLY*

NOTE: The second SYNC character is skipped if MODE instruction has programmed
the UT82CRH51A to single character internal SYNC Mode. Both SYNC characters are
skipped if MODE instruction has programmed the UT82CRH51A to ASYNC mode or
External SYNC mode.

Figure 8. Typical Data Block

7

the Mode Instruction. The character is then transmitted as a se­rial data stream on the TxD output. The serial data is shifted out
on the falling edge of TxC at a rate equal to 1, 1/16, or 1/64 that
of the TxC as defined by the Mode Instruction. BREAK char­acters can be continuously sent to the TxD if commanded to do
so.

When no data characters have been loaded into the
UT82CRH51A the TxD output remains "high" (marking) unless
a Break (continuously low) has been programmed (figure 9).

2.2.5 Asynchronous Mode (Receive)

The RxD line is normally high. A falling edge on this line trig­gers the beginning of a START bit. The validity of this START
bit is checked by again strobing this bit at its nominal center
(16x or 64x mode only). If a low is detected again, it is a valid
START bit, and the bit counter starts counting. The bit counter
thus locates the center of the data bits, the parity bit (if it exists),
and the stop bits. If parity error occurs, the parity error flag is
set. Data and parity bits are sampled on the RxD pin with the

rising edge of RxC. If a low level is detected as the STOP bit,
the Framing Error flag sets. The STOP bit signals the end of a
character. Note: The receiver requires only one stop bit regard-
less of the number of stop bits programmed. This character is
then loaded into the parallel I/O buffer of the UT82CRH51A.
The RxRDY pin is raised to signal the CPU that a character is
ready to be fetched. If a previous character has not been fetched
by the CPU, the present character replaces it in the I/O buffer,
and the OVERRUN Error flag is raised (thus the previous char­acter is lost). All of the error flags can be reset by an Error Reset
Instruction. The occurrence of any of these errors will not affect
the operation of the UT82CRH51A (figure 10).

2.2.6 Synchronous Mode (Transmission)

The TxD output is continuously high until the CPU sends its
first character to the UT82CRH51A which usually is a SYNC
character. When the CTS line goes low, the first character is se­rially transmitted out. All characters are shifted out on the fall­ing edge of TxC. Data is shifted out at the same rate as the TxC.

Once transmission has started, the data stream at TxD output
continues at the TxC rate. If the CPU does not provide the
UT82CRH51A with a data character before the UT82CRH51A
Transmitter Buffers become empty, the SYNC characters (or
character if in single SYNC character mode) will be automati­cally inserted in the TxD data stream. In this case, the TxEMP­TY pin is raised high to signal that the UT82CRH51A is empty
and SYNC characters are being sent out. TxEMPTY does not
go low when the SYNC is being shifted out (see figure 11). The
TxEMPTY pin is internally reset by a data character being writ­ten into the UT82CRH51A.

S2S

1

EP

PEN

L

2L1

B

2

B

1

D

5

D

6

D

7

D4D3D

2

D1D

0

0

SYNC

MODE

0

1

(1X)

0

0

(16X)

1

1

1

(64X)

BAUD RATE FACTOR

0

5

BITS

0

1

6

BITS

0

0

7

BITS

1

1
1

8

BITS

CHARACTER LENGTH

PARITY ENABLE

1 = ENABLE 0 = DISABLE

EVEN PARITY

GENERATION/CHECK

1 = EVEN 0= ODD

0

INVALID

0

1

1

BITS

0

0

1 1/2
BITS

1

1
1

2

BITS

NUMBER OF STOP BITS

(ONLY AFFECTS Tx:Rx

NEVER REQUIRES MORE

THAN ONE STOP BIT)

Figure 9. Mode and Command Instruction Format,

Asynchronous Node

S2S

1

EP

PEN

L

2L1

B

2

B

1

D

5

D

6

D

7

D4D3D

2

D1D

0

0

SYNC

MODE

0

1

(1X)

0

0

(16X)

1

1

1

(64X)

BAUD RATE FACTOR

0

5

BITS

0

1

6

BITS

0

0

7

BITS

1

1
1

8

BITS

CHARACTER LENGTH

PARITY ENABLE

1 = ENABLE 0 = DISABLE

0

INVALID

0

1

1

BITS

0

0

1 1/2
BITS

1

1
1

2

BITS

NUMBER OF STOP BITS

Figure 11. Synchronous Mode

DATA

DATA

SYNC 1 SYNC 2

DATA

- - - - - -

TxD

AUTOMATICALLY INSERTED BY USART

TxEMPTY

NOMINAL CENTER OF LAST BIT

FALLS UPON CPU

WRITING A

CHARACTER TO

THE USART

8

2.2.7 Synchronous Mode (Receive)

In this mode, character synchronization can be internally or ex­ternally achieved. If the SYNC mode has been programmed, an
ENTER HUNT command should be included in the first com­mand instruction word written. Data on the RxD pin is then
sampled on the rising edge of RxC. The content of the Rx buffer
is compared at every bit boundary with the first SYNC character
until a match occurs. If the UT82CRH51A has been pro­grammed for two SYNC characters, the subsequent received
character is also compared; when both SYNC characters have
been detected, the USART ends the HUNT mode and is in char­acter synchronization. The SYNDET pin is then set high and is
reset automatically by a STATUS READ. If parity is pro­grammed, SYNDET will not be set until the middle of the parity
bit instead of the middle of the last data bit.

In the external SYNC mode, synchronization is achieved by ap­plying a high level of the SYNDET pin, thus forcing the
UT82CRH51A out of the HUNT mode. The high level can be
removed after one RxC cycle. An ENTER HUNT command has
no effect in the asynchronous mode of operation.

Parity error and overrun error are both checked in the same way
as in the Asynchronous Rx mode. Parity is checked when not in
HUNT, regardless of whether the Receiver is enabled or not
(Figure 12).

The CPU can command the receiver to enter the HUNT mode if
synchronization is lost. This will also set all the used character
bits in the buffer to a "one", thus preventing a possible false
SYNDET caused by data that happens to be in the Rx Buffer at
ENTER HUNT time. Note: The SYNDET F/F is reset at each
Status Read regardless of whether internal or external sync has
been programmed. This does not cause the UT82CRH51A to
return to the HUNT mode. When the SYNC mode but not in
HUNT, Sync Detection is still functional, but only occurs at the
"known" word boundaries. Thus, if one Status Read indicates
SYNDET and a second Status Read also indicates SYNDET,
then the programmed SYNDET characters have been received
since the previous Status Read. (If double character sync has
been programmed, then both sync characters have been contig­uously received to gate a SYNDET indication.) When external
SYNDET mode is selected, internal Sync Detection is disabled,
and the SYNDET F/F may be set at any bit boundary (figure 13).

TRANSMITTER OUTPUT

START

BIT

DATA BITS

PARITY BITS

STOP BITS

D0 D1 --------------D

x

Generated by

UT82CRH51A

MARKING

TxD

RECEIVER INPUT

START

BIT

DATA BITS

PARITY BITS

STOP BITS

D0 D1 --------------D

x

DOES NOT APPEAR ON

THE DATA BUS

RxD

PROGRAMMED CHARACTER

LENGTH

TRANSMISSION FORMAT

DATA CHARACTER

CPU BYTE (5-8 BITS/CHAR)

START

BIT

DATA CHARACTER

PARITY BITS

STOP BITS

ASSEMBLED SERIAL DATA OUTPUT (TxD)

START

BIT

DATA CHARACTER

PARITY BITS

STOP BITS

SERIAL DATA INPUT (RxD)

RECEIVE FORMAT

DATA CHARACTER

CPU BYTE (5-8 BITS/CHAR)

*Note: If character length is defined

as 5,6 or 7 bits, the unused bits are

set to "ZERO"

Figure 10. Asynchronous Mode

}