UTMC 5962P9960602QUX, 5962P9960602QUC, 5962P9960602QUA, 5962P9960601TUX, 5962P9960601TUC Datasheet

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UTMC 5962P9960602QUX, 5962P9960602QUC, 5962P9960602QUA, 5962P9960601TUX, 5962P9960601TUC Datasheet

Standard Products

QCOTSTM UT7Q512 512K x 8 SRAM

Data Sheet

August, 2002

FEATURES

q100ns (5 volt supply) maximum address access time

qAsynchronous operation for compatibility with industrystandard 512K x 8 SRAMs

qTTL compatible inputs and output levels, three-state bidirectional data bus

qTypical radiation performance

-Total dose: 30krad(Si)

-30krad(Si) to 300krad(Si), depending on orbit, using Aeroflex UTMC patented shielded package

-SEL Immune >80 MeV-cm2 /mg

-LETTH(0.25) = 5MeV-cm 2/mg

-Saturated Cross Section (cm2) per bit, ~1.0E-7

-1.5E-8 errors/bit-day, Adams 90% geosynchronous

heavy ion

qPackaging options:

-32-lead ceramic flatpack (weight 2.5-2.6 grams)

qStandard Microcircuit Drawing 5962-99606

-QML T and Q compliant

INTRODUCTION

The QCOTST M UT7Q512 Quantified Commercial Off-the- Shelf product is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (E), an active LOW Output Enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected.

Writing to the device is accomplished by taking the Chip Enable One ( E) input LOW and the Write Enable ( W) input LOW. Data on the eight I/O pins (DQ0 through DQ7) is then

written into the location specified on the address pins (A0 through A1 8). Reading from the device is accomplished by

taking Chip Enable One (E) and Output Enable (G) LOW while forcing Write Enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the eight I/O pins.

The eight input/output pins (DQ0 through DQ7) are placed

in a high impedance state when the device is deselected (E, HIGH), the outputs are disabled (G HIGH), or during a write operation (E LOW and W LOW).

Clk. Gen. Pre-Charge Circuit

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Array

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A2

 

 

 

Select

 

 

 

 

 

1024 Rows

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

512x8 Columns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

 

 

 

 

 

 

 

 

 

 

 

A4

 

 

 

Row

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O Circuit

 

 

A9

 

 

 

 

 

 

 

 

 

Column Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ0

- DQ 7

Data

 

 

 

 

 

 

 

 

 

Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

A10

A11

A12

A13

A14

A15

A16

A17

A18

 

 

Gen.

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

W

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

 

 

Figure 1. UT7Q512 SRAM Block Diagram

 

 

 

 

 

 

 

PIN NAMES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A(18:0)

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ(7:0)

 

Data Input/Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

Chip Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

 

Write Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G

 

Output Enable

 

 

 

 

 

 

 

 

 

 

 

VDD

 

Power

 

 

 

 

VSS

 

Ground

 

 

 

A18

 

 

 

 

 

 

 

 

NC

 

 

1

 

 

36

 

 

 

 

 

 

A16

 

 

2

 

 

35

 

 

A15

 

 

 

 

 

 

 

 

 

A14

 

 

3

 

 

34

 

 

A17

 

 

 

 

 

 

 

 

 

A12

 

 

4

 

 

33

 

 

W

 

 

 

 

 

 

 

 

 

A7

 

 

5

 

 

32

 

 

A13

 

 

 

 

 

 

 

 

 

A6

 

 

6

 

 

31

 

 

A8

 

 

 

 

 

 

 

 

 

A5

 

 

7

 

 

30

 

 

A9

 

 

 

 

 

 

 

 

 

A4

 

 

8

 

 

29

 

 

A11

 

 

 

 

 

 

 

 

 

VDD

 

 

9

 

 

28

 

 

VS S

 

 

 

 

 

 

 

 

 

VSS

 

 

10

 

 

27

 

 

VD D

 

 

 

 

 

 

 

 

 

A3

 

 

11

 

 

26

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

A2

 

 

12

 

 

25

 

 

A10

 

 

 

 

 

 

 

 

 

A1

 

 

13

 

 

24

 

 

E

 

 

 

 

 

 

 

 

 

A0

 

 

14

 

 

23

 

 

DQ7

 

 

 

 

 

 

 

 

 

DQ0

 

 

15

 

 

22

 

 

DQ6

 

 

 

 

 

 

 

 

 

DQ1

 

 

16

 

 

21

 

 

DQ5

 

 

 

 

 

 

 

 

 

DQ2

 

 

17

 

 

20

 

 

DQ4

 

 

 

 

 

 

 

 

 

DQ3

 

 

18

 

 

19

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2a. UT7Q512 100ns SRAM Shielded

Package Pinout (36)

A18

 

 

1

32

 

 

VD D

 

 

A16

 

2

31

 

 

A15

 

 

 

A14

 

 

 

 

 

 

3

30

 

 

A17

 

 

 

 

 

A12

 

 

 

 

 

 

 

 

4

29

 

 

W

 

 

 

A7

 

 

 

 

 

 

5

28

 

 

A13

 

 

 

 

 

A6

 

6

27

 

 

A8

 

 

 

A5

 

 

 

 

 

 

7

26

 

 

A9

 

 

 

A4

 

 

8

25

 

 

A11

 

 

 

 

 

A3

 

 

 

 

 

 

 

 

9

24

 

 

G

 

 

 

A2

 

 

 

 

 

 

10

23

 

 

A10

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

11

22

 

 

E

 

 

 

A0

 

 

 

 

 

 

12

21

 

 

DQ7

 

 

 

 

 

DQ0

 

13

20

 

 

DQ6

 

 

 

DQ1

 

 

 

 

 

 

14

19

 

 

DQ5

 

 

 

 

 

DQ2

 

15

18

 

 

DQ4

 

 

 

VSS

 

 

 

 

 

 

16

17

 

 

DQ3

 

 

 

 

 

Figure 2b. UT7Q512 100ns SRAM

Package Pinout (32)

DEVICE OPERATION

The UT7Q512 has three control inputs called Enable 1 ( E), Write Enable ( W), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). The E Device Enable controls device selection, active, and standby modes. Asserting E enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

 

 

 

 

 

 

 

 

 

 

 

 

G

W

 

E

I/O Mode

Mode

 

 

 

 

 

 

 

 

 

 

 

X1

 

X

1

 

3-state

Standby

 

X

0

 

0

 

Data in

Write

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

0

 

3-state

Read2

 

 

 

 

 

 

 

 

 

 

 

0

 

1

 

0

 

Data out

Read

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.“X” is defined as a “don’t care” condition.

2.Device active; outputs disabled.

READ CYCLE

A combination of W greater than VIH (min), G and E less than VIL (max) defines a read cycle. Read access time is measured from the latter of DeviceEnable, Output Enable, or valid address to valid data output.

SRAM read Cycle 1, the Address Access in figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as Device Enable and Output Enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV).

SRAM read Cycle 2, the Chip Enable-Controlled Access in figure 3b, is initiated by E going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0).

SRAM read Cycle 3, the Output Enable-Controlled Access in figure 3c, is initiated by G going active while E is asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless t AVQV or tETQV have not been satisfied.

2

WRITE CYCLE

A combination of W less than VIL(max) and E less than

VIL(max) defines a write cycle. The state of G is a “don’t care” for a write cycle. The outputs are placed in the high-impedance state when either G is greater than V IH(min), or when W is less than VIL(max).

Write Cycle 1, the Write Enable-Controlled A ccess in figure 4a, is defined by a write terminated by W going high, with E still active. The write pulse width is defined by tWLWH when the

write is initiated by W, and by t ETWH when the write is initiated

by E. Unless the outputs have been previously placed in the highimpedance state byG, the user must wait t WLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention.

Write Cycle 2, the Chip Enable-Controlled Access in figure 4b, is defined by a write terminated by the latter of E going inactive. The write pulse width is defined by tWLEF when the write is

initiated by W, and by tETEF when the write is initiated by the

E going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state

by G, the user must wait t WLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention.

TYPICAL RADIATION HARDNESS

Table 2. Typical Radiation Hardness

Design Specifications1

Total Dose

30

krad(Si) nominal

 

 

 

Heavy Ion

1.5E-7

Errors/Bit-Day

Error Rate2

 

 

 

 

 

Notes:

1.The SRAM will not latchup during radiation exposure under recommended operating conditions.

2.9 0% worst case particle environment, Geosynchronous orbit, 100 m ils of Aluminum.

3

ABSOLUTE MAXIMUM RATINGS1

(Referenced to VSS)

SYMBOL

PARAMETER

LIMITS

 

 

 

VDD

DC supply voltage

-0.5 to 7.0V

VI/O

Voltage on any pin

-0.5 to 7.0V

TSTG

Storage temperature

-65 to +150°C

PD

Maximum power dissipation

1.0W

TJ

Maximum junction temperature2

+150°C

 

 

 

ΘJC

Thermal resistance, junction-to-case3

10°C/W

II

DC input current

±10 mA

 

 

 

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.

2.Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3.Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

 

 

 

VDD

Positive supply voltage

4.5 to 5.5V

TC

Case temperature range

-55 to +125°C

 

 

 

VIN

DC input voltage

0V to VDD

4

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(VDD = 5.0V±10%) (-55°C to +125°C)

SYMBOL

PARAMETER

 

 

CONDITION

 

MIN

MAX

UNIT

 

 

 

 

 

 

 

 

 

VIH

High-level input voltage

 

 

 

 

2.2

 

V

VIL

Low-level input voltage

 

 

 

 

 

.8

V

VOL

Low-level output voltage

 

IOL = 2.1mA,VDD =4.5V

 

 

0.4

V

VOH

High-level output voltage

 

IOH = -1mA,VDD =4.5V

 

2.4

 

V

1

Input capacitance

 

¦ = 1MHz @ 0V

 

 

10

pF

CIN

 

 

 

 

 

 

 

 

1

Bidirectional I/O capacitance

 

¦ = 1MHz @ 0V

 

 

10

pF

CIO

 

 

 

 

 

 

 

 

IIN

Input leakage current

 

VSS < VIN < VDD , VDD = VDD (max)

-2

2

mA

IOZ

Three-state output leakage current

 

0V < VO < VDD

 

-2

2

mA

 

 

 

VDD = VDD (max)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G = V DD (max)

 

 

 

 

 

 

 

 

 

 

 

 

I 2, 3

Short-circuit output current

 

0V <VO <VDD

 

-80

80

mA

OS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDD(OP)

Supply current operating

 

Inputs: VIL = VSS + 0.8V,

 

 

50

mA

 

@ 1MHz

 

VIH = 2.2V

 

 

 

 

 

 

 

IOUT = 0mA

 

 

 

 

 

 

 

VDD = VDD (max)

 

 

 

 

 

 

 

 

 

 

 

 

IDD1(OP)

Supply current operating

 

Inputs: V IL = VSS + 0.8V,

 

 

100

mA

 

@10MHz

 

VIH = 2.2V

 

 

 

 

 

 

 

IOUT = 0mA

 

 

 

 

 

 

 

VDD = VDD (max)

 

 

 

 

 

 

 

 

 

 

 

 

IDD2(SB)

Nominal standby supply current

 

Inputs: V IL = VSS

-55°C and

 

 

 

 

@0MHz

 

IOUT = 0mA

25°C

 

35

mA

 

 

 

 

 

 

 

 

 

 

 

 

E = VDD - 0.5

 

 

 

 

 

 

 

+125°C

 

1

mA

 

 

 

VDD = VDD (max)

 

 

 

 

 

 

 

 

 

 

 

VIH = VDD - 0.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 .

1.Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2.Supplied as a design limit but not guaranteed or tested.

3.Not more than one output may be shorted at a time for maximum duration of one second.

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