UTMC 5962RTBD02VYX, 5962RTBD02VYC, 5962RTBD02VYA, 5962RTBD02QYX, 5962RTBD02QYC Datasheet

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Standard Products

UT54LVDS032LVT Low Voltage Quad Receiver with Integrated Termination Resistor

Preliminary Data Sheet

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

February 14, 2003

FEATURES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTRODUCTION

q >400.0 Mbps (200 MHz) switching rates

 

 

 

 

 

 

 

 

 

 

 

 

The UT54LVDS032LV Quad Receiver is a quad CMOS

 

 

 

 

 

 

 

 

 

 

 

 

differential line receiver designed for applications requiring

q +340mV differential signaling

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ultra low power dissipation and high data rates. The device is

q 3.3 V power supply

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

designed to support data rates in excess of 400.0 Mbps (200

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MHz) utilizing Low Voltage Differential Signaling (LVDS)

q TTL compatible outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

technology.

 

 

 

 

 

 

 

 

 

q Cold spare all pins

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The UT54LVDS032LV accepts low voltage (340mV)

q Nominal 105Ω Integrated Termination Resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

differential input signals and translates them to 5V TTL o utput

q 3.3ns maximum propagation delay

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

levels. The receiver supports a three-state function that may be

q 0.35ns maximum differential skew

 

 

 

 

 

 

 

 

 

 

 

 

used to multiplex outputs. The receiver also supports OPEN,

 

 

 

 

 

 

 

 

 

 

 

 

shorted and terminated (100 Ω) input fail-safe. Receiver output

q Radiation-hardened design; total dose irradiation testing to

 

 

 

 

 

 

will be HIGH for all fail-safe conditions.

MIL-STD-883 Method 1019

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

- Total-dose: 300 krad(Si) and 1Mrad(Si)

 

 

 

 

 

 

 

 

 

 

 

 

The UT54LVDS032LV and companion quad line driver

- Latchup immune (LET > 100 MeV-cm2 /mg)

 

 

 

 

 

 

 

UT54LVDS031LV provides new alternatives to high power

 

 

 

 

 

 

 

pseudo-ECL devices for high speed point-to-point interface

q Packaging options:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

applications.

 

 

 

 

 

 

 

 

T

- 16-lead flatpack (dual in-line)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

q Standard Microcircuit Drawing TBD

 

 

 

 

 

 

 

 

 

 

 

 

All pins have Cold Spare buffers. These buffers will be high

 

 

 

 

 

 

 

 

 

 

 

 

impedance when V DD is tied to VSS.

- QML Q and V compliant part

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

 

 

 

 

 

 

 

 

 

 

 

 

An integrated termination resistor will reduce component count

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

q Compatible with IEEE 1596.3SCI LVDS

 

 

 

 

 

 

 

 

 

 

 

 

and save boardEspace.

q Compatible with ANSI/TIA/EIA 644-1996 LVDS

 

 

 

 

 

 

 

 

 

 

M

Standard

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RIN1+

 

 

 

 

+

R1

ROUT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RIN1-

 

 

 

O-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RIN2+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

R 2

ROUT2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RIN2-

 

 

 

 

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RIN3+

 

 

 

 

+

 

 

 

 

 

 

 

ROUT3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

RIN3-

 

 

 

 

 

 

 

R 3

 

 

N

 

 

 

 

 

 

 

 

 

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RIN4+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ROUT4

 

 

 

 

 

 

 

 

+

R 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

RIN4-

 

 

 

 

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EN

EN

Figure 1. UT54LVDS032LV Quad Receiver Block Diagram

1

RIN1-

1

 

16

VDD

RIN1+

2

 

15

RIN4-

ROUT1

3

UT54LVDS032LV

14

RIN4+

EN

4

13

ROUT4

Receiver

ROUT2

5

 

12

EN

RIN2+

6

 

11

ROUT3

RIN2-

7

 

10

RIN3+

VSS

8

 

9

R I N 3 -

Figure 2. UT54LVDS032LVT Pinout

APPLICATIONS INFORMATION

The UT54LVDS032LVT receiver’s intended use is primarily in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling environment for quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100Ω. An integrated termination resistor of 105Ω is used to match the media . The termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account.

TRUTH TABLE

 

 

 

 

 

 

 

 

ENABLE

 

 

1/4 UT54LVDS032LV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

RT 100Ω

 

 

+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Enables

 

 

 

Input

 

Output

 

 

INPUT

 

T

 

 

-

 

DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

EN

 

 

EN

 

RIN+ - RIN-

ROUT

 

 

1/4 UT54LVDS031LV

N

 

 

 

 

 

 

L

 

 

H

 

 

X

 

Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3. Point-to-Point Application

 

 

 

All other combinations

 

VID > 0.1V

H

 

 

E

 

 

 

 

 

 

of ENABLE inputs

 

VID < -0.1V

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Full Fail-safe

H

 

 

The UT54LVDS032LVT differential line receiver is capable of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OPEN/SHORT or

 

 

 

 

M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

detecting signals as low as 100mV, over a + 1V common-mode

 

 

 

 

 

Terminated

 

 

 

 

rangePcentered around +1.2V. This is related to the driver offset

 

 

 

 

 

 

 

 

 

 

 

 

PIN DESCRIPTION

 

 

 

 

 

 

 

 

voltage which is typically +1.2V. The driven signal is centered

 

 

 

 

 

 

 

 

around this voltage and may shift +1V around this center point.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin No.

 

Name

 

 

Description

 

L

The +1V shifting may be the result of a ground potential

 

 

 

 

difference between the driver’s ground reference and the

2, 6, 10, 14

 

 

RIN+

 

 

 

 

 

 

 

 

 

 

 

 

 

 

receiver’s ground reference, the common-mode effects of

 

 

 

Non-inverting receiver input pin

 

1, 7, 9, 15

 

 

RIN-

 

 

 

 

 

E

 

coupled noise or a combination of the two. Both receiver input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Inverting receiver input pin

 

pins should honor their specified operating input voltage range

 

 

 

 

 

 

 

 

 

 

 

 

3, 5, 11, 13

 

 

ROUT

 

 

Receiver output pin

 

 

of 0V to +2.4V (measured from each pin to ground).

 

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

4

 

 

EN

 

Active high enable pin, OR-ed

 

The integrated termination resistor is a nominal 105Ω when V DD

 

 

 

 

 

 

E

 

 

 

is 3.0 to 3.6V. In cold spare mode, the integrated termination

 

 

 

 

 

 

 

with EN

 

 

 

12

 

 

EN

 

Active low enable pin, OR-ed

 

resistor is 145Ω.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

with EN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

VDD

 

Power supply pin, +3.3 + 0.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

I

 

Ground pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

2. Terminated Input. If the driver is disconnected

Receiver Fail-Safe

 

(cable unplugged), or if the driver is in a three-state

 

or power-off condition, the receiver output will again

 

 

The UT54LVDS032LVT receiver is a high gain, high speed

be in a HIGH state, even with the end of cable 100Ω

device that amplifies a small differential signal (20mV) to

integrated termination resistor across the input pins.

TTL logic levels. Due to the high gain and tight threshold of

The unplugged cable can become a floating antenna

which can pick up noise. If the cable picks up more

the receiver, care should be taken to prevent noise from

appearing as a valid signal.

 

than 10mV of differential noise, the receiver may see

The receiver’s internal fail-safe circuitry is designed to

the noise as a valid signal and switch. To insure that

any noise is seen as common-mode and not

source/sink a small amount of current, providing fail-safe

differential, a balanced interconnect should be used.

protection (a stable known state of HIGH output voltage) for

Twisted pair cable offers better balance than flat

floating, terminated or shorted receiver inputs.

ribbon cable.

 

1. Open Input Pins. The UT54LVDS032LVT is a quad

3. Shorted Inputs. If a fault condition occurs that shorts

receiver device, and if an application requires only 1,

the receiver inputs together, thus resulting in a 0V

2 or 3 receivers, the unused channel(s) inputs should

differential input voltage, the receiver output remains

be left OPEN. Do not tie unused receiver inputs to

in a HIGH state. Shorted input fail-safe is not

ground or any other voltages. The input is biased by

supported across the common-mode range of the

internal high value pull up and pull down resistors to

device (VSS to 2.4V). It is only supported with inputs

set the output to a HIGH state. This internal circuitry

 

T

will guarantee a HIGH, stable output state for open

shorted and no external common-mode voltage

applied.

 

inputs.

 

N

 

 

 

 

 

 

 

E

 

 

M

 

 

 

P

 

 

 

O

 

 

L

 

 

E

 

 

 

V

 

 

 

E

 

 

N

D

 

 

 

 

 

I

 

 

 

3

UTMC 5962RTBD02VYX, 5962RTBD02VYC, 5962RTBD02VYA, 5962RTBD02QYX, 5962RTBD02QYC Datasheet

ABSOLUTE MAXIMUM RATINGS1

(Referenced to VSS)

SYMBOL

PARAMETER

LIMITS

VDD

DC supply voltage

-0.3 to 4.0V

VI/O

Voltage on any pin during operation

-0.3 to (VDD + 0.3V)

 

Voltage on any pin during cold spare

-.3 to 4.0V

TSTG

Storage temperature

-65 to +150°C

PD

Maximum power dissipation

1.25 W

TJ

Maximum junction temperature2

+150°C

ΘJC

Thermal resistance, junction-to-case3

10°C/W

II

DC input current

±10mA

 

 

 

1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only,Tand functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended.N Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. E

RECOMMENDED OPERATING CONDITIONS

 

 

 

 

 

SYMBOL

 

PARAMETER

 

LIMITS

 

 

 

 

VDD

 

Positive supply voltage

P

3.0 to 3.6V

 

 

 

M

 

 

IN

 

 

O

 

-55 to +125°C

 

TC

 

Case temperature range

 

 

 

V

 

 

L

 

 

2.4V

 

 

 

DC input voltage, receiver inputs

 

 

 

 

E

 

 

 

0 to VDD for EN, EN

 

 

 

 

DC input voltage, logic inputs

 

 

 

 

 

V

 

 

 

 

 

 

 

E

 

 

 

 

 

 

N

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

4

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