Standard Products
UT54LVDS032LVT Low Voltage Quad Receiver with Integrated Termination Resistor
Preliminary Data Sheet
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February 14, 2003 |
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FEATURES |
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INTRODUCTION |
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q >400.0 Mbps (200 MHz) switching rates |
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The UT54LVDS032LV Quad Receiver is a quad CMOS |
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differential line receiver designed for applications requiring |
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q +340mV differential signaling |
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ultra low power dissipation and high data rates. The device is |
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q 3.3 V power supply |
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designed to support data rates in excess of 400.0 Mbps (200 |
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MHz) utilizing Low Voltage Differential Signaling (LVDS) |
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q TTL compatible outputs |
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technology. |
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q Cold spare all pins |
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The UT54LVDS032LV accepts low voltage (340mV) |
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q Nominal 105Ω Integrated Termination Resistor |
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differential input signals and translates them to 5V TTL o utput |
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q 3.3ns maximum propagation delay |
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levels. The receiver supports a three-state function that may be |
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q 0.35ns maximum differential skew |
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used to multiplex outputs. The receiver also supports OPEN, |
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shorted and terminated (100 Ω) input fail-safe. Receiver output |
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q Radiation-hardened design; total dose irradiation testing to |
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will be HIGH for all fail-safe conditions. |
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MIL-STD-883 Method 1019 |
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- Total-dose: 300 krad(Si) and 1Mrad(Si) |
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The UT54LVDS032LV and companion quad line driver |
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- Latchup immune (LET > 100 MeV-cm2 /mg) |
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UT54LVDS031LV provides new alternatives to high power |
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pseudo-ECL devices for high speed point-to-point interface |
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q Packaging options: |
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applications. |
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T |
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- 16-lead flatpack (dual in-line) |
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q Standard Microcircuit Drawing TBD |
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All pins have Cold Spare buffers. These buffers will be high |
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impedance when V DD is tied to VSS. |
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- QML Q and V compliant part |
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N |
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An integrated termination resistor will reduce component count |
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q Compatible with IEEE 1596.3SCI LVDS |
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and save boardEspace. |
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q Compatible with ANSI/TIA/EIA 644-1996 LVDS |
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M |
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Standard |
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P |
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RIN1+ |
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+ |
R1 |
ROUT1 |
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RIN1- |
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O- |
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L |
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RIN2+ |
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+ |
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E |
R 2 |
ROUT2 |
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RIN2- |
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- |
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E |
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V |
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RIN3+ |
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+ |
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ROUT3 |
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D |
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RIN3- |
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R 3 |
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N |
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- |
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RIN4+ |
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ROUT4 |
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+ |
R 4 |
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I |
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RIN4- |
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- |
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EN
EN
Figure 1. UT54LVDS032LV Quad Receiver Block Diagram
1
RIN1- |
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16 |
VDD |
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RIN1+ |
2 |
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15 |
RIN4- |
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ROUT1 |
3 |
UT54LVDS032LV |
14 |
RIN4+ |
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EN |
4 |
13 |
ROUT4 |
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Receiver |
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ROUT2 |
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12 |
EN |
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RIN2+ |
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11 |
ROUT3 |
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RIN2- |
7 |
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10 |
RIN3+ |
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VSS |
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9 |
R I N 3 - |
Figure 2. UT54LVDS032LVT Pinout
APPLICATIONS INFORMATION
The UT54LVDS032LVT receiver’s intended use is primarily in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling environment for quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100Ω. An integrated termination resistor of 105Ω is used to match the media . The termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account.
TRUTH TABLE |
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ENABLE |
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1/4 UT54LVDS032LV |
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DATA |
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RT 100Ω |
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+ |
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Enables |
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Input |
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Output |
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INPUT |
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T |
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- |
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DATA |
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OUTPUT |
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EN |
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EN |
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RIN+ - RIN- |
ROUT |
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1/4 UT54LVDS031LV |
N |
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L |
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H |
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X |
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Z |
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Figure 3. Point-to-Point Application |
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All other combinations |
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VID > 0.1V |
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E |
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of ENABLE inputs |
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VID < -0.1V |
L |
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Full Fail-safe |
H |
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The UT54LVDS032LVT differential line receiver is capable of |
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OPEN/SHORT or |
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M |
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detecting signals as low as 100mV, over a + 1V common-mode |
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Terminated |
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rangePcentered around +1.2V. This is related to the driver offset |
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PIN DESCRIPTION |
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voltage which is typically +1.2V. The driven signal is centered |
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around this voltage and may shift +1V around this center point. |
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O |
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Pin No. |
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Name |
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Description |
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L |
The +1V shifting may be the result of a ground potential |
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difference between the driver’s ground reference and the |
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2, 6, 10, 14 |
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RIN+ |
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receiver’s ground reference, the common-mode effects of |
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Non-inverting receiver input pin |
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1, 7, 9, 15 |
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RIN- |
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E |
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coupled noise or a combination of the two. Both receiver input |
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Inverting receiver input pin |
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pins should honor their specified operating input voltage range |
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3, 5, 11, 13 |
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ROUT |
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Receiver output pin |
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of 0V to +2.4V (measured from each pin to ground). |
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V |
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4 |
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EN |
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Active high enable pin, OR-ed |
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The integrated termination resistor is a nominal 105Ω when V DD |
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E |
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is 3.0 to 3.6V. In cold spare mode, the integrated termination |
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with EN |
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12 |
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EN |
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Active low enable pin, OR-ed |
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resistor is 145Ω. |
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D |
with EN |
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VDD |
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Power supply pin, +3.3 + 0.3V |
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8 |
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Ground pin |
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VSS |
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2
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2. Terminated Input. If the driver is disconnected |
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Receiver Fail-Safe |
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(cable unplugged), or if the driver is in a three-state |
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or power-off condition, the receiver output will again |
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The UT54LVDS032LVT receiver is a high gain, high speed |
be in a HIGH state, even with the end of cable 100Ω |
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device that amplifies a small differential signal (20mV) to |
integrated termination resistor across the input pins. |
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TTL logic levels. Due to the high gain and tight threshold of |
The unplugged cable can become a floating antenna |
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which can pick up noise. If the cable picks up more |
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the receiver, care should be taken to prevent noise from |
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appearing as a valid signal. |
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than 10mV of differential noise, the receiver may see |
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The receiver’s internal fail-safe circuitry is designed to |
the noise as a valid signal and switch. To insure that |
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any noise is seen as common-mode and not |
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source/sink a small amount of current, providing fail-safe |
differential, a balanced interconnect should be used. |
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protection (a stable known state of HIGH output voltage) for |
Twisted pair cable offers better balance than flat |
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floating, terminated or shorted receiver inputs. |
ribbon cable. |
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1. Open Input Pins. The UT54LVDS032LVT is a quad |
3. Shorted Inputs. If a fault condition occurs that shorts |
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receiver device, and if an application requires only 1, |
the receiver inputs together, thus resulting in a 0V |
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2 or 3 receivers, the unused channel(s) inputs should |
differential input voltage, the receiver output remains |
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be left OPEN. Do not tie unused receiver inputs to |
in a HIGH state. Shorted input fail-safe is not |
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ground or any other voltages. The input is biased by |
supported across the common-mode range of the |
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internal high value pull up and pull down resistors to |
device (VSS to 2.4V). It is only supported with inputs |
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set the output to a HIGH state. This internal circuitry |
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T |
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will guarantee a HIGH, stable output state for open |
shorted and no external common-mode voltage |
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applied. |
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inputs. |
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E |
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M |
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P |
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O |
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E |
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V |
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D |
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3
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL |
PARAMETER |
LIMITS |
VDD |
DC supply voltage |
-0.3 to 4.0V |
VI/O |
Voltage on any pin during operation |
-0.3 to (VDD + 0.3V) |
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Voltage on any pin during cold spare |
-.3 to 4.0V |
TSTG |
Storage temperature |
-65 to +150°C |
PD |
Maximum power dissipation |
1.25 W |
TJ |
Maximum junction temperature2 |
+150°C |
ΘJC |
Thermal resistance, junction-to-case3 |
10°C/W |
II |
DC input current |
±10mA |
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1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only,Tand functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended.N Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. E
RECOMMENDED OPERATING CONDITIONS |
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SYMBOL |
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PARAMETER |
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LIMITS |
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VDD |
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Positive supply voltage |
P |
3.0 to 3.6V |
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M |
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IN |
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O |
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-55 to +125°C |
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TC |
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Case temperature range |
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V |
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L |
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2.4V |
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DC input voltage, receiver inputs |
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E |
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0 to VDD for EN, EN |
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DC input voltage, logic inputs |
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V |
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E |
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N |
D |
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I |
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4