Standard Products
UT7C138/139 4Kx8/9 Radiation-Hardened
Dual-Port Static RAM with Busy Flag
Data Sheet
January 2002
FEATURES
q45ns and 55ns maximum address access time
qAsynchronous operation for compatibility with industrystandard 4K x 8/9 dual-port static RAM
qCMOS compatible inputs, TTL/CMOS compatible output levels
qThree-state bidirectional data bus
qLow operating and standby current
qRadiation-hardened process and design; total dose irradiation testing to MIL-STD-883 Method 1019
-Total-dose: 1.0E6 rads(Si)
-Memory Cell LET threshold: 85 MeV-cm2 /mg
-Latchup immune (LET >100 MeV-cm2 /mg)
qQML Q and QML V compliant part
qPackaging options:
-68-lead Flatpack
-68-pin PGA
q5-volt operation
qStandard Microcircuit Drawing 5962-96845
INTRODUCTION
The UT7C138 and UT7C139 are high-speed radiationhardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs. Arbitration schemes are included on the UT7C138/139 to handle situations when multiple processors access the same memory location. Two ports provide independent, asynchronous access for reads and writes to any location in memory. The UT7C138/139 can be utilized as a stand-alone 32/36-Kbit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/ slave dual-port static RAM. For applications that require depth expansion, the BUSY pin is open-collector allowing for wired OR circuit configuration. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications, and status buffering.
Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable ( OE). BUSY signals that the port is trying to access the same location currently being accessed by the other port.
R/WL |
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R/WR |
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CE L |
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CE R |
OEL |
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OER |
A11L |
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A11R |
A10L |
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A10R |
I/O 8L (7C139) |
COL |
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COL |
I/O8R (7C139) |
I/O 7L |
COLUMN |
COLUMN |
I/O7R |
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I/O 0L |
SEL |
I/O |
I/O |
SEL |
I/O0R |
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BUSYL |
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BUSY R |
A9L |
ROW |
MEMORY |
ROW |
A |
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SELECT |
ARRAY |
SELECT |
9R |
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A0L |
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A0R |
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M/S |
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ARBITRATION |
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Figure 1. Logic Block Diagram
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VDD
GND
I/O0R
I/O1R
I/O2R
VDD
I/O3R
I/O4R
I/O5R
I/O6R
Notes:
1.I/O8R on the7C139
2.I/O8L on the 7C139
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1L |
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0L |
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L |
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R/W |
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L |
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DD |
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I/O |
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I/O |
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NC |
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OE |
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NC |
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CE |
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NC |
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NC |
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NC |
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A11 |
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A10 |
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A9 |
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A8 |
A7 |
A6 |
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7C138/139 |
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7R |
(1) |
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R |
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R |
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GND |
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11R |
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10R |
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R/W |
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R |
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9R |
8R |
7R |
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6R |
5R |
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I/O |
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NC |
OE |
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NC |
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CE |
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NC |
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NC |
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NC |
A |
A |
A A A |
A |
A |
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Figure 2a. DPRAM Pinout (68-Flatpack)
(top view)
A5L
A4L
A3L
A2L
A1L
A0L
NC
BUSYL
GND
M/S
BUSYR
NC
A0R
A1R
A2R
A3R
A4R
2
11
10
9
8
7
6
5
4
3
2
1
Notes:
|
B11 |
C11 |
D11 |
E11 |
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F11 |
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G11 |
H11 |
J11 |
K11 |
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A5L |
A4L |
A2L |
A0L |
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BUSYL |
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M/S |
NC |
A1R |
A3R |
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||||
A10 |
B10 |
C10 |
D10 |
E10 |
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F10 |
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G10 |
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H10 |
J10 |
K10 |
L10 |
|||||
A7L |
A6L |
A3L |
A1L |
NC |
|
GND |
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BUSYR |
A0R |
A2R |
A4R |
A5R |
||||||
A9 |
B9 |
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K9 |
L9 |
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A9L |
A8L |
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A7R |
A6R |
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A8 |
B8 |
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K8 |
L8 |
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A11L |
A10L |
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A9R |
A8R |
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A7 |
B7 |
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K7 |
L7 |
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VDD |
NC |
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A11R |
A10R |
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A6 |
B6 |
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7C138/139 |
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K6 |
L6 |
||||||||||
NC |
NC |
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GND |
NC |
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A5 |
B5 |
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K5 |
L5 |
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NC |
CEL |
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NC |
NC |
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A4 |
B4 |
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K4 |
L4 |
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OEL |
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R/W |
L |
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NC |
CER |
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A3 |
B3 |
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K3 |
L3 |
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NC(2) |
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I/O0L |
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OER |
R/WR |
|||||
A2 |
B2 |
C2 |
D2 |
E2 |
|
F2 |
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G2 |
H2 |
J2 |
K2 |
L2 |
||||||
I/O1L |
I/O2L |
I/O4L |
GND |
I/O7L |
|
GND |
|
I/O1R |
VDD |
I/O4R |
I/O7R |
NC(1) |
||||||
|
B1 |
C1 |
D1 |
E1 |
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F1 |
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G1 |
H1 |
J1 |
K1 |
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||||
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I/O3L |
I/O5L |
I/O6L |
VDD |
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I/O0R |
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I/O2R |
I/O3R |
I/O5R |
I/O6R |
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A B C D E F G H J K L
Figure 2b: DPRAM Pinout (68 PGA) (top view)
1.I/O8R on the7C139
2.I/O8L on the 7C139
PIN NAMES
|
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LEFT PORT |
|
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|
RIGHT PORT |
DESCRIPTION |
||
|
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|||||||||||||
|
I/O0L-7L(8L) |
I/O0R-7R(8R) |
Data Bus Input/Output |
|||||||||||||
|
A0L-11L |
A0R-11R |
Address Lines |
|||||||||||||
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L |
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R |
Chip Enable |
|||||||
|
CE |
CE |
||||||||||||||
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L |
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R |
Output Enable |
|||||
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OE |
OE |
||||||||||||||
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L |
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R |
Read/Write Enable |
||
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R/W |
R/W |
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L |
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R |
Busy Flag Input/Output |
|
BUSY |
BUSY |
||||||||||||||
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Master or Slave Select |
||
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M/S |
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VDD |
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Power |
|||||||
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GND |
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Ground |
|||||||
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3
The UT7C138/139 consists of an array of 4K words of 8 or 9 bits of dual-port SRAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. With the M/S pin, the UT7C138/139 can
function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). Each port is provided with its own output enable control (OE), which allows data to be read from the device.
WRITE CYCLE
A combination of R/W less than VIL (max), and CE less than VIL (max), defines a write cycle. The state of OE is a “don’t
care” for a write cycle. The outputs are placed in the highimpedance state when either OE is greater than VIH (min), or
when R/W is less than VIL (max).
WRITE OPERATION
Write Cycle 1, the Write Enable-controlled Access shown in figure 4a, is defined by a write terminated by R/W going high with CE active. The write pulse width is defined by tPWE when
the write is initiated by R/W, and by tSCE when the write is initiated by CE going active. Unless the outputs have been previously placed in the high-impedance state by OE, the user must wait tHZOE before applying data to the eight/nine bidirectional pins I/O(0:7/0:8) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access shown in figure 4b, is defined by a write terminated byCE going inactive. The write pulse width is defined by tPWE when the write is
initiated by R/W, and by tSCE when the write is initiated by CE
going active. For the R/W initiated write, unless the outputs have been previously placed in the high-impedance state by OE, the user must wait tHZWE before applying data to the eight/nine bidirectional pins I/O(0:7/0:8) to avoid bus contention.
If a location is being written by one port and the opposite port attempts to read that location, a port-to-port flow through delay must be met before the data is read on the output. Data will be valid on the port wishing to read the location (tBZA + t BDD) after
the data is written on the other port (see figure 5a).
READ OPERATION
When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE
is asserted (see figures 3a and 3b).
MASTER/SLAVE
A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. Writing of slave devices must be delayed until after the BUSY input has settled. Otherwise, the slave chip may begin a write cycle during a contention situation. When presented as a HIGH
input, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. When presented as a LOW input, the M/S pin allows the device to be used as a slave, and, therefore, the BUSY pin is an input.
Table 1. Non-Contending Read/Write
|
INPUTS |
|
OUTPUTS |
|
||
|
|
|
|
|
|
|
CE |
|
R/W |
|
OE |
I/O0-7 |
OPERATION |
H |
|
X |
|
X |
High Z |
Power Down |
|
|
|
|
|
|
|
X |
|
X |
|
H |
High Z |
I/O Lines |
|
|
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|
|
Disabled |
|
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|
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|
L |
|
H |
|
L |
Data Out |
Read |
|
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L |
|
L |
|
X |
Data In |
Write |
|
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L |
|
X |
|
X |
--- |
Illegal |
|
|
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|
|
|
Condition |
|
|
|
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|
|
|
RADIATION HARDNESS
The UT7C138/139 incorporates special design and layout features which allow operation in high-level radiation environments. UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup immunity, UTMC builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. In addition, UTMC pays special attention to power and ground distribution during the design phase, minimizing dose-rate upset caused by rail collapse.
Table 2. Radiation Hardness
Design Specifications1
Total Dose |
1.0E6 |
|
|
rads(Si) |
|
|
|
|
|
|
|
|
|
|
|
LET Threshold |
85 |
|
|
MeV-cm |
2 |
/mg |
|
|
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|
|||
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|
|
Neutron Fluence2 |
3.0E14 |
|
|
n/cm2 |
|
|
|
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|
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|
|
|
Memory Device |
< 1.376E |
-2 |
(4Kx8) |
cm |
2 |
|
|
Cross Section @ LET |
|
|
|
|
|||
< 1.548E |
-2 |
(4Kx9) |
|
|
|
|
|
= 120MeV-cm2/mg |
|
|
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|
|||
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|
|
Notes:
1.The DPRAM will not latchup during radiation exposure under recommended operating conditions.
2.Not tested for CMOS technology.
4
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL |
PARAMETER |
LIMITS |
|
|
|
VDD |
DC supply voltage |
-0.5 to 7.0V |
VI/O |
Voltage on any pin |
-0.5 to (VDD + 0.3)V |
TSTG |
Storage temperature |
-65 to +150°C |
PD |
Maximum power dissipation |
2.0W |
|
|
|
TJ |
Maximum junction temperature2 |
+150°C |
ΘJC |
Thermal resistance, junction-to-case3 |
3.3°C/W |
II |
DC input current |
± 10 mA |
|
|
|
Notes:
1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3.Test per MIL-STD-883, Method 1012, infinite heat sink.
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
LIMITS |
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VDD |
Positive supply voltage |
4.5 to 5.5V |
TC |
Case temperature range |
-55 to +125°C |
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VIN |
DC input voltage |
0V to VDD |
5
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (VDD = 5.0V ± 10%; -55°C < TC < +125°C)
SYMBOL |
PARAMETER |
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CONDITION |
MIN |
MAX |
UNIT |
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VIH |
High-level input voltage |
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(CMOS) |
0.7VDD |
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V |
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VIL |
Low-level input voltage |
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(CMOS) |
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0.3VDD |
V |
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VOL |
Low-level output voltage |
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IOL = 8mA, V DD = 4.5V (TTL) |
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0.4 |
V |
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VOL |
Low-level output voltage |
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IOL = 200mA, VDD = 4.5V (CMOS) |
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0.05 |
V |
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VOH |
High-level output voltage |
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IOH = -4mA, V DD = 4.5V (TTL) |
2.4 |
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V |
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VOH |
High-level output voltage |
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IOH = -200mA, VDD = 4.5V (CMOS) |
4.45 |
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V |
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1 |
Input capacitance |
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¦ = 1MHz @ 0V |
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25 |
pF |
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CIN |
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1 |
Bidirectional I/O capacitance |
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¦ = 1MHz @ 0V |
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25 |
pF |
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CIO |
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IIN |
Input leakage current |
|
VIN = V DD and VSS |
-10 |
10 |
mA |
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IOZ |
Three-state output leakage current |
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VO = VDD and VSS |
-10 |
10 |
mA |
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VDD = 5.5V |
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G = 5.5V |
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I |
2,3 |
Short-circuit output current |
|
VDD = 5.5V, VO = V DD |
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90 |
mA |
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OS |
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VDD = 5.5V, VO = 0V |
-90 |
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mA |
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I |
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(OP)4,5 |
Supply current operating (both ports) |
|
CMOS inputs (IOUT = 0) |
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300 |
mA |
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DD |
@ 22.2MHz |
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VDD = 5.5V |
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I |
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(OP)4,6 |
Supply current operating (single port) |
|
CMOS inputs (IOUT = 0) |
|
150 |
mA |
||
|
DD |
@ 22.2 MHz |
|
VDD = 5.5V |
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I |
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(OP)4,5 |
Supply current operating (both ports) |
|
CMOS inputs (IOUT = 0) |
|
275 |
mA |
||
|
DD |
@ 18.2MHz |
|
VDD = 5.5V |
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I |
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(OP)4,6 |
Supply current operating (single port) |
|
CMOS inputs (IOUT = 0) |
|
138 |
mA |
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DD |
@ 18.2 MHz |
|
VDD = 5.5V |
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IDD(SB)4 |
Supply current standby |
|
CMOS inputs (IOUT = 0) |
|
1 |
mA |
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CE = VDD - 0.5, VDD = 5.5V |
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Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1.Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2.Supplied as a design limit but not guaranteed or tested.
3.Not more than one output may be shorted at a time for maximum duration of one second.
4.VIH = 5.5V, V IL = 0V.
5.IDD (OP) derates at 6.4mA/MHz.
6.IDD (OP) derates at 3.4mA/MHz.
6
AC CHARACTERISTICS READ CYCLE 1,2
(VDD = 5.0V±10%)
SYMBOL |
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PARAMETER |
7C138 - 45 |
7C138 - 55 |
UNIT |
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7C139 - 45 |
7C139 - 55 |
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MIN MAX |
MIN MAX |
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tRC |
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Read cycle time |
45 |
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55 |
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ns |
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tAA |
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Address to data valid2 |
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45 |
|
55 |
ns |
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tOHA |
Output hold from address change |
5 |
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5 |
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ns |
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tACE |
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LOW to data valid2 |
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45 |
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55 |
ns |
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CE |
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t |
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20 |
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20 |
ns |
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OE LOW to data valid2 |
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DOE |
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tLZOE |
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OE LOW to low Z |
0 |
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0 |
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ns |
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tHZOE |
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OE HIGH to high Z |
|
20 |
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20 |
ns |
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tLZCE |
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CE LOW to low Z |
0 |
|
0 |
|
ns |
||||
tHZCE |
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|
CE HIGH to high Z |
|
20 |
|
20 |
ns |
Notes:
1 . Test conditions assume signal transition time of 5ns or less, timing reference levels of V DD /2, input pulse levels of 0.5V to VDD-0.5V, and output loading of the specified IO L/IOH and 50-pF load capacitance.
2. AC test conditions use VOH/V OL=VDD/2 + 500mV.
7