Standard Products
UT69RH051 Radiation-Hardened MicroController
Data Sheet
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May 2003 |
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FEATURES |
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q Three 16-bit timer/counters |
q Flexible clock operation |
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- High speed output |
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- Compare/capture |
- 1Hz to 20MHz with external clock |
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- Pulse width modulator |
- 2MHz to 20MHz using internal oscillator with external |
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- Watchdog timer capabilities |
crystal |
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q 256 bytes of on-chip data RAM |
q Radiation-hardened process and design; total dose irradia- |
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q 32 programmable I/O lines |
tion testing MIL-STD-883 Method 1019 |
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- Total dose: 1.0E6 rads(Si) |
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q 7 interrupt sources |
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- Latchup immune |
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q Programmable serial channel with: |
q Packaging options: |
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- Framing error detection |
- 40-pin 100-mil center DIP (0.600 x 2.00) |
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- Automatic address recognition |
- 44-lead 25-mil center Flatpack (0.670 x 0.800) |
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q TTL and CMOS compatible logic levels |
q Standard Microcircuit Drawing 5962-95638 available |
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q 64K external data and program memory space |
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- QML Q & V compliant |
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q MCS-51 fully compatible instruction set |
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RAMADDRESS |
REG ISTER |
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PORT 0 |
PORT 2 |
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DRIVERS |
DRIVERS |
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RAM |
PORT 0 |
PORT 2 |
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LATCH |
LATCH |
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PROGRAM |
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ADDRESS |
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REGISTER |
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B |
ACC |
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STACK |
BUFFER |
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REGISTER |
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POINTER |
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TMP2 |
TMP1 |
SPECIAL FUNCTION |
PC |
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REGISTERS, |
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INCREMENTER |
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ALU |
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TIMERS, |
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PCA, |
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PSEN |
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S EQUENCER |
INSTRUCTION REGISTER |
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PROGRAM |
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SERIAL PORT |
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PSW |
TMP3 |
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COUNTER |
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MICRO- |
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ALE |
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E A |
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DPTR |
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RST |
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PORT 1 |
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PORT 3 |
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LATCH |
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LATCH |
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OSC. |
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PORT 1 |
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PORT 3 |
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DRIVERS |
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DRIVERS |
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XTAL1 |
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XTAL2 |
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P1.0 - P1.7 |
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P3.0 - P3.7 |
Figure 1. UT69RH051 MicroController Block Diagram
1.0 INTRODUCTION
The UT69RH051 is a radiation-tolerant 8-bit microcontroller that is pin equivalent to the MCS-51 industry standard microcontroller when in a 40-pin DIP. The UT69RH051’s static design allows operation from 1Hz to 20MHz. This data sheet describes hardware and software interfaces to the UT69RH051.
2.0 SIGNAL DESCRIPTION
VDD: +5V Supply voltage
VSS: Circuit Ground
Port 0 (P0.0 - P0.7): Port 0 is an 8-bit port. Port 0 pins are used as the low-order multiplexed address and data bus during accesses to external program and data memory. Port 0 pins use internal pullups when emitting 1’s and are TTL compatible.
Port 1 (P1.0 - P1.7):Port 1 is an 8-bit bidirectional I/O port with internal pullups. The output buffers can drive TTL loads. When the Port 1 pins have 1’s written to them, they are pulled high by the internal pullups and can be used as inputs in this state. As inputs, any pins that are externally pulled low sources current because of the pullups. In addition, Port 1 pins have the alternate uses shown in table 1.
Port 2 (P2.0 - P2.7): Port 2 is an 8-bit port. Port 2 pins are used as the high-order address bus during accesses to external Program Memory and during accesses to external Data Memory that uses 16-bit addresses (i.e., MOVX@DPTR). Port 2 uses internal pullups when emitting 1’s in this mode. During operations that do not require a 16-bit address, Port 2 emits the contents of the P2 Special Function Registers (SFR). The pins have internal pullups and drives TTL loads.
Port 3 (P3.0 - P3.7):Port 3 is an 8-bit bidirectional I/O port with internal pullups. The output buffers can drive TTL loads. When the Port 3 pins have 1’s written to them, they are pulled high by the internal pullups and can be used as inputs in this state. As inputs, any pins that are externally pulled low sources current because of the pullups. In addition, Port 3 pins have the alternate uses shown in table 2.
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Table 1. Port 1 Alternate Functions |
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Port |
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Alternate |
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Alternate Function |
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Pin |
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Name |
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P1.0 |
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T2 |
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External clock input to Timer/ |
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Counter 2 |
P1.1 |
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T2EX |
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Timer/Counter 2 Capture/Reload |
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trigger and direction control |
P1.2 |
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ECI |
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External count input to PCA |
P1.3 |
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CEX0 |
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External I/O for PCA capture/ |
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compare Module 0 |
P1.4 |
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CEX1 |
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External I/O for PCA capture/ |
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compare Module 1 |
P1.5 |
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CEX2 |
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External I/O for PCA capture/ |
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compare Module 2 |
P1.6 |
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CEX3 |
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External I/O for PCA capture/ |
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compare Module 3 |
P1.7 |
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CEX4 |
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External I/O for PCA capture/ |
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compare Module 4 |
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Table 2. Port 3 Alternate Functions |
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Alternate |
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Alternate Function |
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Name |
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P3.0 |
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RXD |
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Serial port input |
P3.1 |
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TXD |
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Serial port output |
P3.2 |
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INT0 |
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External interrupt 0 |
P3.3 |
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INT1 |
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External interrupt 1 |
P3.4 |
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T0 |
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External clock input for Timer 0 |
P3.5 |
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T1 |
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External clock input for Timer 1 |
P3.6 |
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WR |
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External Data Memory write |
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strobe |
P3.7 |
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RD |
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External Data Memory read strobe |
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RST: Reset Input. A high on this input for 24 oscillator periods while the oscillator is running resets the device. All ports and SFRs reset to their default conditions. Internal data memory is undefined after reset. Program execution begins within 12 oscillator periods (one machine cycle) after the RST signal is brought low. RST contains an internal pulldown resistor to allow implementing power-up reset with only an external capacitor.
ALE: Address Latch Enable. The ALE output is a pulse for latching the low byte of the address during accesses to external memory. In normal operation, the ALE pulse is output every sixth oscillator cycle and may be used for external timing or clocking. However, during each access to external Data Memory (MOVX instruction), one ALE pulse is skipped.
PSEN: Program Store Enable. This active low signal is the read strobe to the external program memory. PSEN activates every sixth oscillator cycle except that two PSEN activations are skipped during external data memory accesses.
EA: External Access Enable. This pin should be strapped to VSS (Ground) for the UT69RH051.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
2.1 Hardware/Software Interface
2.1.1 Memory
The UT69RH051 has a separate address space for Program and Data Memory. Internally, the UT69RH051 contains 256 bytes of Data Memory. It addresses up to 64Kbytes of external Data Memory and 64Kbytes of external Program Memory.
2.1.1.1 Program Memory
There is no internal program memory in the UT69RH051. All program memory is accessed as external through ports P0 and P2. The EA pin must be tied to VSS (ground) to enable access to external locations 0000H through 7FFFH. Following reset, the UT69RH051 fetches the first instruction at address 0000h.
2.1.1.2 Data Memory
The UT69RH051 implements 256 bytes of internal data RAM. The upper 128 bytes of this RAM occupy a parallel address space to the SFRs. The CPU determines if the internal access to an address above 7FH is to the upper 128 bytes of RAM or to the SFR space by the addressing mode of the instruction. If direct addressing is used, the access is to the SFR space. If indirect addressing is used, the access is to the internal RAM. Stack operations are indirectly addressed so the upper portion of RAM can be used as stack space. Figure 3 shows the organization of the internal Data Memory.
The first 32 bytes are reserved for four register banks of eight bytes each. The processor uses one of the four banks as its working registers depending on the RS1 and RS0 bits in the PSW SFR. At reset, bank 0 is selected. If four register banks are not required, use the unused banks as general purpose scratch pad memory. The next 16 bytes (128 bits) are individually bit addressable. The remaining bytes are byte addressable and can be used as general purpose scratch pad memory. For addresses 0 - 7FH, use either direct or indirect addressing. For addresses larger than 7FH, use only indirect addressing.
In addition to the internal Data Memory, the processor can access 64Kbytes of external Data Memory. The MOVX instruction accesses external Data Memory.
2.1.2 Special Function Registers
Table 3 contains the SFR memory map. Unoccupied addresses are not implemented on the device. Read accesses to these addresses will return unknown values and write accesses will have no effect.
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(T2) |
P1.0 |
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1 |
40 |
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VDD |
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(T2EX) |
P1.1 |
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2 |
39 |
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P0.0 |
(AD0) |
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(ECI) |
P1.2 |
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3 |
38 |
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P0.1 |
(AD1) |
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(CEX0) |
P1.3 |
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4 |
37 |
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P0.2 |
(AD2) |
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(CEX1) |
P1.4 |
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36 |
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P0.3 |
(AD3) |
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(CEX2) |
P1.5 |
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6 |
35 |
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P0.4 |
(AD4) |
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(CEX3) |
P1.6 |
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34 |
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P0.5 |
(AD5) |
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(CEX4) |
P1.7 |
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33 |
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P0.6 |
(AD6) |
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RST |
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9 |
32 |
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P0.7 |
(AD7) |
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(RXD) |
P3.0 |
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31 |
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EA |
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(TXD) |
P3.1 |
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30 |
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ALE |
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(INT0) |
P3.2 |
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12 |
29 |
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PSEN |
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(INT1) |
P3.3 |
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13 |
28 |
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P2.7 |
(A15) |
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(T0) |
P3.4 |
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27 |
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P2.6 |
(A14) |
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(T1) |
P3.5 |
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15 |
26 |
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P2.5 |
(A13) |
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(WR) |
P3.6 |
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16 |
25 |
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P2.4 |
(A12) |
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(RD) |
P3.7 |
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17 |
24 |
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P2.3 |
(A11) |
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XTAL2 |
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18 |
23 |
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P2.2 |
(A10) |
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XTAL1 |
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22 |
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P2.1 |
(A9) |
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V SS |
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20 |
21 |
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P2.0 |
(A8) |
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Figure 2a. UT69RH051 40-Pin DIP Connections
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VSS |
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1 |
44 |
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VDD |
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(T2) |
P1.0 |
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43 |
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P0.0 |
(AD0) |
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(T2EX) |
P1.1 |
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42 |
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P0.1 |
(AD1) |
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NC |
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41 |
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P0.2 |
(AD2) |
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(ECI) |
P1.2 |
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40 |
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P0.3 |
(AD3) |
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(CEX0) |
P1.3 |
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6 |
39 |
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P0.4 |
(AD4) |
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(CEX1) |
P1.4 |
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38 |
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P0.5 |
(AD5) |
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(CEX2) |
P1.5 |
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37 |
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P0.6 |
(AD6) |
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(CEX3) |
P1.6 |
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36 |
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P0.7 |
(AD7) |
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(CEX4) |
P1.7 |
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35 |
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EA |
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RST |
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34 |
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ALE |
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(RXD) |
P3.0 |
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12 |
33 |
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PSEN |
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(TXD) |
P3.1 |
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13 |
32 |
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P2.7 |
(A15) |
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(INTO ) |
P3.2 |
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14 |
31 |
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P2.6 |
(A14) |
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(INT1) |
P3.3 |
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15 |
30 |
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P2.5 |
(A13) |
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(TO) |
P3.4 |
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16 |
29 |
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P2.4 |
(A12) |
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(T1) |
P3.5 |
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17 |
28 |
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P2.3 |
(A11) |
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(WR) |
P3.6 |
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18 |
27 |
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P2.2 |
(A10) |
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(RD) |
P3.7 |
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19 |
26 |
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P2.1 |
(A9) |
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XTAL2 |
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20 |
25 |
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P2.0 |
(A8) |
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XTAL1 |
21 |
24 |
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NC |
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VSS |
22 |
23 |
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VDD |
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Figure 2b. UT69RH051 44-Pin Flatpack Connections
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F8 |
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8 BYTES |
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FF |
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F0 |
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F7 |
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INDIRECT |
∙ |
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∙ |
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ACCESS |
∙ |
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∙ |
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ONLY |
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∙ |
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∙ |
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88 |
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8F |
SCRATCH |
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80 |
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87 |
PAD AREA |
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78 |
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7F |
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70 |
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77 |
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∙ |
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∙ |
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∙ |
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∙ |
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∙ |
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∙ |
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38 |
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3F |
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DIRECT OR |
30 |
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37 |
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INDIRECT |
28 |
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2F |
BIT |
ACCESS |
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ADDRESSABLE |
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20 |
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27 |
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SEGMENT |
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18 |
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1F |
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10 |
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17 |
REGISTER |
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08 |
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0F |
BANKS |
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00 |
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07 |
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Figure 3. Internal Data Memory Organization
2.1.3 Reset
The reset input is the RST pin. To reset, hold the RST pin high for a minimum of 24 oscillator periods while the oscillator is running. The CPU generates an internal reset from the external signal. The port pins are driven to the reset state as soon as a valid high is detected on the RST pin.
While RST is high,PSEN and the port pins are pulled high; ALE is pulled low. All SFRs are reset to their reset values as shown in table 3. The internal Data Memory content is indeterminate.
The processor will begin operation one machine cycle after the RST line is brought low. A memory access occurs immediately after the RST line is brought low, but the data is not brought into the processor. The memory access repeats on the next machine cycle and actual processing begins at that time.
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Table 3. SFR Memory Registers
F8 |
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CH |
CCAP0H |
CCAP1H |
CCAP2H |
CCAP3H |
CCAP4H |
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FF |
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00000000 |
XXXXXXXX |
XXXXXXXX |
XXXXXXXX |
XXXXXXXX |
XXXXXXXX |
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F0 |
B |
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F7 |
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00000000 |
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E8 |
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CL |
CCAP0L |
CCAP1L |
CCAP2L |
CCAP3L |
CCAP4L |
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EF |
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00000000 |
XXXXXXXX |
XXXXXXXX |
XXXXXXXX |
XXXXXXXX |
XXXXXXXX |
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E0 |
ACC |
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E7 |
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00000000 |
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D8 |
CCON |
CMOD |
CCAPM0 |
CCAPM1 |
CCAPM2 |
CCAPM3 |
CCAPM4 |
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DF |
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00X00000 |
OOXXX000 |
X00000000 |
X00000000 |
X00000000 |
X00000000 |
X00000000 |
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D0 |
PSW |
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D7 |
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00000000 |
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C8 |
T2CON |
T2MOD |
RCAP2L |
RCAP2H |
TL2 |
TH2 |
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CF |
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00000000 |
XXXXXX00 |
00000000 |
00000000 |
00000000 |
00000000 |
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C0 |
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C7 |
B8 |
IP |
SADEN |
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BF |
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X0000000 |
00000000 |
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B0 |
P3 |
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IPH |
B7 |
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11111111 |
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X00000000 |
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A8 |
IE |
SADDR |
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AF |
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00000000 |
00000000 |
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A0 |
P2 |
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A7 |
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11111111 |
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98 |
SCON |
SBUF |
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9F |
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00000000 |
XXXXXXXX |
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90 |
P1 |
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97 |
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11111111 |
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88 |
TCON |
TMOD |
TL0 |
TL1 |
TH0 |
TH1 |
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8F |
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00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
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80 |
P0 |
SP |
DPL |
DPH |
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PCON |
87 |
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11111111 |
00000111 |
00000000 |
00000000 |
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00XX00XX |
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Notes:
1.Values shown are the reset values of the registers.
2.X = undefined.
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