Standard Products
UT67164 Radiation-Hardened 8K x 8 SRAM -- SEU Hard
Data Sheet
January 2002
FEATURES
q55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day (-55o C to 125+oC)
q5-volt operation
qPost-radiation AC/DC performance characteristics guaranteed by MIL-STD-883 Method 1019 testing at 1.0E6 rads(Si)
qAsynchronous operation for compatibility with industrystandard 8K x 8 SRAM
qTTL-compatible input and output levels
qThree-state bidirectional data bus
qLow operating and standby current
qFull military operating temperature range, -55o C to 125+o C, screened to specific test methods listed in Table I MIL-STD- 883 Method 5004 for Class S or Class B
qRadiation-hardened process and design; total dose irradiation testing to MIL-STD-883 Method 1019
-Total-dose: 1.0E6 rads(Si)
-Dose rate upset: 1.0E9 rads (Si)/sec
-Dose rate survival: 1.0E12 rads (Si)/sec
-Single-event upset: <1.0E-10 errors/bit-day
qIndustry standard (JEDEC) 64K SRAM pinout
qPackaging options:
-28-pin 100-mil center DIP (.600 x 1.2)
-28-pin 50-mil center flatpack (.700 x .75)
INTRODUCTION
The UT67164 SRAM is a high performance, asynchronous, radiation-hardened, 8K x 8 random access memory conforming to industry-standard fit, form, and function. The UT67164 SRAM features fully static operation requiring no external clocks or timing strobes. UTMC designed and implemented the UT67164 using an advanced radiationhardened twin-well CMOS process. Advanced CMOS processing along with a device enable/disable function result in a high performance, power-saving SRAM. The combination of radiation-hardness, fast access time, and low power consumption make UT67164 ideal for high-speed systems designed for operation in radiation environments.
A(12:5) |
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INPUT |
ROW |
256 x 256 |
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DRIVERS |
DECODERS |
MEMORY ARRAY |
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A(4:0) |
INPUT |
COLUMN |
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DATA |
INPUT |
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COLUMN |
WRITE |
DRIVERS |
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DRIVERS |
DECODERS |
CIRCUIT |
DQ(7:0) |
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I/O |
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E1 |
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CHIP ENABLE |
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DATA |
OUTPUT |
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READ |
DRIVERS |
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CIRCUIT |
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E2 |
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G |
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OUTPUT ENABLE |
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W |
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WRITE ENABLE |
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Figure 1. SRAM Block Diagram
NC |
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1 |
28 |
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VDD |
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A12 |
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2 |
27 |
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W |
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A7 |
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3 |
26 |
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E2 |
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A6 |
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4 |
25 |
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A8 |
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A5 |
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5 |
24 |
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A9 |
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A4 |
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6 |
23 |
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A11 |
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A3 |
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7 |
22 |
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G |
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A2 |
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8 |
21 |
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A10 |
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A1 |
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9 |
20 |
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E1 |
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A0 |
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10 |
19 |
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DQ7 |
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DQ0 |
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11 |
18 |
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DQ6 |
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DQ1 |
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12 |
17 |
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DQ5 |
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DQ2 |
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13 |
16 |
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DQ4 |
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Vss |
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14 |
15 |
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DQ3 |
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Figure 2. SRAM Pinout
PIN NAMES
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A(12:0) |
Address |
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W |
Write |
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DQ(7:0) |
Data Input/Output |
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G |
Output Enable |
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E1 |
Enable 1 |
VDD |
Power |
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E21 |
Enable 2 |
VSS |
Ground |
DEVICE OPERATION
The UT67164 has four control inputs called Enable 1 (E 1), Enable 2 (E2), Write Enable (W), and Output Enable (G); 13 address inputs, A(12:0); and eight bidirectional data lines, DQ(7:0). E1 and E2 are device enable inputs that control device selection, active, and standby modes. Asserting both E1 and E2 enables the device, causes IDD to rise to its active value, and decodes the 13 address inputs to select one of 8,192 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
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G |
W |
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E1 |
E2 |
I/O Mode |
Mode |
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X |
1 |
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X |
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X |
0 |
3-state |
Standby |
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X |
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X |
1 |
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X |
3-state |
Standby |
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X |
0 |
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0 |
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1 |
Data in |
Write |
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1 |
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1 |
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0 |
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1 |
3-state |
Read |
2 |
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0 |
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1 |
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0 |
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1 |
Data out |
Read |
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Notes:
1.“X” is defined as a “don’t care” condition.
2.Device active; outputs disabled.
READ CYCLE
A combination of W greater than VIH (min), E1 less than VIL
(max), and E2 greater than V IH (min) defines a read cycle. Read access time is measured from the latter of device enable, Output Enable, or valid address to valid data output.
Read Cycle 1, the Address Access read in figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV ).
Figure 3b shows Read Cycle 2, the Chip Enable-controlled Access. For this cycle, G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(12:0) is accessed and appears at the data outputs DQ(7:0).
Figure 3c shows Read Cycle 3, the Output Enable-controlled Access. For this cycle, E1 and E2 are asserted, W is deasserted, and the addresses are stable before G is enabled. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.
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WRITE CYCLE
A combination of W less than V IL(max), E 1less than V IL(max), and E2 greater than VIH(min) defines a write cycle. The state of
G is a “don’t care” for a write cycle. The outputs are placed in the high-impedance state when either G is greater than
VIH(min), or when W is less than VIL(max).
Write Cycle 1, the Write Enable-controlled Access shown in figure 4a, is defined by a write terminated byW going high, with E1and E2 still active. The write pulse width is defined by t WLWH
when the write is initiated by W, and by tETWH when the write
is initiated by the latter of E1 or E2. Unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access shown in figure 4b, is defined by a write terminated by the latter of E1 or E2 going inactive. The write pulse width is defined by tWLEF when the write is initiated by W, and by tETEF when the write
is initiated by the latter of E1 or E2 going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention.
RADIATION HARDNESS
The UT67164 SRAM incorporates special design and layout features which allow operation in high-level radiation environments.
Table 2. Radiation Hardness
Design Specifications1
Total Dose |
1.0E6 |
rads(Si) |
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Dose Rate Upset |
1.0E9 |
rads(Si)/s 20ns pulse |
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Dose Rate Survival |
1.0E12 |
rads(Si)/s 20ns pulse |
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Single-Event Upset |
1.0E-10 |
errors/bit day2 |
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Neutron Fluencs |
3.0E14 |
2 |
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n/cm |
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Notes:
1.The SRAM will not latchup during radiation exposure under recommended operating conditions.
2.90% Adam’s worst case spectrum (-55oC to 125+oC).
Table 3. SEU versus Temperature
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10-4 |
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10-6 |
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day |
10-8 |
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10-10 |
SEU errors/bit- |
10-10 |
10-13 |
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10-11 |
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10-12 10-13 |
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10-14 |
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10-16 |
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-55 -35 -15 |
5 |
25 45 |
65 85 |
105 125 |
Temperature (oC)
3
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL |
PARAMETER |
LIMITS |
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VDD |
DC supply voltage |
-0.5 to 7.0V |
VI/O |
Voltage on any pin |
-0.5 to VDD + 0.5 |
TSTG |
Storage temperature |
-65 to +150°C |
PD |
Maximum power dissipation |
1.0W |
TJ |
Maximum junction temperature |
+150°C |
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ΘJC |
Thermal resistance, junction-to-case2 |
10°C/W |
ILU |
Latchup immunity |
+/-150mA |
II |
DC input current |
+/-10 mA |
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Notes:
1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
LIMITS |
UNITS |
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VDD |
Positive supply voltage |
4.5 to 5.5V |
V |
TC |
Case temperature range |
-55 to +125°C |
o C |
VIN |
DC input voltage |
0V to VDD |
V |
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DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(VDD = 5.0V±10%; -55°C <Tc < +125°C)
SYMBOL |
PARAMETER |
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CONDITION |
MIN |
MAX |
UNIT |
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VIH |
High-level input voltage |
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2.2 |
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V |
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VIL |
Low-level input voltage |
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0.8 |
V |
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VOL |
Low-level output voltage |
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IOL = +/- 4.0mA, V DD = 4.5V |
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0.4 |
V |
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VOH |
High-level output voltage |
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IOH = +/-4mA, V DD = 4.5V |
2.4 |
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V |
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CIN |
Input capacitance |
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¦ = 1MHz @ 0V, V DD = 4.5V |
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15 |
pF |
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1 |
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CIO |
Bidirectional I/O capacitance |
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¦ = 1MHz @ 0V, V DD = 4.5V |
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20 |
pF |
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1 |
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IIN |
Input leakage current |
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VIN = V DD and V SS |
-10 |
+10 |
mA |
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IOZ |
Three-state output leakage current |
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VO = VDD and VSS |
-10 |
+10 |
mA |
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VDD = 5.5V |
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G = 5.5V |
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I |
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2, 3 |
Short-circuit output current |
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VDD = 5.5V, V O = VDD |
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+90 |
mA |
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OS |
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VDD = 5.5V, V O = 0V |
-90 |
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mA |
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I |
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(OP) |
Supply current operating @1MHz |
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CMOS inputs (IOUT = 0) |
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40 |
mA |
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DD |
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VDD = 5.5V |
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IDD(SB) |
Supply current standby |
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CMOS inputs (IOUT = 0) |
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200 |
mA |
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pre-rad |
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E1 = V DD - 0.5, VDD = 5.5V |
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IDD(SB) |
Supply current standby |
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CMOS inputs (IOUT = 0) |
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3 |
mA |
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post-rad |
@ f = 0Hz |
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CS1 = negated V DD = 5.5V |
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CS2 = negated |
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Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).
1.Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2.Supplied as a design limit but not guaranteed or tested.
3.Not more than one output may be shorted at a time for maximum duration of one second.
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