Standard Products
UT54LVDS218 Deserializer
Data Sheet
October 2002
FEATURES
q15 to 50MHz shift clock support
q50% duty cycle on receiver output clock
qLow power consumption
qCold sparing all pins
q+1V common mode range (around +1.2V)
qNarrow bus reduces cable size and cost
qUp to 1.05 Gbps throughput
qUp to 132 Megabytes/sec bandwidth
q325 mV (typ) swing LVDS devices for low EMI
qPLL requires no external components
qRising edge strobe
qRadiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019
-Total-dose: 300 krad(Si) and 1 Mrad(Si)
-Latchup immune (LET > 100 MeV-cm2 /mg)
qPackaging options:
-48-lead flatpack
qStandard Microcircuit Drawing 5962-01535
-QML Q and V compliant part
qCompatible with TIA/EIA-644 LVDS standard
INTRODUCTION
The UT54LVDS218 Deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 50MHz, 21 bits of TTL data are transmitted at a rate of 350 Mbps per LVDS data channel. Using a 50 MHz clock, the data throughput is 1.05 Gbit/s (132 Mbytes/sec).
The UT54LVDS218 Deserializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size.
All pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS.
DATA (LVDS)
LVDS TO-PARALLEL TTL
21
CMOS/TTL OUTPUTS
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CLOCK (LVDS) |
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PLL |
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RECEIVER CLOCK OUT |
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POWER DOWN |
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Figure 1. UT54LVDS218 Deserializer Block Diagram |
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RxOUT 17 |
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1 |
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VDD |
PIN DESCRIPTION |
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RxOUT 18 |
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RxOUT 16 |
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GND |
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RxOUT 15 |
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No. |
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Description |
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RxOUT 19 |
4 |
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RxOUT 14 |
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RxIN+ |
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3 |
Positive LVDS differential data inputs1 |
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GND |
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RxOUT 20 |
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RxIN- |
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Negative LVDS differential data output 1 |
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N/C |
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UT54LVDS218 |
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RxOUT 13 |
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LVDS GND |
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VDD |
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RxOUT |
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21 |
TTL level data outputs |
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RxOUT 12 |
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RxIN0- |
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RxCLK IN+ |
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Positive LVDS differential clock input |
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RxIN0+ |
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RxOUT 11 |
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RxCLK IN- |
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Negative LVDS differential clock input |
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RxIN1- |
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RxOUT 10 |
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RxCLK OUT |
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TTL level clock output. The rising edge acts |
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RxIN1+ |
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as data strobe. Pin name RxCLK OUT. |
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LVDS V DD |
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RxOUT 9 |
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PWR DWN |
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TTL level input. When asserted (low input) |
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LVDS GND |
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VDD |
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the receiver outputs are low |
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RxIN2- |
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RxOUT 8 |
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VDD |
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4 |
Power supply pins for TTL outputs and log- |
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RxIN2+ |
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RxOUT 7 |
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RxCLK IN- |
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GND |
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5 |
Ground pins for TTL outputs and logic |
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RxOUT 6 |
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RxCLK IN+ |
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GND |
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PLL VDD |
I |
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1 |
Power supply for PLL |
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RxOUT 5 |
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LVDS GND |
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PLL GND |
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Ground pin for PLL |
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RxOUT 4 |
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PLL GND |
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LVDS V DD |
I |
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1 |
Power supply pin for LVDS pins |
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PLL V DD |
20 |
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29 |
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RxOUT 3 |
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LVDS GND |
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3 |
Ground pins for LVDS inputs |
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PLL GND |
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28 |
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VDD |
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PWR DWN |
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27 |
RxOUT 2 |
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Notes: |
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RxCLK OUT |
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26 |
RxOUT 1 |
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1. These receivers have input fail-safe bias circuitry to guarantee a stable receiver |
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RxOUT0 |
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output for floating or terminated receiver inputs. Under these conditions receiver |
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inputs will be in a HIGH state. If a clock signal is present, outputs will all be |
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HIGH; if the clock input is also floating/terminated outputs will remain in the |
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last valid state. A floating/terminated clock input will result in a LOW clock |
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Figure 2. UT54LVDS218 Pinout |
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output. |
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LVDS CABLE |
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TX |
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RX |
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MEDIA DEPENDENT DATA |
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TxIN |
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(LVDS) |
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RxOUT |
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0 |
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1 |
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2 |
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CMOS/ |
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TTL |
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CLOCK |
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TxCLK |
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(LVDS) |
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RxCLK |
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GND |
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PCB |
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PCB |
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SHIELD
Figure 3. UT54LVDS218 Typical Application
2
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL |
PARAMETER |
LIMITS |
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VDD |
DC supply voltage |
-0.3 to 4.0V |
VI/O |
Voltage on any pin |
-0.3 to (VDD + 0.3V) |
TSTG |
Storage temperature |
-65 to +150°C |
PD |
Maximum power dissipation |
1.25 W |
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TJ |
Maximum junction temperature2 |
+150°C |
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ΘJC |
Thermal resistance, junction-to-case3 |
10°C/W |
II |
DC input current |
±10mA |
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Notes:
1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.
2.Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3.Test per MIL-STD-883, Method 1012.
4.For cold spare mode (VDD = VSS), VI/O may be -0.3V to the maximum recommended operating V DD +0.3V.
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
LIMITS |
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VDD |
Positive supply voltage |
3.0 to 3.6V |
TC |
Case temperature range |
-55 to +125°C |
VIN |
DC input voltage |
0V to VDD |
3
DC ELECTRICAL CHARACTERISTICS1
(VDD = 3.0V to 0.3V; -55°C < TC < +125°C)
SYMBOL |
PARAMETER |
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CONDITION |
MIN |
MAX |
UNIT |
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CMOS/TTL DC SPECIFICATIONS (PWR DWN, RXOUT) |
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VIH |
High-level input voltage |
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2.0 |
VDD |
V |
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VIL |
Low-level input voltage |
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GND |
0.8 |
V |
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VOL |
Low-level output voltage |
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IOL = 2mA |
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0.3 |
V |
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VOH |
High-level output voltage |
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IOL = -0.4mA |
2.7 |
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V |
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I |
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High-level input current |
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VIN=3.6V; VDD = 3.6V |
-10 |
+10 |
μA |
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IH |
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IIL |
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Low-level input current |
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VIN=0V; VDD = 3.6V |
-10 |
+10 |
μA |
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VCL |
Input clamp voltage |
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ICL = -18mA |
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-1.5 |
V |
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ICS |
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Cold spare leakage current |
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VIN=3.6V; VDD = VSS |
-20 |
+20 |
μA |
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IOS |
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Output short circuit current |
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VOUT = 0V |
-15 |
-130 |
mA |
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2, 3 |
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LVDS RECEIVER DC SPECIFICATIONS (IN+, IN-) |
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VΤΗ |
3 |
Differential input high threshold |
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VCM = +1.2V |
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+100 |
mV |
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V |
3 |
Differential input low threshold |
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VCM = +1.2V |
-100 |
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mV |
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ΤL |
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VCMR |
Common mode voltage range |
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VID=210mV |
0.2 |
2.00 |
V |
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IIN |
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Input current |
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VIN = +2.4V, VDD = 3.6V |
-10 |
+10 |
μA |
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VIN = 0V, VDD = 3.6V |
-10 |
+10 |
μA |
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ICSIN |
Cold spare leakage current |
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VIN = 3.6V, VDD = VSS |
-20 |
+20 |
μA |
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Supply Current |
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3 |
Active supply current |
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CL=8pF (see Figure 4) |
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105 |
mΑ |
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ICC |
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ICCPD |
Power down supply current |
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= Low, LVDS inputs = |
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2.0 |
mA |
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PWR DWN |
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logic low |
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Notes:
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenc ed to ground.
2.Output short circuit current (I OS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification.
3.Guaranteed by characterization.
4