UTMC 5962R9687301QYC, 5962R9687301QXX, 5962R9687301QXC, 5962R9687301QXA, 5962R9687302QYA Datasheet

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UTMC 5962R9687301QYC, 5962R9687301QXX, 5962R9687301QXC, 5962R9687301QXA, 5962R9687302QYA Datasheet

Standard Products

UT28F64 Radiation-Hardened 8K x 8 PROM

Data Sheet

August 2001

FEATURES

qProgrammable, read-only, asynchronous, radiationhardened, 8K x 8 memory

-Supported by industry standard programmer

q35ns and 45ns maximum address access time (-55 oC to +125 oC)

qTTL compatible input and TTL/CMOS compatible output levels

qThree-state data bus

qLow operating and standby current

-Operating: 100mA maximum @28.6MHz ∙ Derating: 3mA/MHz

-Standby: 500μA maximum (post-rad)

qRadiation-hardened process and design; total dose irradiation testing to MIL-STD-883, Method 1019

-Total dose: 1E6 rad(Si)

-LETTH(0.25) ~ 100 MeV-cm2/mg

-SEL Immune >128 MeV-cm 2/mg

-Saturated Cross Section cm2 per bit, 1.0E-11

-1.2E-8 errors/device-day, Adams 90% geosynchronous

heavy ion

A(12:0)

 

DECODER

 

 

 

 

 

 

 

CE

PE

CONTROL

LOGIC

OE

-Memory cell LET threshold: >128 MeV-cm 2/mg

qQML Q & V compliant part

-AC and DC testing at factory

qPackaging options:

-28-pin 100-mil center DIP (0.600 x 1.4)

-28-lead 50-mil center flatpack (0.490 x 0.74)

qVDD: 5.0 volts + 10%

qStandard Microcircuit Drawing 5962-96873

PRODUCT DESCRIPTION

The UT28F64 amorphous silicon anti-fuse PROM is a high performance, asynchronous, radiation-hardened,

8K x 8 programmable memory device. The UT28F64 PROM features fully asychronous operation requiring no external clocks or timing strobes. An advanced radiation-hardened twin-well CMOS process technology is used to implement the UT28F64. The combination of radiationhardness, fast access time, and low power consumption make the UT28F64 ideal for high speed systems designed for operation in radiation environments.

MEMORY

ARRAY

SENSE AMPLIFIER

DQ(7:0)

PROGRAMMING

Figure 1. PROM Block Diagram

1

DEVICE OPERATION

The UT28F64 has three control inputs: Chip Enable (CE), Program Enable (PE), and Output Enable (OE); thirteen address inputs, A(12:0); and eight bidirectional data lines, DQ(7:0). CE is the device enable input that controls chip selection, active, and standby modes. AssertingCE causes I DD to rise to its active value and decodes the thirteen address inputs to select one of 8,192 words in the memory. PE controls program and read operations. During a read cycle, OE must be asserted to enable the outputs.

PIN CONFIGURATION

NC

 

1

28

 

 

VDD

 

 

A12

 

2

27

 

 

 

PE

 

 

 

 

A7

 

3

26

 

 

NC

 

 

 

 

A6

 

4

25

 

 

A8

 

 

 

A5

 

5

24

 

 

A9

A4

 

 

 

 

 

 

 

6

23

 

 

A11

 

 

 

 

A3

 

 

 

 

 

 

 

 

 

 

7

22

 

 

OE

 

 

 

 

 

 

 

 

 

 

A2

 

8

21

 

 

A10

 

 

 

A1

 

9

20

 

 

 

 

 

 

 

 

CE

 

 

 

 

A0

 

10

19

 

 

DQ7

 

 

DQ0

 

11

18

 

 

DQ6

 

 

DQ1

 

12

17

 

 

 

DQ5

 

 

 

DQ2

 

13

16

 

 

DQ4

 

 

 

VSS

 

14

15

 

 

DQ3

 

 

 

PIN NAMES

 

A(12:0)

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

Chip Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

Output Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PE

 

 

Program Enable

 

 

 

 

 

 

 

 

 

 

 

 

DQ(7:0)

 

 

Data Input/Data Output

 

 

 

 

 

 

 

 

 

 

 

 

Table 1. Device Operation Truth Table 1

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

PE

 

CE

 

I/O MODE

 

MODE

 

 

 

 

 

 

 

 

 

 

X

 

1

 

1

 

 

Three-state

 

Standby

 

 

 

 

 

 

 

 

 

 

0

 

1

 

0

 

 

Data Out

 

Read

 

 

 

 

 

 

 

 

 

 

1

 

0

 

0

 

 

Data In

 

Program

 

 

 

 

 

 

 

 

 

 

1

 

1

 

0

 

 

Three-state

 

Read 2

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.“X” is defined as a “don’t care” condition.

2.Device active; outputs disabled.

ABSOLUTE MAXIMUM RATINGS 1

(Referenced to VSS)

SYMBOL

PARAMETER

LIMITS

UNITS

 

 

 

 

VDD

DC supply voltage

-0.3 to 7.0

V

VI/O

Voltage on any pin

-0.5 to (VDD + 0.5)

V

TSTG

Storage temperature

-65 to +150

°C

PD

Maximum power dissipation

1.5

W

TJ

Maximum junction temperature

+175

°C

ΘJC

Thermal resistance, junction-to-case 2

3.3

°C/W

II

DC input current

±10

mA

Notes:

1 . Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability. 2 . Test per MIL-STD-883, Method 1012, infinite heat sink.

2

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

LIMITS

UNITS

 

 

 

 

VDD

Positive supply voltage

4.5 to 5.5

V

TC

Case temperature range

-55 to +125

°C

 

 

 

 

VIN

DC input voltage

0 to VDD

V

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(VDD = 5.0V ±10%; -55°C < TC < +125°C)

SYMBOL

PARAMETER

 

 

 

 

CONDITION

MINIMUM

MAXIMUM

UNIT

 

 

 

 

 

 

 

 

 

VIH

High-level input voltage

 

(TTL)

2.4

 

V

 

VIL

Low-level input voltage

 

(TTL)

 

0.8

V

VOL1

Low-level output voltage

 

IOL = 4.8mA, V DD = 4.5V (TTL)

 

0.4

V

VOL2

Low-level output voltage

 

IOL = 200mA, VDD = 4.5V (CMOS)

 

VSS + 0.05

V

VOH1

High-level output voltage

 

IOH = -400mA, VDD = 4.5V (TTL)

2.4

 

V

 

 

 

 

 

IOH = -2.0mA

3.5

 

 

 

 

 

 

 

 

 

VOH2

High-level output voltage

 

IOH = -200mA VDD = 4.5V (CMOS)

4.45

 

V

 

 

 

 

 

I = -100mA

VDD - 0.3

 

 

 

 

 

 

 

OH

 

 

 

 

 

 

 

 

 

 

 

C

1

Input capacitance

 

¦ = 1MHz, V DD = 5.0V

 

15

pF

 

IN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CIO

1, 4

Bidirectional I/O capacitance

 

¦ = 1MHz, V DD = 5.0V

 

15

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOUT = 0V

 

 

 

 

 

 

 

 

 

 

 

 

IIN

Input leakage current

 

VIN = 0V to VDD

-1

1

mA

 

IOZ

Three-state output leakage

 

VO = 0V to VDD

-10

10

mA

 

 

 

current

 

VDD = 5.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE = 5.5V

 

 

 

 

 

 

 

 

 

 

 

 

I

 

2,3

Short-circuit output current

 

VDD = 5.5V, VO = V DD

 

90

mA

OS

 

 

 

VDD = 5.5V, VO = 0V

-90

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

(OP)5

Supply current operating

 

TTL input levels (IOUT = 0),

 

 

 

DD

 

@28.6MHz (35ns product)

 

VIL = 0.2V

 

100

mA

 

 

 

 

 

 

 

 

@22.2MHz (45ns product)

 

 

 

 

 

 

 

 

 

 

 

85

 

 

 

 

VDD, PE = 5.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDD(SB)

Supply current standby

 

CMOS input levels ,

 

500

mA

post-rad

 

 

VIL = V SS to 0.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE = VDD -025, VIH = V DD -0.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).

1.Measured only for initial qualification, and after process or design changes that could affect input/output capacitance.

2.Supplied as a design limit but not guaranteed or tested.

3.Not more than one output may be shorted at a time for maximum duration of one second.

4.Functional test.

5.Derates at 2.5mA/MHz.

3

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