UTMC 5962R0153601VYC, 5962R0153601VYA, 5962R0153601QYX, 5962H0153601VYX, 5962H0153601VYC Datasheet

Standard Products

UT54LVDM328 Octal 400 Mbps Bus LVDS Repeater

Data Sheet

August, 2002

FEATURES

q400.0 Mbps low jitter fully differential data path

q200MHz clock channel

q3.3 V power supply

q10mA LVDS output drivers

qCold sparing all pins

qFast propagation delay of 3.5ns max

qReceiver input threshold < + 100 mV

qRadiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019

-Total-dose: 300 krad(Si) and 1 Mrad(Si)

-Latchup immune (LET > 100 MeV-cm2 /mg)

qPackaging options:

-48-lead flatpack

qStandard Microcircuit Drawing 5962-01536

-QML Q and V compliant part

qCompatible with ANSI/TIA/EIA 644-1995 LVDS Standard

INTRODUCTION

The UT54LVDM328 is an Octal Bus Repeater utilizing Low Voltage Differential Signaling (LVDS) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. LVDS I/O enable high speed data transmission for point-to point or multi-drop interconnects. This device is designed for use as a high speed differential repeater.

The UT54LVDM328 is a repeater designed specifically for the bridging of multiple backplanes in a system. The UT54LVDM328 utilizes low voltage differential signaling to deliver high speed while consuming minimal power with reduced EMI. The UT54LVDM328 repeats signals between backplanes and accepts or drives signals onto the local bus.

The individual LVDS outputs can be put into Tri-State by use of the enable pins.

All pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS.

END
IN1+	+	OUT1+
IN1-	-	OUT1-
IN2+	+	OUT2+
IN2-	-	OUT2-

Figure 1a. UT54LVDM328 Repeater Block Diagram (Partial - see Page 2 for complete diagram)

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	END
	IN1+	+	OUT1+
	IN1-	-	OUT1-
	IN2+	+	OUT2+
	IN2-	-	OUT2-
	IN3+	+	OUT3+
	IN3-	-	OUT3-
	IN4+	+	OUT4+
	IN4-	-	OUT4-
	IN5+	+	OUT5+
	IN5-	-	OUT5-
	IN6+	+	OUT6+
	IN6-	-	OUT6-
	IN7+	+	OUT7+
	IN7-	-	OUT7-
	IN8+	+	OUT8+
	IN8-	-	OUT8-
	ENCK
	Clk In+	+	Clk Out+
	Clk In-		Clk Out-
		-

Figure 1b. UT54LVDM328 Repeater Diagram

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	IN1+		1		48		OUT1+
	IN1-		2		47		OUT1-
	IN2+		3		46		OUT2+
	IN2-		4		45		OUT2-
					44		VDD
	VDD		5
	VSS		6		43		VSS
	IN3+		7		42		OUT3+
					41		OUT3-
	IN3-		8
	IN4+		9		40		OUT4+
	IN4-		10		39		OUT4-
	ENCK		11
					38		VDD
	CLK In+		12
					37	CLK OUT+
	CLK In-		13
					36	CLK OUT-
			14
	END				35		VSS
	IN5+		15
				UT54LVDM328	34		OUT5+
	IN5-		16
				Bus Repeater	33		OUT5-
	IN6+		17		32		OUT6+
					31		OUT6-
	IN6-		18
							VDD
	VDD		19		30
	VSS		20		29		VSS
	IN7+		21		28		OUT7+
	IN7-		22		27		OUT7-
	IN8+		23		26		OUT8+
	IN8-		24		25		OUT8-

Figure 2. UT54LVDM328 Pinout

PIN DESCRIPTION

Name	# of Pins	Description
INn+	8	Non-inverting LVDS input
INn-	8	Inverting LVDS input
OUTn+	8	Non-inverting LVDS output
OUTn-	8	Inverting LVDS Output
END	1	A logic low on the enable puts
		the LVDS data output into Tri-
		State and reduces the supply
		current
ENCK	1	A logic low on the enable puts
		the LVDS clock output into Tri-
		State and reduces the supply
		current
VSS	5	Ground
VDD	5	Power supply
CLK IN+	1	Non-Inverting Clock LVDS
		Input
CLK IN-	1	Inverting clock LVDS Input
CLK	1	Non-Inverting Clock LVDS
OUT+		Output
CLK	1	Inverting Clock LVDS Output
OUT-

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APPLICATIONS INFORMATION

The UT54LVDM328 provides the basic bus repeater function. The device operates as a 9 channel LVDS buffer. Repeating the signal restores the LVDS amplitude, allowing it to drive another media segment. This allows for isolation of segments or long distance applications.

The intended application of these devices and signaling technique is for both point-to-point baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.)

Input Fail-Safe:

The UT54LVDM328 also supports OPEN, shorted and terminated input fail-safe. Receiver output will be HIGH for all fail-safe conditions.

PCB layout and Power System Bypass:

Circuit board layout and stack-up for the UT54LVDM328 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01μF to 0.1μ F. Tantalum capacitors may be in the range of 2.2μF to 10μF. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the UT54LVDM328, as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance and extends the effective frequency range of the bypass components.

The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding and isolation, as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity in signal transmission lines by providing short paths for image currents which reduces signal distortion. The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads.

Compatibility with LVDS standard:

In backplane multidrop configurations, with closely spaced loads, the effective differential impedance of the line is reduced. If the mainline has been designed for 50Ω differential impedance, the loading effects may reduce this to the 35Ω range depending upon spacing and capacitance load. Terminating the line with a 35Ω load is a better match than with 50Ω and reflections are reduced.

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ABSOLUTE MAXIMUM RATINGS1

(Referenced to VSS)

SYMBOL	PARAMETER	LIMITS
VDD	DC supply voltage	-0.3 to 4.0V
VI/O	Voltage on any pin	-0.3 to (VDD + 0.3V)
TSTG	Storage temperature	-65 to +150°C
PD	Maximum power dissipation	800mW
TJ	Maximum junction temperature2	+150°C
ΘJC	Thermal resistance, junction-to-case3	22°C/W
II	DC input current	±10mA

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.

2.Maximum junction temperature may be increased to +175°C during burn-in and life test .

3.Test per MIL-STD-883, Method 1012.

4.For cold spare mode (VDD = VSS), VI/O may be -0.3V to the maximum recommended operating V DD +0.3V.

RECOMMENDED OPERATING CONDITIONS

SYMBOL		PARAMETER	LIMITS
VDD		Positive supply voltage	3.3 to 3.6V
TC		Case temperature range	-55 to +125°C
VIN		DC input voltage, receiver inputs	0 to 2.4V
		DC input voltage, logic inputs	0 to VDD for END or ENCK

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