Standard Products
QCOTSTM UT9Q512 512K x 8 SRAM
Data Sheet
February, 2003
FEATURES
q20ns maximum (5 volt supply) address access time
qAsynchronous operation for compatibility with industrystandard 512K x 8 SRAMs
qTTL compatible inputs and output levels, three-state bidirectional data bus
qTypical radiation performance
-Total dose: 50krads
->100krads(Si), for any orbit, using Aeroflex UTMC patented shielded package
-SEL Immune >80 MeV-cm2 /mg
-LETTH(0.25) = >10 MeV-cm 2/mg
-Saturated Cross Section (cm2) per bit, 5.0E-9
-<1E-8 errors/bit-day, Adams to 90% geosynchronous heavy ion
qPackaging options:
-36-lead ceramic flatpack (weight 3.42 grams)
-36-lead flatpack shielded (weight 10.77 grams)
qStandard Microcircuit Drawing 5962-00536
-QML T and Q compliant part
INTRODUCTION
The QCOTST M UT9Q512 Quantified Commercial Off-the- Shelf product is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (E), an active LOW Output Enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected.
Writing to the devicei s accomplished by taking Chip Enable one (E) input LOW and Write Enable (W) inputs LOW. Data on the eight I/O pins (DQ0 through DQ7 ) is then written
into the location specified on the address pins (A0 through A18 ). Reading from the device is accomplished by taking
Chip Enable one (E) and Output Enable (G) LOW while forcing Write Enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed in a high impedance state when the device is deselected (E) HIGH), the outputs are disabled ( G HIGH), or during a write operation (E LOWand W LOW).
Clk. Gen. Pre-Charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
DQ - DQ
0 7
E
W
G
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Memory Array |
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SelectRow |
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1024 Rows |
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512x8 Columns |
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I/O Circuit |
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Column Select |
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Data |
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Control |
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CLK |
A10 |
A11 |
A12 |
A13 |
A14 |
A15 |
A16 |
A17 |
A18 |
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Gen. |
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Figure 1. UT9Q512 SRAM Block Diagram
A0 |
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1 |
36 |
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NC |
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A1 |
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2 |
35 |
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A18 |
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A2 |
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3 |
34 |
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A17 |
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A3 |
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4 |
33 |
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A16 |
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A4 |
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5 |
32 |
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A15 |
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E |
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6 |
31 |
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G |
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DQ0 |
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7 |
30 |
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DQ7 |
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DQ1 |
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8 |
29 |
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DQ6 |
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V |
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9 |
28 |
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VS S |
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D D |
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VD D |
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VSS |
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10 |
27 |
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DQ2 |
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11 |
26 |
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DQ5 |
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DQ3 |
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12 |
25 |
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DQ4 |
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W |
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13 |
24 |
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A14 |
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A5 |
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14 |
23 |
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A13 |
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A6 |
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15 |
22 |
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A12 |
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A7 |
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16 |
21 |
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A11 |
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A8 |
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17 |
20 |
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A10 |
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A9 |
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18 |
19 |
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NC |
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Figure 2. UT9Q512 25ns SRAM Pinout (36) (For both shielded and unshielded packages)
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PIN NAMES |
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A(18:0) |
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Address |
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DQ(7:0) |
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Data Input/Output |
E |
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Enable |
W |
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Write Enable |
G |
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Output Enable |
VDD |
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Power |
VSS |
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Ground |
DEVICE OPERATION
The UT9Q512 has three control inputs called Enable 1 ( E), Write Enable ( W), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). E Device Enable controls device selection, active, and standby modes. Asserting E enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G |
W |
E |
I/O Mode |
Mode |
X1 |
X |
1 |
3-state |
Standby |
X |
0 |
0 |
Data in |
Write |
1 |
1 |
0 |
3-state |
Read2 |
0 |
1 |
0 |
Data out |
Read |
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Notes:
1.“X” is defined as a “don’t care” condition.
2.Device active; outputs disabled.
READ CYCLE
A combination of W greater than VIH (min) and E less than V IL (max) defines a read cycle. Read access time is measured from the latter of Device Enable, Output Enable, or valid address to valid data output.
SRAM Read Cycle 1, the Address Access in figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as Device Enable and Output Enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable - Controlled Access in figure 3b, is initiated by E going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable - Controlled Access in figure 3c, is initiated by G going active while E is asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.
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WRITE CYCLE
A combination of W less than VIL(max) and E less than
VIL(max) defines a write cycle. The state of G is a “don’t care” for a write cycle. The outputs are placed in the high-impedance state when either G is greater than V IH(min), or when W is less than VIL(max).
Write Cycle 1, the Write Enable - Controlled Access in figure 4a, is defined by a write terminated by W going high, with E still active. The write pulse width is defined by t WLWH when the write is initiated by W, and by t ETWH when the write is initiated by E. Unless the outputs have been previously placed in the highimpedance state byG, the user must wait t WLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable - Controlled Access in figure 4b, is defined by a write terminated by E going inactive. The write pulse width is defined by tWLEF when the write is initiated
by W, and by tETEF when the write is initiated by the E going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state
by G, the user must wait t WLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
Table 2. Radiation Hardness
Design Specifications1
Total Dose |
50 |
krad(Si) |
Heavy Ion |
<1E-8 |
Errors/Bit-Day |
Error Rate2 |
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Notes:
1.The SRAM will not latchup during radiation exposure under recommended operating conditions.
2.10% worst case particle environment, Geosynchronous orbit, 0.025 mils of Aluminum.
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ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL |
PARAMETER |
VDD |
DC supply voltage |
VI/O |
Voltage on any pin |
TSTG |
Storage temperature |
PD |
Maximum power dissipation |
TJ |
Maximum junction temperature2 |
ΘJC |
Thermal resistance, junction-to-case3 |
II |
DC input current |
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LIMITS
-0.5 to 7.0V -0.5 to 7.0V -65 to +150°C 1.0W
+150°C
10°C/W
±10 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.
2.Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3.Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS |
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SYMBOL |
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PARAMETER |
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LIMITS |
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VDD |
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Positive supply voltage |
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4.5 to 5.5V |
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TC |
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Case temperature range |
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(C) screening: -55° to +125°C |
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(E) screening: -40° to +125°C |
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VIN |
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DC input voltage |
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0V to VDD |
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DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* |
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(-55°C to +125°C for (C) screening and -40oC to +125oC for (W) screening) (V |
DD |
= 5.0V + 10%) |
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SYMBOL |
PARAMETER |
CONDITION |
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MIN |
MAX |
UNIT |
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VIH |
High-level input voltage |
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2.0 |
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V |
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VIL |
Low-level input voltage |
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0.8 |
V |
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VOL1 |
Low-level output voltage |
IOL = 8mA, V DD =4.5V |
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0.4 |
V |
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VOL2 |
Low-level output voltage |
IOL = 200mA,VDD =4.5V |
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0.05 |
V |
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VOH1 |
High-level output voltage |
IOH = -4mA,VDD =4.5V |
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2.4 |
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V |
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VOH2 |
High-level output voltage |
IOH = -200mA,VDD =4.5V |
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3.2 |
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V |
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CIN |
Input capacitance |
¦ = 1MHz @ 0V |
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10 |
pF |
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1 |
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CIO |
Bidirectional I/O capacitance |
¦ = 1MHz @ 0V |
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12 |
pF |
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1 |
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IIN |
Input leakage current |
VIN = VDD and VSS, VDD = VDD (max) |
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-2 |
2 |
mA |
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IOZ |
Three-state output leakage current |
VO = VDD and VSS |
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-2 |
2 |
mA |
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VDD = VDD (max) |
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G = VDD (max) |
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IOS |
Short-circuit output current |
VDD = VDD (max), VO = VDD |
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-90 |
90 |
mA |
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2, 3 |
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VDD = VDD (max), VO = 0V |
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IDD(OP) |
Supply current operating |
Inputs: VIL = 0.8V, |
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125 |
mA |
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@ 1MHz |
VIH = 2.0V |
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IOUT = 0mA |
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VDD = VDD (max) |
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IDD1(OP) |
Supply current operating |
Inputs: VIL = 0.8V, |
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180 |
mA |
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@40MHz |
VIH = 2.0V |
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IOUT = 0mA |
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VDD = VDD (max) |
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IDD2 (SB) |
Supply current standby |
Inputs: VIL = VSS |
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-55°C and 25°C |
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6 |
mA |
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@0MHz |
IOUT = 0mA |
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-40°C and 25°C |
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6 |
mA |
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E = VDD - 0.5 |
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125°C |
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12 |
mA |
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VDD = VDD (max) |
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VIH = VDD - 0.5V |
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Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 .
1.Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2.Supplied as a design limit but not guaranteed or tested.
3.Not more than one output may be shorted at a time for maximum duration of one second.
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