UTMC 5962P0053604TXX, 5962P0053604TXC, 5962P0053604TXA, 5962P0053604TUX, 5962P0053604TUC Datasheet

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Standard Products

QCOTSTM UT9Q512 512K x 8 SRAM

Data Sheet

February, 2003

FEATURES

q20ns maximum (5 volt supply) address access time

qAsynchronous operation for compatibility with industrystandard 512K x 8 SRAMs

qTTL compatible inputs and output levels, three-state bidirectional data bus

qTypical radiation performance

-Total dose: 50krads

->100krads(Si), for any orbit, using Aeroflex UTMC patented shielded package

-SEL Immune >80 MeV-cm2 /mg

-LETTH(0.25) = >10 MeV-cm 2/mg

-Saturated Cross Section (cm2) per bit, 5.0E-9

-<1E-8 errors/bit-day, Adams to 90% geosynchronous heavy ion

qPackaging options:

-36-lead ceramic flatpack (weight 3.42 grams)

-36-lead flatpack shielded (weight 10.77 grams)

qStandard Microcircuit Drawing 5962-00536

-QML T and Q compliant part

INTRODUCTION

The QCOTST M UT9Q512 Quantified Commercial Off-the- Shelf product is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (E), an active LOW Output Enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected.

Writing to the devicei s accomplished by taking Chip Enable one (E) input LOW and Write Enable (W) inputs LOW. Data on the eight I/O pins (DQ0 through DQ7 ) is then written

into the location specified on the address pins (A0 through A18 ). Reading from the device is accomplished by taking

Chip Enable one (E) and Output Enable (G) LOW while forcing Write Enable (W) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (DQ0 through DQ7) are placed in a high impedance state when the device is deselected (E) HIGH), the outputs are disabled ( G HIGH), or during a write operation (E LOWand W LOW).

Clk. Gen. Pre-Charge Circuit

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

DQ - DQ

0 7

E

W

G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Array

 

 

 

SelectRow

 

 

 

 

1024 Rows

 

 

 

 

 

 

 

512x8 Columns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O Circuit

 

 

 

 

 

 

 

Column Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data

 

 

 

 

 

 

 

 

 

 

 

 

 

Control

 

 

 

 

 

 

 

 

 

CLK

A10

A11

A12

A13

A14

A15

A16

A17

A18

Gen.

 

 

 

 

 

 

 

 

 

Figure 1. UT9Q512 SRAM Block Diagram

A0

 

 

1

36

 

NC

 

 

A1

 

 

2

35

 

A18

 

 

A2

 

 

3

34

 

A17

 

 

A3

 

 

4

33

 

A16

 

 

A4

 

 

5

32

 

A15

 

 

E

 

 

6

31

 

G

 

 

DQ0

 

 

7

30

 

DQ7

 

 

DQ1

 

 

8

29

 

DQ6

 

 

V

 

 

9

28

 

VS S

 

 

D D

 

 

 

VD D

VSS

 

 

10

27

 

 

 

DQ2

 

 

11

26

 

DQ5

 

 

DQ3

 

 

12

25

 

DQ4

 

 

W

 

 

13

24

 

A14

 

 

A5

 

 

14

23

 

A13

 

 

A6

 

 

15

22

 

A12

 

 

A7

 

 

16

21

 

A11

 

 

A8

 

 

17

20

 

A10

 

 

A9

 

 

18

19

 

NC

 

 

Figure 2. UT9Q512 25ns SRAM Pinout (36) (For both shielded and unshielded packages)

 

PIN NAMES

A(18:0)

 

Address

 

DQ(7:0)

 

Data Input/Output

E

 

Enable

W

 

Write Enable

G

 

Output Enable

VDD

 

Power

VSS

 

Ground

DEVICE OPERATION

The UT9Q512 has three control inputs called Enable 1 ( E), Write Enable ( W), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). E Device Enable controls device selection, active, and standby modes. Asserting E enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

G

W

E

I/O Mode

Mode

X1

X

1

3-state

Standby

X

0

0

Data in

Write

1

1

0

3-state

Read2

0

1

0

Data out

Read

 

 

 

 

 

Notes:

1.“X” is defined as a “don’t care” condition.

2.Device active; outputs disabled.

READ CYCLE

A combination of W greater than VIH (min) and E less than V IL (max) defines a read cycle. Read access time is measured from the latter of Device Enable, Output Enable, or valid address to valid data output.

SRAM Read Cycle 1, the Address Access in figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as Device Enable and Output Enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV).

SRAM read Cycle 2, the Chip Enable - Controlled Access in figure 3b, is initiated by E going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0).

SRAM read Cycle 3, the Output Enable - Controlled Access in figure 3c, is initiated by G going active while E is asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.

2

WRITE CYCLE

A combination of W less than VIL(max) and E less than

VIL(max) defines a write cycle. The state of G is a “don’t care” for a write cycle. The outputs are placed in the high-impedance state when either G is greater than V IH(min), or when W is less than VIL(max).

Write Cycle 1, the Write Enable - Controlled Access in figure 4a, is defined by a write terminated by W going high, with E still active. The write pulse width is defined by t WLWH when the write is initiated by W, and by t ETWH when the write is initiated by E. Unless the outputs have been previously placed in the highimpedance state byG, the user must wait t WLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention.

Write Cycle 2, the Chip Enable - Controlled Access in figure 4b, is defined by a write terminated by E going inactive. The write pulse width is defined by tWLEF when the write is initiated

by W, and by tETEF when the write is initiated by the E going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state

by G, the user must wait t WLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention.

TYPICAL RADIATION HARDNESS

Table 2. Radiation Hardness

Design Specifications1

Total Dose

50

krad(Si)

Heavy Ion

<1E-8

Errors/Bit-Day

Error Rate2

 

 

 

 

 

Notes:

1.The SRAM will not latchup during radiation exposure under recommended operating conditions.

2.10% worst case particle environment, Geosynchronous orbit, 0.025 mils of Aluminum.

3

ABSOLUTE MAXIMUM RATINGS1

(Referenced to VSS)

SYMBOL

PARAMETER

VDD

DC supply voltage

VI/O

Voltage on any pin

TSTG

Storage temperature

PD

Maximum power dissipation

TJ

Maximum junction temperature2

ΘJC

Thermal resistance, junction-to-case3

II

DC input current

 

 

LIMITS

-0.5 to 7.0V -0.5 to 7.0V -65 to +150°C 1.0W

+150°C

10°C/W

±10 mA

Notes:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.

2.Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3.Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

 

 

 

SYMBOL

 

PARAMETER

 

LIMITS

 

 

 

 

VDD

 

Positive supply voltage

 

4.5 to 5.5V

 

TC

 

Case temperature range

 

(C) screening: -55° to +125°C

 

 

 

 

 

(E) screening: -40° to +125°C

 

VIN

 

DC input voltage

 

0V to VDD

4

UTMC 5962P0053604TXX, 5962P0053604TXC, 5962P0053604TXA, 5962P0053604TUX, 5962P0053604TUC Datasheet

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

 

 

 

 

 

 

 

(-55°C to +125°C for (C) screening and -40oC to +125oC for (W) screening) (V

DD

= 5.0V + 10%)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYMBOL

PARAMETER

CONDITION

 

 

MIN

MAX

UNIT

 

VIH

High-level input voltage

 

 

 

 

 

 

2.0

 

V

 

VIL

Low-level input voltage

 

 

 

 

 

 

 

0.8

V

 

VOL1

Low-level output voltage

IOL = 8mA, V DD =4.5V

 

 

 

 

 

0.4

V

 

 

 

 

 

 

 

 

VOL2

Low-level output voltage

IOL = 200mA,VDD =4.5V

 

 

 

 

0.05

V

 

VOH1

High-level output voltage

IOH = -4mA,VDD =4.5V

 

 

 

 

2.4

 

V

 

VOH2

High-level output voltage

IOH = -200mA,VDD =4.5V

 

 

3.2

 

V

 

CIN

Input capacitance

¦ = 1MHz @ 0V

 

 

 

 

 

10

pF

 

1

 

 

 

 

 

 

 

 

 

 

 

CIO

Bidirectional I/O capacitance

¦ = 1MHz @ 0V

 

 

 

 

 

12

pF

 

1

 

 

 

 

 

 

 

 

 

 

 

IIN

Input leakage current

VIN = VDD and VSS, VDD = VDD (max)

 

-2

2

mA

 

IOZ

Three-state output leakage current

VO = VDD and VSS

 

 

 

 

-2

2

mA

 

 

 

VDD = VDD (max)

 

 

 

 

 

 

 

 

 

 

G = VDD (max)

 

 

 

 

 

 

 

 

IOS

Short-circuit output current

VDD = VDD (max), VO = VDD

 

-90

90

mA

 

2, 3

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD = VDD (max), VO = 0V

 

 

 

 

 

 

IDD(OP)

Supply current operating

Inputs: VIL = 0.8V,

 

 

 

 

 

125

mA

 

 

@ 1MHz

VIH = 2.0V

 

 

 

 

 

 

 

 

 

 

IOUT = 0mA

 

 

 

 

 

 

 

 

 

 

VDD = VDD (max)

 

 

 

 

 

 

 

 

IDD1(OP)

Supply current operating

Inputs: VIL = 0.8V,

 

 

 

 

 

180

mA

 

 

@40MHz

VIH = 2.0V

 

 

 

 

 

 

 

 

 

 

IOUT = 0mA

 

 

 

 

 

 

 

 

 

 

VDD = VDD (max)

 

 

 

 

 

 

 

 

IDD2 (SB)

Supply current standby

Inputs: VIL = VSS

 

-55°C and 25°C

 

 

6

mA

 

 

@0MHz

IOUT = 0mA

 

-40°C and 25°C

 

 

6

mA

 

 

 

E = VDD - 0.5

 

 

 

125°C

 

 

12

mA

 

 

 

VDD = VDD (max)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIH = VDD - 0.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 .

1.Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2.Supplied as a design limit but not guaranteed or tested.

3.Not more than one output may be shorted at a time for maximum duration of one second.

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