UTMC 5962-8957501XC, 5962-8957501XX Datasheet

RTS-1
UTI760A RTS Remote Terminal for Stores
F
Complete MIL-STD-1760A Notice I through III remote terminal interface
1K x 16 of on-chip static RAM for message data, completely accessible to host
Self-test capability, including continuous loop-back compare
Programmable memory mapping via pointers for efficient use of internal memory, including buffering multiple messages per subaddress
R T-RT Terminal Address Compare
Command word stored with incoming data for enhanced data management
User selectable RAM Busy (RBUSY) signal for slow or fast processor interfacing
Full military operating temperature range, -55°C to +125
°
C, screened to the specific test methods listed in
T able I of MIL-STD-883, Method 5004, Class B, also Standard Military Drawing available
Available in 68-pin pingrid array package
I
NTRODUCTION
The UT1760A RTS is a monolithic CMOS VLSI solution to the requirements of the dual-redundant MIL-STD-1553B interface as specified by MIL-STD-1760A. Designed to reduce cost and space in the mission stores interface, the RTS integrates the remote terminal logic with a user­configured 1K x 16 static RAM. In addition, the RTS has a flexible subsystem interface to permit use with most processors or controllers.
The RTS provides all protocol, data handling, error checking, and memory control functions, as well as comprehensive self-test capabilities. The RTS’s memory meets all of a mission store’s message storage needs through user-defined memory mapping. This memory-mapped architecture allows multiple message buffering at
DECODER
COMMAND RECOGNITION
DECODER
ENCODER
MUX
OUT
OUT
IN
IN
MCSA(4:0)
RTA(4:0) REMOTE TERMINAL ADDRESS
MODE CODE/ SUBADDRESS
CONTROL AND ERROR LOGIC
CONTROL INPUTS
STATUS OUTPUTS
1K X 16 RAM
ADDR(9:0)
PTR REGISTER
DATA(15:0)
2MHz
12MHz
RESET
CLOCK AND RESET
LOGIC
Figure 1. UT1760A RTS Functional Block Diagram
OUTPUT MULTIPLEXING AND
SELF-TEST WRAP AROUND LOGIC
RTS-2
Table of Contents
1.0 ARCHITECTURE AND OPERATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Memory Map and Host Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 RTS RAM Pointer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Mode Code and Subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 MIL-STD-1760A Subaddress and Mode Code Definitions . . . . . . . . . . . . . . . 9
1.6 Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.7 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.8 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.9 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.10 RT-RT Transfer Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.11 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.0 MEMORY MAP EXAMPLE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.0 PIN IDENTIFICATION AND DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.0 MAXIMUM AND RECOMMENDED OPERATING CONDITIONS
22
5.0 DC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.0 AC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
7.0 PACKAGE OUTLINE DRAWING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
RTS-3
1.0 A
RCHITECTURE AND OPERATION
The UT1760A RTS is an interface device linking a MIL­STD-1553 serial data bus and a host microprocessor system. The RTS’s MIL-STD-1553B interface includes encoding/ decoding logic, error detection, command recognition, 1K x 16 of SRAM, pointer registers, clock, and reset circuits. Illegal subaddress circuitry makes the RTS MIL-STD­1760A-specific.
1.1 Memory Map and Host Memory Interface
The host can access the 1K x 16 RAM memory like a standard RAM device through the 10-bit address and 16-bit data buses. The host uses the Chip Select (CS
), Read/Write
(RD/WR
), and Output Enable (OE) signals to control data
transfer to and from memory . When the RTS requires access
to its own internal RAM, it asserts the RBUSY signal to alert the host. The RBUSY signal is programmable via the internal Control Register to be asserted either 5.7ms or
2.7ms prior to the RTS needing access to its internal RAM. The RTS stores MIL-STD-1760A messages in 1K x 16 of
on-chip RAM. For efficient use of the 1K x 16 memory on the R TS, the host programs a set of pointers to map where the 1760A message is stored. The RTS uses the upper 64 words (address 3C0 (hex) through 3FF (hex)) as pointers. The RTS pro vides pointers for all 30 recei ve subaddresses, all 30 transmit subaddresses, and four mode code commands with associated data words as defined in MIL-STD-1553B. The remaining 960 words of memory contain receive, transmit, and mode code data in a host-defined structure.
Figure 2. RTS Memory Map
15 MSB 0 LSB
RTS Memory Map
3C0 (hex)
3DF (hex)
3C1 (hex)
3DE (hex)
RCV SUBADDRESS 01
RCV SUBADDRESS 30
XMIT VECTOR WORD MODE CODE (W/DATA)
SYNCHRONIZE MODE CODE (W/DATA)
15 MSB 0 LSB
3FF (hex)
XMIT LAST COMMAND MODE CODE (W/DATA)
XMT BIT WORD MODE CODE (W/DATA)
3E0 (hex)
XMT SUBADDRESS 30
3FE (hex)
3E1 (hex)
15 MSB 0 LSB
000 (hex)
3BF(hex)
Message Storage Locations
Receive Message Pointers
Transmit Message Pointers
(3C1 TO 3DE)
(3E1 TO 3FE)
XMT SUBADDRESS 01
RTS-4
1.2 RTS RAM Pointer Structure
The RAM 16-bit pointers have a 6-bit index field and a 10-bit address field. The 6-bit index field allows for the storage of up to 64 messages per subaddress. A message consists of the 1553 command word and its associated data words.
The 16-bit pointer for Transmit Last Command Mode Code is located at memory location 3E0 (hex). The T ransmit Last Command Mode Code pointer buffers up to 63 command words. An example of command word storage follows:
Example: 3E0 (hex) Contents = FC00 (hex)
11 1111 00 0000 0000 Address Field = 000 (hex)
Index Field = 3F (hex)
First command word storage location (3E0 = F801):
Address Field = 001 (hex) Index Field = 3E (hex)
Sixty-third command word storage location
(3E0 = 003F):
Address Field = 03F (hex) Index Field = 00 (hex)
Sixty-fourth command word storage location (3E0 = 003F) (previous command word overwritten):
Address Field = 03F (hex) Index Field = 00 (hex)
The Transmit Last Command Mode Code has Address Field boundary conditions for the location of command word buffers. The host can allocate a maximum 63 sequential locations following the Address Field starting address. F or proper operation, the Address Field must start on an I x 40 (hex) address boundary, where I is greater than or equal to zero and less than or equal to 14. A list of valid Index and Address Fields follows:
Figure 3. Message Pointer Structure
MESSAGE INDEX MESSAGE DATA ADDRESS
15 (MSB) 0 (LSB)
Message Index: Defines the maximum messages buffered for the given subaddress.
Message Data Address: Indicates the starting memory address for incoming message storage.
10 9
I Valid Index Fields Valid Address Fields
0 3F (hex) to 00 (hex) 000 (hex) to 03F(hex) 1 3F (hex) to 00 (hex) 040 (hex) to 07F (hex) 2 3F (hex) to 00 (hex) 080 (hex) to 0BF(hex) 3 3F (hex) to 00 (hex) 0C0 (hex) to 0FF (hex) 4 3F (hex) to 00 (hex) 100 (hex) to 13F (hex) 5 3F (hex) to 00 (hex) 140 (hex) to 17F (hex) 6 3F (hex) to 00 (hex) 180 (hex) to 1BF (hex) 7 3F (hex) to 00 (hex) 1C0 (hex) to 1FF (hex) 8 3F (hex) to 00 (hex) 200 (hex) to 23F (hex) 9 3F (hex) to 00 (hex) 240 (hex) to 27F (hex) 10 3F (hex) to 00 (hex) 280 (hex) to 2BF (hex) 11 3F (hex) to 00 (hex) 2C0 (hex) to 2FF (hex) 12 3F (hex) to 00 (hex) 300 (hex) to 33F (hex) 13 3F (hex) to 00 (hex) 340 (hex) to 37F (hex) 14 3F (hex) to 00 (hex) 380 (hex) to 3BF (hex)
RTS-5
1.3 Internal Registers
The RTS uses two internal registers to allow the host to control the RTS operation and monitor its status. The host uses the Control (CTRL
) signal along with Chip Select (CS),
Read/Write (RD/WR
), and Output Enable (OE) to read the 16-bit Status Register or write to the 13-bit Control Register . No address data is needed to select a register. The Control Register toggles bits in the MIL-STD-1553B status word,
enables the biphase inputs, recognizes broadcast commands, selects Notice I and II or III, determines RAM Busy (RBUSY) timing, selects disconnect or terminal active flag, and puts the part in self-test mode. The Status Register supplies operational status of the UT1760A RTS to the host. These registers must be initialized before attempting RTS operation. Internal registers can be accessed while RBUSY is active.
Subaddress/Mode Code RAM Location Subaddress/Mode Code RAM Location
Transmit Vector Word Mode Code 3C0 (hex) Transmit Last Command Mode Code 3E0 (hex) Receive Subaddress 01 3C1 (hex) Transmit Subaddress 01 3E1 (hex) Receive Subaddress 02 3C2 (hex) Transmit Subaddress 02 3E2 (hex) Receive Subaddress 03 3C3 (hex) Transmit Subaddress 03 3E3 (hex) Receive Subaddress 04 3C4 (hex) Transmit Subaddress 04 3E4 (hex) Receive Subaddress 05 3C5 (hex) Transmit Subaddress 05 3E5 (hex) Receive Subaddress 06 3C6 (hex) Transmit Subaddress 06 3E6 (hex) Receive Subaddress 07 3C7 (hex) Transmit Subaddress 07 3E7 (hex) Receive Subaddress 08 3C8 (hex) Transmit Subaddress 08 3E8 (hex) Receive Subaddress 09 3C9 (hex) Transmit Subaddress 09 3E9 (hex) Receive Subaddress 10 3CA (hex) Transmit Subaddress 10 3EA (hex) Receive Subaddress 11 3CB (hex) Transmit Subaddress 11 3EB (hex) Receive Subaddress 12 3CC (hex) Transmit Subaddress 12 3EC (hex) Receive Subaddress 13 3CD (hex) Transmit Subaddress 13 3ED (hex) Receive Subaddress 14 3CE (hex) Transmit Subaddress 14 3EE (hex) Receive Subaddress 15 3CF (hex) Transmit Subaddress 15 3EF (hex) Receive Subaddress 16 3D0 (hex) Transmit Subaddress 16 3F0 (hex) Receive Subaddress 17 3D1 (hex) Transmit Subaddress 17 3F1 (hex) Receive Subaddress 18 3D2 (hex) Transmit Subaddress 18 3F2 (hex) Receive Subaddress 19 3D3 (hex) Transmit Subaddress 19 3F3 (hex) Receive Subaddress 20 3D4 (hex) Transmit Subaddress 20 3F4 (hex) Receive Subaddress 21 3D5 (hex) Transmit Subaddress 21 3F5 (hex) Receive Subaddress 22 3D6 (hex) Transmit Subaddress 22 3F6 (hex) Receive Subaddress 23 3D7 (hex) Transmit Subaddress 23 3F7 (hex) Receive Subaddress 24 3D8 (hex) Transmit Subaddress 24 3F8 (hex) Receive Subaddress 25 3D9 (hex) Transmit Subaddress 25 3F9 (hex) Receive Subaddress 26 3DA (hex) Transmit Subaddress 26 3FA (hex) Receive Subaddress 27 3DB (hex) Transmit Subaddress 27 3FB (hex) Receive Subaddress 28 3DC (hex) Transmit Subaddress 28 3FC (hex) Receive Subaddress 29 3DD (hex) Transmit Subaddress 29 3FD (hex) Receive Subaddress 30 3DE (hex) Transmit Subaddress 30 3FE (hex) Synchronize w/Data Word Mode Code 3DF (hex) Transmit Bit Word Mode Code 3FF (hex)
RTS-6
Control Register (Write Only)
The 13-bit write-only Control Register manages the operation of the RTS. Write to the Control Register by applying a logic one to OE
, and a logic zero to CTRL, CS, and RD/WR. Data is loaded into the Control Register via I/O pins DATA(12:0).
Control register write must occur 50ns before the rising edge of COMSTR
to latch data into the outgoing status word.
Bit Number
Initial Condition
Description
Bit 0 [1] Channel A Enable. A logic 1 enables Channel A biphase inputs. Bit 1 [1] Channel B Enable. A logic 1 enables Channel B biphase inputs. Bit 2 [0] Terminal Flag. A logic 1 sets the Terminal Flag bit of the Status Word. Bit 3 [1] System Busy. A logic 1 sets the Busy bit of the Status Word and limits RTS access to the
memory. No data word can be retrieved or stored; command words will be stored. Bit 4 [0] Subsystem Busy. A logic 1 sets the Subsystem Flag bit of the Status Word. Bit 5 [0] Self-Test Channel Select. This bit selects which channel the self-test checks; a logic 1 selects
Channel A and a logic 0 selects Channel B. Bit 6 [0] Self-Test Enable. A logic 1 places the RTS in the internal self-test mode and inhibits normal
operation. Channels A and B should be disabled if self-test is chosen. Bit 7 [0] Service Request. A logic 1 sets the Service Request bit of the Status Word. Bit 8 [0] Instrumentation. A logic 1 sets the Instrumentation bit of the Status Word. Bit 9 [1] Broadcast Enable. A logic 1 enables the RTS to recognize broadcast commands. Bit 10 [1] Notice Select. A logic 1 enables Notice III operation; logic 0 enables Notice I or II operation. Bit 11 [1] DSCNCT/TERA
CT Pin Select. A logic 1 selects the “Disconnect” function; a logic 0 selects
the “Terminal Active” function. Bit 12 [1] RBUSY Time Select. A logic 1 selects a 5.7µs RBUSY alert; a logic 0 selects a 2.7µs
RBUSY alert. [] - Values in parentheses indicate the initialized values of these bits.
X X X NO
TICE
PS BCEN INS SRQ ITST SUBS BUSY TF CH BENCH A
EN
ITCSRBUSY
TS
[1]
Figure 4a. Control Register
[1][0][1][0][0][0][0][0][1][1][1][1]
[ ] defines reset state
CONTROL REGISTER (WRITE ONLY):
MSB
LSB
RTS-7
Status Register (Read Only):
The 16-bit read-only Status Register provides the R TS system status. Read the Status Register by applying a logic 0 to CTRL , CS
, and OE, and a logic 1 to RD/WR. The 16-bit contents of the Status Register are read from data I/O pins DATA(15:0).
Bit Number
Initial Condition
Description
Bit 0 [0] MCSA0. The LSB of the mode code or subaddress as indicated by the logic state of bit 5. Bit 1 [0] MCSA1. Mode code or subaddress as indicated by the logic state of bit 5. Bit 2 [0] MCSA2. Mode code or subaddress as indicated by the logic state of bit 5. Bit 3 [0] MCSA3. Mode code or subaddress as indicated by the logic state of bit 5. Bit 4 [0] MCSA4. Mode code or subaddress as indicated by the logic state of bit 5. Bit 5 [0] MC/SA. A logic 1 indicates that bits 4 through 0 are the subaddress of the last command word,
and that the last command word was a normal transmit or receive command. A logic 0 indicates that bits 4 through 0 are a mode code, and that the last command was a mode command.
Bit 6 [1] Channel A/B
. A logic 1 indicates that the most recent command arri v ed on Channel A; a logic 0
indicates that it arrived on Channel B.
Bit 7 [1] Channel B Enabled. A logic 1 indicates that Channel B is available for both reception and
transmission.
Bit 8 [1] Channel A Enabled. A logic 1 indicates that Channel A is available for both reception and
transmission.
Bit 9 [1] Terminal Flag Enabled. A logic 1 indicates that the Bus Controller has not issued an Inhibit
Terminal Flag Mode Code. A logic 0 indicates that the Bus Controller, via the above mode code, is overriding the host system’s ability to set the Terminal Flag bit of the status word.
Bit 10 [1] Busy. A logic 1 indicates the Busy bit is set. This bit is reset when the System Busy bit in the
Control Register is reset.
Bit 11 [0] Self-Test. A logic 1 indicates that the chip is in the internal self-test mode. This bit is reset
when the self-test is terminated.
Bit 12 [0] TA Parity Error. A logic 1 indicates the wrong Terminal Address parity; it causes the biphase
inputs to be disabled. TA Parity Error results in the Message Error bit being set to a logic one, and Channels A and B become disabled.
Bit 13 [0] Message Error. A logic 1 indicates that a message error has occurred since the last Status Reg-
ister read. This bit is not reset until the Status Register has been examined. Message error con­dition must be removed before reading the Status Register to reset the Message Error bit.
Bit 14 [0] Valid Message. A logic 1 indicates that a valid message has been received since the last Status
Register read. This bit is not reset until the Status Register has been examined.
Bit 15 [0] Terminal Active. A logic 1 indicates the device is executing a transmit or receive operation.
Same as TERA
CT output except active high. (Always TERACT; never DSCNCT.)
[] - Values in parentheses indicate the initialized values of these bits.
SELF­TEST
TERM ACTV
VAL MESS
MESS ERR
TAPA ERR
BUSY TFEN CH AENCH BENCHNL
A/B
MCSA 4MCSA 3MCSA 2MCSA 1MCSA
0
MC/ SA
[0][0][0][0][0][0][1][1][1][1][1][0][0][0][0][0]
[ ] defines reset state
STATUS REGISTER (READ ONLY):
MSB LSB
Figure 4b. Status Register
RTS-8
1.4 Mode Code and Subaddress
The UT1760A RTS provides two modes of illegal subaddress decoding, one meeting MIL-STD-1760A Notices I and II, and the other meeting MIL-STD-1760A Notice III. In addition, the device has automatic internal illegal command decoding for reserved MIL-STD-1553B mode codes. These definitions are extracted from MIL­STD-1760A and reviewed in section 1.5 of this document. Upon command word validation and decode, status pins MCSA(4:0) and MC
/SA become valid. Status pin MC/SA
will indicate whether the data on pins MCSA(4:0) is mode code or subaddress information. Status Register bits 0 through 5 contain the same information as pins MCSA(4:0) and MC
/SA. The system designer can use signals
MCSA(4:0), MC
/SA, BRDCST, RTRT, etc. to illegalize mode codes, subaddresses, and other message formats (broadcast and RT-to-RT) via the Illegal Command (ILLCOM) input to the part.
RTS MODE CODE HANDLING PROCEDURE
T/R Mode Code Function Operation
0 10100 Selected Transmitter Shutdown
2
1. Command word stored
2. MERR pin asserted
3. MERR bit set in Status Register
4. Status word transmitted
0
10101
Override Selected Transmitter Shutdown
2
1. Command word stored
2. MERR pin asserted
3. MERR bit set in Status Register
4. Status word transmitted
0 10001 Synchronize (w/Data) 1. Command word stored
2. Data word stored
3. Status word transmitted
1 00000 Dynamic Bus Control
2
1. Command word stored
2. MERR pin asserted
3. MERR bit set in Status Register
4. Status word transmitted
1 00001 Synchronize
1
1. Command word stored
2. Status word transmitted
1 00010 Transmit Status Word 3 1. Command word stored
2. Status word transmitted
1 00011 Initiate Self-Test
1
1. Command word stored
2. Status word transmitted
1 00100 Transmitter Shutdown 1. Command word stored
2. Alternate bus shutdown
3. Status word transmitted
1 00101 Override Transmitter Shutdown 1. Command word stored
2. Alternate bus enabled
3. Status word transmitted
1 00110 Inhibit Terminal Flag Bit 1. Command word stored
2. Terminal Flag bit set to zero and disabled
3. Status word transmitted
1 00111 Override Inhibit Terminal Flag 1. Command word stored
2. Terminal Flag bit enabled, but not set to logic one
3. Status word transmitted
1 01000 Reset Remote Terminal
1
1. Command word stored
2. Status word transmitted
1 10010 Transmit Last Command
Word 3
1. Status word transmitted
2. Last command word transmitted
1 10000 Transmit Vector Word 1. Command word stored
2. Status word transmitted
3. Data word transmitted
1 10011 Transmit BIT Word 1. Command word stored
2. Status word transmitted
3. Data word transmitted
Notes:
1. Further host interaction required for mode code operation.
2. Reserved mode code; A) MERR pin asserted, B) MESS ERR bit set, C) status word transmitted (ME bit set to logic one).
3. Status word not affected.
4. Undefined mode codes are treated as reserved mode codes.
RTS-9
1.5 MIL-STD-1760A Subaddress and Mode Code Definitions
Table 1. Subaddress and Mode Code Definitions Per MIL-STD-1760A Notice I
Subaddress Field Binary (Decimal)
Message Format
Description
Receive Transmit
00000 (00) B.40.1.1.3
1
B.40.1.1.3 Mode Code Indicator 00001 (01) Reserved B.40.2.1 2 Store Description 00010 (02) User Defined User Defined 00011 (03) Reserved Reserved 00100 (04) User Defined User Defined 00101 (05) Reserved Reserved 00110 (06) User Defined User Defined 00111 (07) User Defined User Defined 01000 (08) Reserved Reserved 01001 (09) User Defined User Defined 01010 (10) User Defined User Defined 01011 (11) Reserved Reserved 01100 (12) User Defined User Defined 01101 (13) User Defined User Defined 01110 (14) Reserved Reserved 01111 (15) Reserved User Defined 10000 (16) User Defined User Defined 10001 (17) User Defined User Defined 10010 (18) User Defined User Defined 10011 (19) Reserved Reserved Nuclear Weapon 10100 (20) User Defined User Defined 10101 (21) Reserved User Defined 10110 (22) User Defined User Defined 10111 (23) User Defined User Defined 11000 (24) User Defined User Defined 11001 (25) User Defined User Defined 11010 (26) User Defined User Defined 11011 (27) Reserved Reserved Nuclear Weapon 11100 (28) User Defined User Defined 11101 (29) User Defined User Defined 11110 (30) User Defined User Defined 11111 (31) B.40.1.1.3 B.40.1.1.3 Mode Code Indicator
Notes:
1. Refer to section B.40.1.1.3 of the MIL-STD-1760A specification for definition.
2. Refer to section B.40.2.1 of the MIL-STD-1760A specification for definition.
3. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted.
RTS-10
Table 2. Subaddress and Mode Code Definitions Per MIL-STD-1760A Notice II
Subaddress Field Binary (Decimal)
Message Format
Description
Receive Transmit
00000 (00) B.40.1.1.3
1
B.40.1.1.3 Mode Code Indicator 00001 (01) Reserved B.40.2.1 2 Store Description 00010 (02) User Defined User Defined 00011 (03) Reserved Reserved 00100 (04) User Defined User Defined 00101 (05) Reserved Reserved 00110 (06) User Defined User Defined 00111 (07) User Defined User Defined 01000 (08) Reserved Reserved 01001 (09) User Defined User Defined 01010 (10) User Defined User Defined 01011 (11) Reserved Reserved 01100 (12) User Defined User Defined 01101 (13) User Defined User Defined 01110 (14) Reserved Reserved 01111 (15) Reserved User Defined 10000 (16) User Defined User Defined 10001 (17) User Defined User Defined 10010 (18) User Defined User Defined 10011 (19) Reserved Reserved Nuclear Weapon 10100 (20) User Defined User Defined 10101 (21) Reserved User Defined 10110 (22) User Defined User Defined 10111 (23) User Defined User Defined 11000 (24) User Defined User Defined 11001 (25) User Defined User Defined 11010 (26) User Defined User Defined 11011 (27) Reserved Reserved Nuclear Weapon 11100 (28) User Defined User Defined 11101 (29) User Defined User Defined 11110 (30) User Defined User Defined 11111 (31) B.40.1.1.3 B.40.1.1.3 Mode Code Indicator
Notes:
1. Refer to section B.40.1.1.3 of the MIL-STD-1760A specification for definition.
2. Refer to section B.40.2.1 of the MIL-STD-1760A specification for definition.
3. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted.
RTS-11
Table 3. Subaddress and Mode Code Definitions Per MIL-STD-1760A Notice III
Subaddress Field Binary (Decimal)
Message Format
Description
Receive Transmit
00000 (00) B.40.1.1.3
1
B.40.1.1.3 Mode Code Indicator 00001 (01) Reserved B.40.2.1 2 Store Description 00010 (02) User Defined User Defined 00011 (03) User Defined User Defined 00100 (04) User Defined User Defined 00101 (05) User Defined User Defined 00110 (06) User Defined User Defined 00111 (07) User Defined User Defined 01000 (08) Reserved Reserved Test Only 01001 (09) User Defined User Defined 01010 (10) User Defined User Defined 01011 (11) B.40.2.2.1 3 B.40.2.2.1 Mission Store Control/Monitor 01100 (12) User Defined User Defined 01101 (13) User Defined User Defined 01110 (14) B.40.1.1.5.8 4 B.40.1.5.8 Mass Data Transfer 01111 (15) User Defined User Defined 10000 (16) User Defined User Defined 10001 (17) User Defined User Defined 10010 (18) User Defined User Defined 10011 (19) B.40.2.2.4
5
B.40.2.2.5
6
Nuclear W eapon 10100 (20) User Defined User Defined 10101 (21) User Defined User Defined 10110 (22) User Defined User Defined 10111 (23) User Defined User Defined 11000 (24) User Defined User Defined 11001 (25) User Defined User Defined 11010 (26) User Defined User Defined 11011 (27) B.40.2.2.4 B.40.2.2.5 Nuclear Weapon 11100 (28) User Defined User Defined 11101 (29) User Defined User Defined 11110 (30) User Defined User Defined 11111 (31) B.40.1.1.3 B.40.1.1.3 Mode Code Indicator
Notes:
1. Refer to section B.40.1.1.3 of the MIL-STD-1760A specification for definition.
2. Refer to section B.40.2.1 of the MIL-STD-1760A specification for definition.
3. Refer to section B.40.2.2.1 of the MIL-STD-1760A specification for definition.
4. Refer to section B.40.1.1.5.8 of the MIL-STD-1760A specification for definition.
5. Refer to section B.40.2.2.4 of the MIL-STD-1760A specification for defi nition.
6. Refer to section B.40.2.2.5 of the MIL-STD-1760A specification for definition.
7. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted.
RTS-12
1.6 Terminal Address
The Terminal Address of the RTS is programmed via five input pins: RTA(4:0) and R TPTY. Asserting MRST
latches the R TS’ s T erminal Address from pins R TA(4:0) and parity bit R TPTY. The address and parity cannot change until the next assertion of the MRST
. The parity of the Terminal Address is odd; input pin RTPTY is set to a logic state to satisfy this requirement. A logic 1 on Status Register bit 12 indicates incorrect Terminal Address parity. An example follows:
RTA(4:0) = 05 (hex) = 00101 RTPTY = 1 (hex) = 1
Sum of 1’s = 3 (odd), Status Register bit 12 = 0
RTA(4:0) = 04 (hex) = 00100 RTPTY = 0 (hex) = 0 Sum of 1’s = 1 (odd), Status Register bit 12 = 0
RTA(4:0) = 04 (hex) = 00100 RTPTY = 1 (hex) = 1 Sum of 1’s = 2 (even), Status Register bit 12 = 1
The RTS checks the T erminal Address and parity on Master Reset. The state of the DSCNCT signal indicates the mated status of the store. When all six Terminal Address pins (R TA(4:0), RTPTY) go to a logic one, the DSCNCT pin is asserted. T o enable the disconnect function (DSCNCT pin) bit 11 of the Control Register is set to a logic one. With broadcast disabled, RTA (4:0) = 11111 operates as a normal RT address.
1.7 Internal Self-Test
Setting bit 6 of the Control Register to a logic one enables the internal self-test. Disable Channels A and B at this time to prevent bus activity during self-test by setting bits 0 and 1 of the Control Register to a logic zero. Normal operation is inhibited when internal self-test is enabled. The self-test capability of the RTS is based on the f act that the MIL-STD­1553B status word sync pulse is identical to the command word sync pulse. Thus, if the status word from the encoder is fed back to the decoder, the RTS will recognize the incoming status word as a command word and thus cause the RTS to transmit another status word. After the host inv okes self-test, the RTS self-test logic forces a status word transmission even though the RTS has not received a valid command. The status word is sent to decoder A or B depending on the channel the host selected for self-test. The self-test is controlled by the host periodically changing the bit patterns in the status word being transmitted. Writing to the Control Register bits 2, 3, 4, 7, 8, and 10 changes the status word. Monitor the self-test by sampling either the Status Register or the external status pins (i.e., Command Strobe (COMSTR
), Transmit/Recei ve (T/R)). For more detailed explanation of internal self-test, consult UTMC publication
RTR/RTS Internal Self-Test Routine.
1.8 Power-up and Master Reset
After power-up, reset initializes the part with its biphase ports enabled, latches the T erminal Address, selects Notice III subaddress decoding, and turns on the busy option. The device is ready to accept commands from the MIL-STD­1553B bus. The busy flag is asserted while the host is loading the message pointers and messages. After this task is completed, the host removes the busy condition via a Control Register write to the RTS. On power-up if the terminal address parity (odd) is incorrect, the biphase inputs are disabled and the message error pin (MERR) is asserted. This condition can also be monitored via bit 12 of the Status Register. The MERR pin is negated on reception of first valid command.
1.9 Encoder and Decoder
The RTS interf aces directly to a bus transmitter/ receiver via the RTS Manchester II encoder/decoder. The UT1760A RTS receives the command word from the MIL-STD­1553B bus and processes it either by the primary or secondary decoder. Each decoder checks for the proper sync pulse and Manchester waveform, edge ske w, correct number of bits, and parity. If the command is a receive command, the RTS processes each incoming data word for correct format and checks the control logic for correct word count and contiguous data. If an inv alid message error is detected, the message error pin is asserted, the RTS ceases processing the remainder (if any) of the message, and it then suppresses status word transmission. Upon command validation recognition, the external status outputs are enabled. Reception of illegal commands does not suppress status word transmission.
The RTS automatically compares the transmitted word (encoder word) to the reflected decoder word by way of the continuous loop-back feature. If the encoder word and reflected word do not match, the transmitter error pin (TXERR) is asserted. In addition to the loop-back compare test, a timer precludes a transmission greater than 760µs by the assertion of Fail-safe T imer (TIMER
ON). This timer is reset upon receipt of another command. (RT-to-R T transfer time-out = 57µs).
1.10 RT-RT Transfer Compare
The RT-to-R T T erminal Address compare logic makes sure that the incoming status word’ s Terminal Address matches the T erminal Address of the transmitting RT specified in the command word. An incorrect match results in setting the message error bit and suppressing transmission of the status word.
RTS-13
1.11 Illegal Command Decoding
The host has the option of asserting the ILLCOM pin to illegalize a received command w ord. On receipt of an illegal command, the RTS sets the Message Error bit in the status word, sets the message error output, and sets the message error latch in the Status Register.
The following RTS outputs may be used to externally decode an illegal command, Mode Code or Subaddress indicator (MC
/SA), Mode Code or Subaddress bus
MCSA(4:0), Command Strobe (COMSTR
), Broadcast
(BRDCST
), and Remote Terminal to Remote Terminal
transfer (RTRT) (see figure 21 on page 34.) To illegalize a transmit command, the ILLCOM pin must
be asserted within 3.3µs after VALMSG goes to a logic 1 if the RTS is to respond with the Message Error bit of the status word at a logic 1. If the illegal command is mode code 2, 4, 5, 6, 7, or 18, the ILLCOM pin must be asserted within 664ns after Command Strobe (COMSTR
) transitions to logic 0. Asserting the ILLCOM pin within the 664ns inhibits the mode code function. For mode code illegalization, assert the ILLCOM pin until the VALMSG signal is asserted.
For an illegal receiv e command, the ILLCOM pin must be asserted within 18.2µs after the COMSTR
transitions to a logic 0 in order to suppress data words from being stored. In addition, the ILLCOM pin must be at a logic 1 throughout the reception of the message until VALMSG is asserted. This does not apply to illegal transmit commands since the status word is transmitted first.
The above timing conditions also apply when the host externally decodes an illegal broadcast command. The host must remove the illegal command condition so that the next command is not falsely decoded as illegal.
2.0 M
EMORY MAP EXAMPLE
Figures 5 and 6 illustrate the UT1760A RTS b uffering three receive command messages to Subaddress 4. The receive message pointer for Subaddress 4 is located at 03C4 (hex) in the 1K x 16 RAM. The 16-bit contents of location 03C4 (hex) point to the memory location where the first receive message is stored. The Address Field defined as bits 0 through 9 of address 03C4 (hex) contain address information. The Index Field defined as bits 10 through 15 of address 03C4 (hex) contain the message buffer inde x (i.e., number of messages buffered).
Figure 5 demonstrates the updating of the message pointer as each message is received and stored. The memory storage of these three messages is shown in figure 6. After receiving the third message for Subaddress 4 (i.e., Index Field equals zero) the Address Field of the message pointer is not incremented. If the host does not update the receive message pointer for Subaddress 4 before the next receive command for Subaddress 4 is accepted, the third message will be overwritten.
Figures 7 and 8 show an example of multiple message retrieval from Subaddress 16 upon reception of a MIL-STD­1553B transmit command. The message pointer for transmit Subaddress 16 is located at 03F0 (hex) in the 1K x 16 RAM. The 16-bit contents of location 03F0 (hex) point to the memory location where the first message data words are stored.
Figure 7 demonstrates the updating of the message pointer as each message is received and stored. The data memory for these three messages is shown in figure 8.
RTS-14
MIL-STD-1553 Bus Activity:
Figure 5. RTS Message Handling
Receive Subaddress 4; data pointer at 03C4 (hex). (Initial condition)
0840 (hex)
03C4 (hex)
INDEX = 0000 10 ADDRESS = 00 0100 0000
0445 (hex)
03C4 (hex)
INDEX = 0000 01 ADDRESS = 00 0100 0101
After message #1, 4 data words plus command word.
0048 (hex)
03C4 (hex)
INDEX = 0000 00 ADDRESS = 00 0100 1000
After message #2, 2 data words plus command word.
0048 (hex)
03C4 (hex)
INDEX = 0000 00 ADDRESS = 00 0100 1000
After message #3, 4 data words plus command word.
Example: Remote terminal will receive and buffer three MIL-STD-1553 receive commands of various word lengths to Subaddress 4.
CMD WORD #1 DW1 DW2 DW3DW0
CMD WORD #2 DW1DW0
CMD WORD #3 DW1 DW3DW0
SA = 4
SA = 4
SA = 4
T/R
= 0
T/R
= 0
T/R
= 0
WC = 4
WC = 2
WC = 4
DW2
040 (hex) 041 (hex) 042 (hex) 043 (hex) 044 (hex) 045 (hex) 046 (hex) 047 (hex) 048 (hex) 049 (hex) 04A (hex) 04B (hex) 04C (hex)
Figure 6. Memory Storage Subaddress 4
COMMAND WORD #2
DATA WORD 0 DATA WORD 1
DATA WORD 2 DATA WORD 3
COMMAND WORD #1
DATA WORD 1
COMMAND WORD #3
DATA WORD 0 DATA WORD 1 DATA WORD 2 DATA WORD 3
DATA WORD 0
0840 (hex)
03C4 (hex)
0445 (hex)
03C4 (hex)
0048 (hex)
03C4 (hex)
0048 (hex)
03C4 (hex)
RTS-15
Figure 7. RTS Message Handling
0830 (hex) INDEX = 0000 10
ADDRESS = 00 0011 0000
0434 (hex)
03F0 (hex)
INDEX = 0000 01 ADDRESS = 00 0011 0100
After message #1, 4 data words.
0036 (hex)03F0 (hex)
INDEX = 0000 00 ADDRESS = 00 0011 0110
After message #2, 2 data words.
0036 (hex)03F0 (hex)
INDEX = 0000 00 ADDRESS = 00 0011 0110
After message #3, 4 data words.
Example: Remote terminal will transmit and buffer three MIL-STD-1553 transmit commands of various word lengths to Subaddress 16.
CMD WORD #1
DW1
SW
CMD WORD #2
DW1
CMD WORD #3
DW1 DW2 DW3DW0
MIL-STD-1553 Bus Activity:
SA = 16 T/R
= 1
SA = 16 T/R = 1 WC = 4
SA = 16 T/R = 1 WC = 2
WC = 4
Transmit Subaddress 16; data pointer at 03F0 (hex). (Initial condition)
03F0 (hex)
DW0
SW
SW
DW3
DW2
SW0
030 (hex) 031 (hex) 032 (hex) 033 (hex)
034 (hex)
035 (hex) 036 (hex) 037 (hex) 038 (hex) 039 (hex)
Figure 8. Memory Storage Subaddress 16
DATA WORD 0 DATA WORD 1
DATA WORD 2 DATA WORD 3
DATA WORD 1
DATA WORD 0 DATA WORD 1 DATA WORD 2 DATA WORD 3
DATA WORD 0
0830 (hex)
03F0(hex)
0434 (hex)
03F0 (hex)
0036 (hex)
0
3F0 (hex)
0036 (hex)
3F0 (hex)
034 (hex)
ote:
xample is valid only if message structure is known in advance.
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