UTMC 5962-8950101YC, 5962-8950101XX, 5962-8950101XC, 5962-8950101XA Datasheet

BCRTMP-1
UT1553 BCRTMP
FEATURES
p Comprehensive MIL-STD-1553 dual-redundant Bus
Controller (BC) and Remote Terminal (RT) functions
p Multiple message processing capability in BC and
RT modes
p Time tagging and message logging in RT mode p Automatic polling and intermessage delay in
BC mode
p Programmable interrupt scheme and internally
generated interrupt history list
p Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
p Register-oriented architecture to enhance
programmability
p DMA memory interface with 64K addressability p Eight mode select inputs configure the device for a
wide variety of 1553 protocols: MIL-STD-1553A, MIL-STD-1553B, McDonnell Douglas A3818, A5232, A5690, Grumman Aerospace SP-G-151A
p Comprehensive Built-In-Test (BIT) includes:
Continuous on-line wrap-around test, off-line BIT, special system wrap-around test
p Available in 144-pin pingrid array or 132-lead flatpack
packages
p Standard Microcircuit Drawing 5962-89501 available
- QML Q compliant
16
16
16
CONTROL
DMA/CPU
MESSAGE
RT PROTOCOL
MESSAGE
BC PROTOCOL
HANDLER
INTERRUPT
CONVER-
PARALLEL
SERIAL-TO-
CONVER-
TO-SERIAL
PARALLEL-
MODULE
DECODER
ENCODER/
CHANNEL
DUAL
BUS
TRANSFER
LOGIC
ADDRESS
16
TIMEOUT
TIMRONA
CLOCK &
RESET
12MHz
MASTER RESET
GENERATOR
ADDRESS
16
1553
HIGH-PRIORITY
RT ADDRESS
STANDARD INTERRUPT
HIGH-PRIORITY
INTERRUPT LOG
CURRENT COMMAND
BUILT-IN-TEST WORD
POLLING COMPARE
CURRENT BC BLOCK/
STATUS
CONTROL
REGISTERS
LIST POINTER
DATA
16
BUILT-
IN-
TEST
16
16
RT TIMER
INTERRUPT STATUS
INTERRUPT ENABLE
SION
SION
&
HANDLER
&
HANDLER
DATA CHANNEL B
1553
DATA CHANNEL A
LOGIC
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
DMA ARBITRATION
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
RT DESCRIPTOR SPACE
ENABLE
BUILT-IN-TEST
START COMMAND RESET COMMAND
RESET COMMAND ACTIVITY STATUS/
OPERATIONAL MODE
PROGRAMMABLE STATUS
WRAP-AROUNDTEST
MULTIPLEXER
TIMRONB
Figure 1. BCRTMP BlockDiagram
BCRTMP-2
Table of Contents
1.0 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Features - Remote Terminal (RT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Features - Bus Controller (BC) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Features - Multiple Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0 PIN IDENTIFICATION AND DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0 SYSTEM OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.0 SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1 DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 CPU Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4 RAM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5 Legalization Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6 Transmitter/Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.0 REMOTE TERMINAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1 RT Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1.1 RT Subaddress Descriptor Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1.2 Message Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.3 Mode Code Descriptor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 RT Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3 RT Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.0 BUS CONTROLLER ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 BC Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3 BC Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.4 BC Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.5 BC Operational Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.0 MULTIPLE PROTOCOL OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.1 Legalization Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.2 Broadcast Option Select (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.3 RT Response Time Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.4 Mode Code Option Select (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.5 Status Word Option Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.6 Message Error Technique Select (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.7 Mode code with Data Select (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.8 Remote Terminal Time Out Option Select (BC, RT) . . . . . . . . . . . . . . . . . . 43
8.2 Additional UT1553 BCRTMP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2.1 DOMC Do Mode Code Control Signal (RT) . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2.2 Continuous Wrap-Around Circuitry (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.3 Stop Enable (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.4 Forced Busy (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.5 ACTIVE Signal (RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.6 Transmitter Inhibit Signals (BC, RT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.7 Immediate Clear Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.8 Status Word Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.0 EXCEPTION HANDLING AND INTERRUPT LOGGING . . . . . . . . . . . . . . . . . . . . 46
10.0 MAXIMUM AND RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . 50
11.0 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.0 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.0 PACKAGE OUTLINE DRAWINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
BCRTMP-3
1.0 INTRODUCTION
The monolithic CMOS UT1553 BCRTMP provides the system designer with an intelligent solution to MIL-STD-1553 multiplexed serial data bus design problems. The UT1553 BCRTMP is a single-chip device that implements two of the three defined MIL-STD-1553 functions - Bus Controller and Remote Terminal - and is flexible enough to conform to many of the MIL-STD-1553 “industry standards” created between and including releases of MIL-STD-1553A and MIL-STD-1553B. Designed to reduce host CPU overhead, the BCRTMP’s powerful state machines automatically execute message transfers, provide interrupts, and generate status information. The BCRTMP’s register-based architecture allows it to conform to the many protocol options regarding status words, mode codes, use of Broadcast, Message Error, and RT Response Time as specified in the various “1553 standards.” Multiple registers offer many programmable functions as well as extensive information for host use. In the BC mode, the BCRTMP uses a linked-list message scheme to provide the host with message chaining capability. The BCRTMP enhances memory use by supporting variable-size, relocatable data blocks. In the RT mode, the BCRTMP implements time­tagging and message history functions. It also supports multiple (up to 128) message buffering and variable length messages to any subaddress.
The UT1553 BCRTMP is an intelligent, versatile, and easy to implement device -- a powerful asset to system designers.
1.1 Features - Remote Terminal (RT) Mode Indexing
The BCRTMP is programmable to index or buffer messages on a subaddress-by-subaddress basis. The BCRTMP, which can index as many as 128 messages, can also assert an interrupt when either the selected number of messages is reached or every time a specified subaddress is accessed.
Variable Space Allocation
The BCRTMP can use as little or as much memory (up to 64K) as needed.
Selectable Data Storage
Address programmability within the BCRTMP provides flexible data placement and convenient access.
Sequential Data Storage
The BCRTMP stores/retrieves, by subaddress, all messages in the order in which they are transacted.
Sequential Message Status Information
The BCRTMP provides message validity, time-tag, and
word-count information, and stores it sequentially in a separate, cross-referenced list.
Illegalizing Mode Codes and Subaddresses
The host can declare mode codes and subaddresses illegal by setting the appropriate bit(s) in memory.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt with provision for high and standard priority interrupts.
Interrupt History List
The BCRTMP provides an Interrupt History List that records, in the order of occurrence, the events that caused the interrupts. The list length is programmable.
1.2 Features - Bus Controller (BC) Mode Multiple Message Processing
The BCRTMP autonomously processes any number of messages or lists of messages that may be stored in a 64K memory space.
Automatic Intermessage Delay
When programmed by the host, the BCRTMP can delay a host-specified time before executing the next message in sequence.
Automatic Polling
When polling, the BCRTMP interrogates the remote terminals and then compares their status word responses to the contents of the Polling Compare Register. The BCRTMP can interrupt the host CPU if an erroneous remote terminal status word response occurs.
Automatic Retry
The BCRTMP can automatically retry a message on busy, message error, and/or response time-out conditions. The BCRTMP can retry up to four times on the same or on the alternate bus.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt with provision for high and standard priority interrupts.
Interrupt History List
The BCRTMP provides an Interrupt History List that records, in the order of occurrence, the events that caused the interrupts. The list length is programmable.
Variable Space Allocation
The BCRTMP uses as little or as much memory (up to 64K) as needed.
Selectable Data Storage
Address programmability within the BCRTMP provides flexible data placement and convenient access.
BCRTMP-4
1.3 Features - Multiple Protocol
Since the inception of the loosely defined MIL-STD-1553A in 1973, various “1553 standards” have developed, all with their own peculiarities. The UT1553 BCRTMP addresses MIL-STD-1553A, MIL-STD-1553B, McDonnell Douglas A3818, McDonnell Douglas A5232, McDonnell Douglas A5690, and Grumman Aerospace SP-G-151A. While the part was designed with these “standards” specifically in mind, the BCRTMP’s flexibility permits conformance to nearly any conceivable “1553-like standard.” The basic differences among the various “standards” fall into five categories:
1) Status Word Definition
2) Mode Code Definition
3) Use of Broadcast
4) Message Error Handling
5) Remote Terminal (RT) Response Time
Status Word Definition
The BCRTMP can operate in a mode where the status word is defined in strict conformance with MIL-STD-1553B, or it can operate in a more flexible mode. In this flexible status word mode, the user can program the individual status word bits using internal registers.
Mode Code Definition
The designer can place the BCRTMP in an operational mode so that the device performs in strict conformance with the mode code definitions for MIL-STD-1553B. The designer may also opt not to automatically execute mode codes, providing flexibility in mode code definition and illegalization.
Use of Broadcast
The BCRTMP has a programmable mode option that allows the user to determine whether to allow broadcast commands in a system.
Message Error Handling
Some 1553 protocols (e. g., MIL-STD-1553B) consider any message error reason to discard the entire message and suppress status word transmission, while others (e. g., McDonnell Douglas A3818) define the required activity according to message error severity. The BCRTMP can be programmed to conform to either requirement.
Remote Terminal (RT) Response Time
The BCRTMP offers two methods of legalization (Bus Legalization and DMA Legalization), which the designer selects depending on the required RT response time.
BCRTMP-5
BUSYACK
Figure 2. BCRTMP Functional Pin Description
D0
D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
LGL0 LGL1 LGL2 LGL3 LGL4 LGL5 LGL6 LGL7 LGL8 LGL9
LGL10
RAZ
RAO
RBZ
RBO
TAZ
TAO
TBZ
TBO
RTA0 RTA1
RTA2 RTA3 RTA4
RTPTY
MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 MDO0
MCLK MCLKD2 CLK
VDD VDD VDD VDD
VSS VSS VSS VSS
WRAPEN WRAPF
ALTWRAP
FBUSY
DMAR DMAG
DMAGO
DMACK
BURST
TSCTL
BRDCAST
MC
LGLEN
LGLCMD
ERR
DOMC
STDINTL STDINTP
HPINT TIMRONA TIMRONB
COMSTR
SSYSF
BCRTF
CHA/B
TEST
RD
WR
CS
AEN
BCRTSEL
LOCK
EXTOVR
MRST
MEMCSO
MEMCSI
RRD
RWR
DATA LINES
++
D1 D2 D3
++ ++ ++
++
ADDRESS LINES +
MODE OUTPUTS*
MODE SELECT INPUTS**
CLOCK SIGNALS
POWER
GROUND
WRAP-AROUND TEST SIGNALS
FORCED BUSY SIGNALS
DMA SIGNALS
LEGALIZATION BUS*
LEGALIZATION SIGNALS
CONTROL SIGNALS
STATUS SIGNALS
TERMINAL ADDRESS**
BIPHASE IN
BIPHASE OUT
+ +
** ** **
+
+
* Pin at high impedance when MRST is low. ** Pin internally pulled up. + Pin at high impedance when not asserted. ++ Bidirectional pin. *** Formerly MEMWIN.
( ) Pingrid array pin identification in parentheses.
Flatpack pin numbers not in parentheses.
ACTIVE
2.0 PIN IDENTIFICATION AND DESCRIPTION
24 25 26 27 28 29 30 31 36 37 38 39 40 41 42 43
91 92 93 94 95 96 97 102 103 104 105 106 107 108 109 110
23 22 21 20 19 18 17 16
(N6) (P6) (P7) (N7) (R6) (R7) (P8) (R8) (R9)
(R10)
(P9) (P10) (N10) (R11) (R12) (R13)
14 13 12 11 10 9 8
58 74 3
132 34 67 100
1 33 66 99
6 5 4
(B10)
(B9)
(C9) (A10)
(A9)
(B8)
(A8)
(A7)
(A6)
(B7)
(B6)
(C6)
(A5)
(A4)
(A3)
(B4)
(R4) (P5) (R3) (N5) (P4) (P3) (P2) (N3)
(P1) (N2)
(L3)
(M2)
(N1)
(M1)
(L1)
(K14)
(E15)
(J1)
(H3) (N9)
(G13)
(C7)
(J3)
(N8)
(H13)
(C8) (K2)
(J2)
(K1)
(L13) (M14) (K13) (M15)
53 52 57 56
51 50 55 54
44 45 46 47 48 49
82 83 84 85 86 81
90 128 129
89
59
62
63
61
60
87
15
88
7 69 64 70 71
122 123 127 124 125 126
111 112 113 114 115 116 117 118 119 120 121
72 73 78 75 77 76
79 80
(N14) (P14) (L14) (N15)
(P12) (N11) (P13) (R14) (N12) (N13)
(C13) (B14) (B13) (B12) (C11) (D13) (C10) (G1) (H2) (A12) (J14)***
(J15) (H14) (K15) (J13) (A13) (M3) (B11) (K3) (G15) (H15) (F15) (G14)
(D1) (F3) (F1) (F2) (G2) (G3)
(C5) (B3) (A2) (C4) (C3) (B2) (C2) (D2) (E3) (C1) (E2)
(F14) (F13) (E13) (D15) (D14) (C15)
(C14) (B15)
**
BCRTMP-6
A0 24
R13
TTB Bit 0 (LSB) of the Address bus A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
25 26 27 28 29 30 31 36 37 38 39
R12
R11
N10
P10
P9
R10
R9
R8
P8
R7
R6
TTB
TTB
TTB
Bit 1 of the Address bus Bit 2 of the Address bus Bit 3 of the Address bus Bit 4 of the Address bus Bit 5 of the Address bus Bit 6 of the Address bus Bit 7 of the Address bus Bit 8 of the Address bus Bit 9 of the Address bus Bit 10 of the Address bus Bit 11 of the Address bus
40
N7
A13 A14
41 42
P7
P6
TTO
TTO
TTO
NAME
PIN NUMBER F/P PGA
TYPE ACTIVE DESCRIPTION
A15 43
N6
TTO
TTO
TTO
TTO
TTO
TTO
TTO
TTO
TTO
Bit 12 of the Address bus
Bit 13 of the Address bus Bit 14 of the Address bus Bit 15 (MSB) of the Address bus
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Legend for TYPE and ACTIVE fields:
TUI = TTL input (pull-up) AL = Active low AH = Active high ZL = Active low - inactive state is high impedance TI = TTL input TO = TTL output TTO = Three-state TTL output TTB = Bidirectional
Notes:
1. Address and data buses are in the high-impedance state when idle.
2. Flatpack pin numbers are same as LCC.
ADDRESS BUS
BCRTMP-7
TTB TTB TTB TTB
D0 D1 D2 D3
91 B10 92 93 94
B9 C9
A10
Bit 0 (LSB) of the Data bus Bit 1 of the Data bus Bit 2 of the Data bus
Bit 3 of the Data bus D4 D5 D6
D7 D8 D9 D10 D11
95 96
97 102 103
104 105
106
A9 B8 A8
A7 A6 B7 B6 C6
TTB TTB TTB
TTB TTB TTB TTB TTB
Bit 4 of the Data bus Bit 5 of the Data bus Bit 6 of the Data bus
Bit 7 of the Data bus Bit 8 of the Data bus Bit 9 of the Data bus Bit 10 of the Data bus Bit 11 of the Data bus
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
NAME TYPE ACTIVE DESCRIPTION
DATA BUS
D12 D13 D14 D15
107 108 109 110
A5 A4 A3 B4
TTB TTB TTB TTB
Bit 12 of the Data bus Bit 13 of the Data bus Bit 14 of the Data bus Bit 15 (MSB) of the Data bus
--
--
--
--
PIN NUMBER F/P PGA
NAME TYPE ACTIVE DESCRIPTION
RTA0
TERMINAL ADDRESS INPUTS
44 P12 TUI Remote Terminal Address Bit 0 (LSB). The entire
RT address is strobed in at Master Reset. Verify it by reading the Remote Terminal Address Register. All the Remote Terminal Address bits are internally pulled up.
RTA1 45 N11 TUI Remote Terminal Address Bit 1. This is bit 1 of
the Remote Terminal Address.
RTA2 46 P13 TUI Remote Terminal Address Bit 2. This is bit 2 of
the Remote Terminal Address.
RTA3 47 R14 TUI Remote Terminal Address Bit 3. This is bit 3 of
the Remote Terminal Address.
--
--
--
--
RTPTY 49 N13 TUI Remote Terminal (Address) Parity. This is an odd
parity input for the Remote Terminal Address.
RTA4 48 N12 TUI Remote Terminal Address Bit 4. This is bit 4
(MSB) of the Remote Terminal Address.
--
--
PIN NUMBER F/P PGA
BCRTMP-8
61
62
63
K15
J15
H14
TI
TI
TI
AL
AL
AL
AEN 60 J13 TI AH
BCRTSEL 87 A13 TUI --
LOCK 15
88
M3
B11
TUI
TUI
AH
AL
7 K3 AL
NAME TYPE ACTIVE DESCRIPTION
CONTROL SIGNALS
69
64
G15
H15
TO
TUI
AL
AL
71 G14 TO AL
70 F15 TO AL
TI
Read. The host uses this in conjunction with CS to read an internal BCRT register.
Write. The host uses this in conjunction with CS to write an internal BCRTMP register.
BC/RT Select. This selects between either the Bus Controller or Remote Terminal mode. The BC/RT Mode Select bit in the Control Register overrides this input if the LOCK pin is not high. This pin is internally pulled high.
Lock. When set, this pin prevents internal changes to the RT address and BC/RT mode select functions as well as the Operation Mode select (MD7-MD0) functions. This pin is internally pulled high.
External Override. Use this in multi-redundant applications. Upon receipt, the BCRTMP aborts all current activity. EXTOVR should be connected to COMSTR output of the adjacent BCRTMP when used. This pin is internally pulled high.
Memory Chip Select Out. This is the regenerated MEMCSI input for external RAM during the pseudo­dual-port RAM mode. The BCRTMP also uses it to select external memory during memory accesses.
RD
WR
CS
EXTOVR
MRST
MEMCSO
MEMCSI
RRD
RWR
Memory Chip Select In. Used in the pseudo-dual-port RAM mode only, MEMCSI is received from the host and is propagated through to the MEMCSO. This pin is internally pulled high.
RAM Read. In the pseudo-dual-port RAM mode, the host uses this signal in conjunction with MEMCSO to read from external RAM through the BCRTMP. It is also the signal the BCRTMP uses to read from memory. It is asserted following receipt of DMAG. When the BCRTMP performs multiple reads, this signal is pulsed.
RAM Write. In the pseudo-dual-port RAM mode, the CPU and BCRTMP use this to write to external RAM. This signal is asserted following receipt of DMAG. For multiple writes, this signal is pulsed.
PIN NUMBER
F/P PGA
Chip Select. This selects the BCRTMP when accessing the BCRTMP’s internal register.
Address Enable. The host CPU uses AEN to indicate to the BCRTMP that the BCRTMP’s address lines can be asserted; this is a precautionary signal provided to avoid address bus crash. If not used, it must be tied high.
Master Reset. This resets all internal state machines, encoders, decoders, and registers. The minimum pulse width for a successful Master Reset is 500ns.
BCRTMP-9
82
83
84
C13
B14
B13
TTO
TO
TTO
ZL
AL
ZL
NAME TYPE ACTIVE DESCRIPTION
85
89
90
B12
A12
C10
TO
TO
TO AL
AL
SSYSF
BCRTF
TEST
128
129
59
G1
H2
J14
TI
TO
TO
AH
AH
AL
STATUS SIGNALS
Timer On - Channel A. When low, this pin indicates that the BCRTMP is transmitting data. This output remains active until the data transmission is complete or until the internal fail-safe timer times out (at 660µs), indicating that the transceiver should be disabled.
86 C11
TO
AL
ACTIVE 81 D13 TO AH Activity on 1553 Bus. When high, this pin indicates
that the BCRTMP has detected a valid command to any remote terminal address on the bus.
--
Standard Interrupt Level. This is a level interrupt. It is asserted when one or more events enabled in either the Standard Interrupt Enable Register, RT Descriptor, or BC Command Block occur. Resetting the Standard Interrupt bit in the High-Priority Interrupt Status/Reset Register clears the interrupt.
STDINTL
STDINTP
Standard Interrupt Pulse. STDINTP pulses when an interrupt is logged.
HPINT
High Priority Interrupt. The High-Priority Interrupt level is asserted upon occurance of events enabled in the High Priority Interrupt Enable Register. The corresponding bit(s) in the High-Priority Interrupt Status/Reset Register reset HPINT.
TIMRONA
TIMRONB
Timer On - Channel B. See TIMRONA description.
COMSTR
CHA/B
ChannelA/B. This indicates the active or last active channel.
TEST. This pin is used as a factory test pin. (Formerly MEMWIN.)
PIN NUMBER
F/P PGA
(RT) Command Strobe. The BCRTMP asserts this signal after receiving a valid command. The BCRTMP deactivates it after servicing the command.
Subsystem Fail. Upon receipt, this signal propagates directly to the RT 1553 status word and the BCRTMP Status Register.
BCRT Fail. this indicates a Built-In-Test (BIT) failure. In the RT mode, the Terminal Flag bit in 1553 status word is also set.
BCRTMP-10
NAME TYPE ACTIVE DESCRIPTION
BIPHASE INPUTS
RAO 50 P14 TI
Receive Channel A One. This is the Manchester-encoded true signal input from Channel A of the bus receiver.
RBO 54 N15 TI Receive Channel B One. This is the Manchester-encoded
true signal input from Channel B of the bus receiver.
RAZ
RBZ
51
55
N14
L14
TI
TI
Receive Channel A Zero. This is the Manchester-encoded complementary signal input from Channel A of the bus receiver.
Receive Channel B Zero. This is the Manchester-encoded complementary signal input from Channel B of the bus receiver.
--
--
--
--
PIN NUMBER
F/P PGA
NAME TYPE ACTIVE DESCRIPTION
TAO 52 M14 TO
TAZ 53 L13 TO
TBO 56 M15 TO
--
--
--
TBZ 57 K13 TO --
BIPHASE OUTPUTS
Transmit Channel A One. This is the Manchester­encoded true output to be connected to the Channel A bus transmitter input. This signal is idle low.
Transmit Channel A Zero. This is the Manchester­encoded complementary output to be connected to the Channel A bus transmitter input. This signal is idle low.
Transmit Channel B One. This is the Manchester­encoded true output to be connected to the Channel B bus transmitter input. This signal is idle low.
Transmit Channel B Zero. This is the Manchester­encoded complementary output to be connected to the Channel B bus transmitter input. This signal is idle low.
PIN NUMBER F/P PGA
BCRTMP-11
72 F14 ZL
73
78
75
F13
E13
D15
AL
AL
ZL
TTO
TI
TTO
TO
NAME TYPE ACTIVE DESCRIPTION
DMA SIGNALS
76 C15 TO AL
BURST 77 D14 TO AH
DMA Request. The BCRTMP issues this signal when access to RAM is required. It goes inactive after receiving a DMAG signal.
DMAR
DMAG
DMAGO
DMACK
TSCTL
DMA Grant Out. If DMAG is received but not needed, it passes through to this output.
DMA Acknowledge. The BCRTMP asserts this signal to confirm receipt of DMAG, it stays low until memory access is complete.
PIN NUMBER
F/P PGA
DMA Grant. This input to the BCRTMP allows the BCRMTP to access RAM. It is recognized 45ns before the rising edge of MCLKD2.
Three-State Control. This signal indicates when the BCRTMP is actually accessing memory. The host subsystem’s address and data lines must be in the high­impedance state when the signalis active. This signal assists in placing the external data and address buffers into the high­impedance state.
Burst (DMA Cycle). This indicates that the current DMA cycle transfers at least two words; worst-case is five words plus a “dummy” word.
BCRTMP-12
MODE SELECT INPUTS
NAME
PIN NUMBER
TYPE ACTIVE DESCRIPTION
F/P PGA
MD7 23 R4 TUI --
Mode 7. This input selects between two Remote Terminal Time Out (RTO) options. When this signal is high, the selected RTO is 16µs. When this signal is low, the selected RTO is 32µs.
MD6 22 P5 TUI --
Mode 6. This input selects whether mode codes with data are allowed in the selected 1553 protocol. When this signal is high, the protocol does allow mode codes with data. When this signal is low, the protocol does not allow mode codes with data.
MD5 21 R3 TUI --
Mode 5. This input selects the message error handling technique. When this signal is high, the message error handling technique is as defined in MIL-STD-1553B. When the signal is low, the message error handling technique is as defined in MACAIR A3818.
MD4 20 N5 TUI --
Mode 4. This input selects between MIL-STD-1553A and MIL-STD-1553B status word protocol. When this signal is high, the selected status word protocol is the “B” option. When this signal is low, the selected status word protocol is the “A” option.
MD3 19 P4 TUI --
Mode 3. This input selects between MIL-STD-1553A and MIL-STD-1553B mode code protocol. When this signal is high, the selected mode code protocol is the “B” option. When this signal is low, the selected mode code protocol is the “A” option.
MD2 18 P3 TUI --
Mode 2. This input selects between MIL-STD-1553A and MIL-STD-1553B RT Response Time protocol. When this signal is high, the selected response time protocol is the “B” option. This signal is low, the selected response time protocol is the “A” option.
MD1 17 P2 TUI --
Mode 1. This input selects whether broadcast is allowed. When this signal is high, broadcast is allowed. When this signal is low, broadcast is not allowed. When MD1 is low, RT address 11111 is treated like RT addresses 00000-11110.
MD0 16 N3 TUI --
Mode 0. This input selects the legalization method. When this signal is high, the DMA method of legalization is used. When this signal is low, the legalization bus is used.
BCRTMP-13
MODE OUTPUTS
NAME
PIN NUMBER
TYPE ACTIVE DESCRIPTION
F/P PGA
MD06 14 P1 TTO --
Mode 6 Out. This output signal reflects the internal state of Mode 6 (MD6).
MDO5 13 N2 TTO --
Mode 5 Out. This output signal reflects the internal state of Mode 5 (MD5).
MDO4 12 L3 TTO --
Mode 4 Out. This output signal reflects the internal state of Mode 4 (MD4).
MDO3 11 M2 TTO --
Mode 3 Out. This output signal reflects the internal state of Mode 3 (MD3).
MDO2 10 N1 TTO --
Mode 2 Out. This output signal reflects the internal state of Mode 2 (MD2).
MDO1 9 M1 TTO --
Mode 1 Out. This output signal reflects the internal state of Mode 1 (MD1).
MD00 8 L1 TTO --
Mode 0 Out. This output signal reflects the internal state of Mode 0 (MD0).
FORCED BUSY SIGNAL
NAME
PIN NUMBER
TYPE ACTIVE DESCRIPTION
F/P PGA
FBUSY 79 C14 TUI AL
Forced Busy. This signal places the RT in a mode where it will automatically respond to a command with the Busy bit set in the RT status word. No DMA memory bus accesses are necessary, and the memory buses remain in the high-impedance state until the busy mode is exited. If the RT is involved in a 1553 message transaction then entry into the busy state is held off until completion of the last DMS associated with that message. Upon entry into the busy state, the BCRTMP asserts the BUSYACK signal.
BUSYACK 80 N2 TTO --
Busy Acknowledge. This signal indicates that the BCRTMP has entered the Forced Busy state.
BCRTMP-14
WRAP-AROUND TEST SIGNALS
NAME
PIN NUMBER
TYPE ACTIVE DESCRIPTION
F/P PGA
WRAPEN
6 K2 TUI AL
Wrap-Around Enable. When this signal is low, thE continuous wrap-around feature is enabled.
WRAPF
5 J2 TO AH
Wrap Fail. When high, this pin indicates that the continuous wrap-around circuitry has detected a failure.
ALTWRAP
4 K1 TUI AL
Alternate Wrap-Around. This signal, when used in conjunction with WRAPEN, places the BCRTMP in a special system diagnostic mode, where the two 1553 buses are connected by a stub, and commands transmitted over one bus are received through the continuous wrap circuitry on the other bus. This permits off-line testing of both channels and the associated 1553 interface components.
LEGALIZATION BUS
NAME
PIN NUMBER
TYPE ACTIVE DESCRIPTION
F/P PGA
LGL10
121 E2 TTO --
Legalization bus bit 10. The Legalization bus bits 0­10 reflect bit times 19-9 of the current command (i.e., LGL10 = Current Command bit time 9 and LGL0 = Current Command bit time19. This bus is used to determine whether or not the command is legal. This bus can also be used to selectively determine if auto- execution of a particular mode code is allowed.
LGL9 120 C1 TTO --
Legalization bus bit 9
LGL8 119 E3 TTO --
Legalization bus bit 8
LGL7 118 D2 TTO --
Legalization bus bit 7
LGL6 117 C2 TTO --
Legalization bus bit 6
LGL5 116 B2 TTO --
Legalization bus bit 5
LGL4 115 C3 TTO --
Legalization bus bit 4. When the MACAIR A3818 method of error logging is selected, Legalization bus bits 4-0 reflect the word count for the defective data word.
LGL3
114 C4 TTO --
Legalization bus bit 3
LGL2
113 A2 TTO --
Legalization bus bit 2
LGL1
112 B3 TTO --
Legalization bus bit 1
LG10
111 C5 TTO --
Legalization bus bit 0
BCRTMP-15
NAME TYPE ACTIVE DESCRIPTION
CLK
MCLK
MCLKD2
3
58
74
J1
K14
E15
TI
TI
TO
Memory Clock Divided by Two. This signal is the Memory Clock input divided by two. It assists the host subsystem in synchronizing DMA events.
Clock. The 12MHz input clock requires a 50% ± 10% duty cycle with an accuracy of ± 0.01%. The accuracy is required in order to meet the Manchester encoding/decoding requirements of MIL-STD-1553.
Memory Clock. This is the input clock frequency the BCRTMP uses for memory accesses. The memory cycle time is equal to two MCLK cycles. Therefore, RAM access time is dependent upon the chosen MCLK frequency (6MHz minimum, 12MHz maximum). Please see the BCRTMP DMA timing diagrams in this data sheet.
--
--
--
CLOCK SIGNALS
PIN NUMBER F/P PGA
LEGALIZATION SIGNALS
NAME
PIN NUMBER
TYPE ACTIVE DESCRIPTION
F/P PGA
BRDCAST
122 D‘ TTO AH
Broadcast. When high, this pin indicates that the current command is a broadcast command.
MC
123 F3 TTO AH
Mode Code. When high, this pin indicates that the current command is a mode command.
LGLEN
127 F1 TTO AL
Legalization Bus Enable. When low, this pin enables the user-supplied legalization logic (if the Legalization bus is used).
LGLCMD 124 F2 TUI AH
Legal Command. A high on this input signal indicates to the BCRTMP that the current command is legal.
ERR 125 G2 TO AL
Error. When low, this pin indicates that a data word parity error or a Manchester error occurred in the current command. When this signal is asserted, the Legalization bus bits 4-0 contain the word count for the defective data word.
DOMC 126 G3 TUI AH
Do Mode Code. When high, this signal enables the automatic execution of mode codes. When low, this signal disables auto-execution.
BCRTMP-16
NAME TYPE ACTIVE DESCRIPTION
132
34 67
100
1
33 66
99
H3 N9
G13
C7
J3
N8
H13
C8
PWR PWR PWR PWR GND GND
GND GND
+5V +5V +5V +5V Ground Ground
Ground Ground
--
--
--
--
--
--
--
--
POWER AND
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
PIN NUMBER F/P PGA
BCRTMP-17
3.0 INTERNAL REGISTERS
The BCRTMP’s internal registers (see table 1 on pages 24-
25) enable the CPU to control the actions of the BCRTMP while maintaining low DMA overhead by the BCRTMP. All functions are active high and ignored when low unless stated
otherwise. Functions and parameters are used in both RT and BC modes except where indicated. Registers are addressed by the binary equivalent of their decimal number. For example, Register 1 is addressed as 0001B. Register usage is defined as follows:
#0 Control Register Bit
Number Description
BITs 15-13 Reserved. BIT 12 (BC,RT) MD7 (Mode 7). Remote Terminal Time-Out Option Select. When high, this bit selects a Remote
Terminal Time-Out that is nominally 32µs. When low, this bit selects a Remote Terminal Time-Out that is nominally 16µs.
BIT 11 Enable External Override. For use in multi-redundant systems. This bit enables the EXTOVR pin. BIT 10 BC/RT Select. This function selects between the Bus Controller and Remote Terminal operation modes. It
overrides the external BCRTSEL input setting if the Change Lock-Out function is not used. A reset operation must be performed when changing between BC and RT modes. This bit is write-only.
BIT 9 (BC) Retry on Alternate Bus. This bit enables an automatic retry to operate on alternate buses. For example, if
on bus A, with two automatic retries programmed, the automatic retries occur on bus B.
BIT 8 (RT) Channel B Enable. When set, this bit enables Channel B operation.
(BC) No significance.
BIT 7 (RT) Channel A Enable. When set, this bit enables Channel A operation.
(BC) Channel Select A/B. When set, this bit selects Channel A. BITs 6-5 (BC) Retry Count. These bits program the number (1-4) of retries to attempt. (00 = 1 retry, 11 = 4 retries) BIT 4 (BC) Retry on Bus Controller Message Error. This bit enables automatic retries on an error the bus controller
detects (see the Bus Controller Architecture section, page 36). BIT 3 (BC) Retry on Time-Out. This bit enables an automatic retry on a response time-Out condition. BIT 2 (BC) Retry on Message Error. This bit enables an automatic retry when the Message Error bit is set in the RT’s
status word response. BIT 1 (BC) Retry on Busy. This bit enables automatic retry on a received Busy bit in an RT status word response. BIT 0 Start Enable. In the BC mode, this bit starts/restarts Command Block execution. In the RT mode, it enables the
BCRTMP to receive a valid command. RT operation does not start until a valid command is received. When
using this function:
Restart the BCRTMP after each Master Reset or programmed reset.
This bit is not readable; verify operation by reading bit 0 of the BCRTMP’s Status Register.
BCRTMP-18
#1 Status Register (Read Only)
These bits indicate the BCRTMP’s current status.
Bit Number Description
BIT 15 TEST. This bit reflects the inverse of the TEST output. It changes state simultaneously with theTEST output. BIT 14 (RT) Remote Terminal Active. Indicates that the BCRTMP, in the Remote Terminal mode, is presently servicing
a command. This bit reflects the inverse of the COMSTR pin. BIT 13 (RT) Dynamic Bus Control Acceptance. This bit reflects the state of the Dynamic Bus Control Acceptance bit
in the RT status word (see Register 10 on page 20). BIT 12 (RT) Terminal Flag bit is set in RT status word. See also section 8.2.8.10. BIT 11 (RT) Service Request bit is set in RT status word. See also section 8.2.8.4. BIT 10 (RT) Busy bit is set in RT status word. See also section 8.2.8.7. BIT 9 BIT is in progress. BIT 8 Reset is in progress. This bit indicates that either a write to Register 12 has just occurred or the BCRTMP has
just received a Reset Remote Terminal (#01000) Mode Code. This bit remains set less than 1ms. BIT 7 BC/(RT) Mode. Indicates the current mode of operation. A reset operation must be performed when changing
between BC and RT modes. BIT 6 Channel A/B. Indicates either the channel presently in use or the last channel used. BIT 5 Subsystem Fail Indicator. Indicates receiving a subsystem fail signal from the host subsystem on the
SSYSF input. BITs 4-1 Reserved. BIT 0 (BC) Command Block Execution is in progress. (RT) Remote Terminal is in operation. This bit reflects bit 0 of
Register 0.
#2 Current Command Block Register (BC)/Remote Terminal Descriptor Space Address Register (RT)
(BC) This register contains the address of the head pointer of the Command Block being executed. Accessing a new Command Block updates it.
(RT) The host CPU initializes this register to indicate the starting location of the RT Descriptor Space. The host must allocate 320 sequential locations following this starting address. For proper operation, this location must start on an I x 512 decimal address boundary, where I is an integer multiple.
#3 Polling Compare Register
In the polling mode, the CPU sets the Polling Compare Register to indicate the RT response word on which the BCRTMP should interrupt. This register is 11 bits wide, corresponding to bit times 9 through 19 of the RT’s 1553 status word response. The sync, Remote Terminal Address, and parity bits are not included (see the section on Polling, page 38).
#4 BIT (Built-In-Test) Word Register
The BCRTMP uses the contents of this register when it responds to the Transmit BIT Word Mode Code (#10011). In addition, the BCRTMP writes to the two most significant bits of the BIT Word Register in response to either an Initiate Self-Test Mode Code (RT mode) or a write to Register 11 (BIT Start Command) to indicate a BIT failure. If the BIT Word needs to be modified, it can be read out, modified, then rewritten to this register. Note that if the processor writes a “1” to either bit 14 or 15 of this register, it effectively induces a BIT failure. Also note that during normal RT operation, bits 10 through 13 of this register indicate specific types of message errors, as shown below.
Bit Number Description
BIT 15 Channel B failure. BIT 14 Channel A failure. BIT 13 Word Count Error. BIT 12 Parity Error. BIT 11 Manchester Error. BIT 10 Remote Terminal Time-Out. BITs 9-0 BIT Word. The least significant ten bits of the BIT Word are user programmable.
BCRTMP-19
#5 Current Command Register (Read Only)
In the RT, this register contains the command currently being processed. When not processing a command, the BCRTMP stores the last command/status word transmitted on the 1553 bus in this register. This register is updated only when bit 0 of Register 0 is set. In the BC mode, this register contains the most current command sent out on the 1553 bus.
#6 Interrupt Log List Pointer Register
Initialized by the CPU, the Interrupt Log List Pointer Register indicates the start of the Interrupt Log List. After each list entry, the BCRTMP updates this register with the address of the next entry in the list. (See page 46-47.)
#7 High-Priority Interrupt Enable Register (Read/Write)
Setting the bits in this register causes a High-Priority Interrupt when the enabled event occurs. If enabled in Register 14, setting these bits also determines which events trigger the Stop Enable feature. To service the High-Priority Interrupt, the user reads Register 8 to determine the cause of the interrupt, then writes to Register 8 to clear the appropriate bits. The BCRTMP also provides a Standard Priority Interrupt Scheme that does not require host intervention. If High-Priority Interrupt service is not possible in a given application, it is advisable to use the Standard Priority features.
Bit Number Description
BITs 15-9 Reserved. BIT 8 Data Overrun Enable. When set, this bit enables an interrupt when DMAG was not received by the BCRTMP
within the allotted time needed for a successful data transfer to memory. BIT 7 (BC) Illogical Command Error Enable. This bit enables a High-Priority Interrupt to be asserted upon the
occurrence of an Illogical Command. Illogical commands include incorrectly formatted RT-RT Command
Blocks. BIT 6 (RT) Dynamic Bus Control Mode Code Interrupt Enable. When set, an interrupt is asserted when the Dynamic
Bus Control Mode Code is received, provided the T/R bit is “1,” the command is legal, and DOMC is active. BIT 5 Subsystem Fail Enable. When set, a High-Priority Interrupt is asserted after receiving a Subsystem Fail
(SSYSF) input pin. BIT 4 End of BIT Enable. This bit indicates the end of the internal BIT routine. BIT 3 BIT Word Fail Enable. This bit enables an interrupt indicating that the BCRTMP detected a BIT failure. BIT 2 (BC) End of Command Block List Enable (see Command Block Control Word, page 38.) This interrupt can be
superseded by other high-priority interrupts. BIT 1 Message Error Enable. If enabled, a High-Priority Interrupt is asserted at the occurrence of a message error. If a
High-Priority Interrupt condition occurs, as the result of an enabled message error, the device will halt operation
until the user clears the interrupt by writing a “1” to bit 1 of the High-Priority Interrupt Status/Reset Register
(Reg. #8). If this interrupt is not cleared, the BCRTMP remains in the HALTED state (appearing to be “locked
up”), even if it receives a valid message. This High-Priority Interrupt scheme is necessary in order to maintain the
BCRT MP’s state of operation so that the host CPU has this information available at the time of interrupt service. BIT 0 Standard Interrupt Enable. Setting this bit enables the STDINTL pin, but does not cause a high-priority
interrupt. If the user wants the Stop Enable feature activated for Standard Interrupts, this bit must be set. If low,
only the STDINTL pin is asserted when a Standard Interrupt occurs.
BCRTMP-20
#8 High-Priority Interrupt Status/Reset Register
When a High-Priority Interrupt is asserted, this register indicates the event that caused it. To clear the interrupt signal and reset the bit, write a “1” to the appropriate bit. See the corresponding bit definitions of Register 7, High-Priority Interrupt Enable Register.
Bit Number Description
BITs 15-9 Reserved. BIT 8 Data Overrun. BIT 7 Illogical Command. BIT 6 Dynamic Bus Control Accepted. BIT 5 Subsystem Fail. BIT 4 End of BIT. BIT 3 BIT Word Fail. BIT 2 End of Command Block. BIT 1 Message Error. BIT 0 Standard Interrupt. The BCRTMP sets this bit when any Standard Interrupt occurs, providing bit 0 of Register 7
is enabled.
#9 Standard Interrupt Enable Register
This register enables Standard Interrupt logging for any of the following enabled events (Standard Interrupt logging can also occur for events enabled in the BC Command Block or RT Subaddress/Mode Code Descriptor):
Bit Number Description
BITs 15-6 Reserved. BIT 5 (RT) Illegal Broadcast Command. When set, this bit enables an interrupt indicating that an Illegal Broadcast
Command has been received. BIT 4 (RT) Illegal Command. When set, this bit enables an interrupt indicating that an illegal command has been
received. BIT 3 (BC) Polling Comparison Match. This enables an interrupt indicating that a polling event has occurred. The user
must also set bit 12 in the BC Command Block Control Word for this interrupt to occur. BIT 2 (BC) Retry Fail. This bit enables an interrupt indicating that all the programmed number of retries have failed. BIT 1 (BC, RT) Message Error Event. This bit enables a standard interrupt for message errors. BIT 0 (BC) Command Block Interrupt and Continue. This bit enables an interrupt indicating that a Command Block,
with the Interrupt and Continue Function enabled, has been executed.
BCRTMP-21
#10 Remote Terminal Address Register
This register sets the Remote Terminal Address via software. The Change Lock-Out Enable feature, when set, prevents the Remote Terminal Address or the BCRTMP Mode Selection from changing. Note that MD4 also controls the effect of BITs 9-15 on status word generation. See section 8.2.8.
Bit Number Description
BIT 15 (RT) Instrumentation. Setting this bit sets the RT status word Instrumentation bit. BIT 14 (RT) Busy. Setting this bit sets the RT status word Busy bit. It does not inhibit data transfers to the subsystem. BIT 13 (RT) Subsystem Fail. Setting this bit sets the RT status word Subsystem Flag bit. In the RT mode, the Subsystem
Fail is also logged into the Message Status Word. BIT 12 (RT) Dynamic Bus Control Acceptance. Setting this bit sets the RT status word Dynamic Bus Control
Acceptance bit when the BCRTMP receives the Dynamic Bus Control Mode Code from the currently active Bus
Controller. Host intervention is required for the BCRTMP to take over as the active Bus Controller. BIT 11 (RT) Terminal Flag. Setting this bit sets the RT status word Terminal Flag bit; the Terminal Flag bit in the RT
status word is also internally set if the BIT fails. BIT 10 (RT) Service Request. Setting this bit sets the RT status word Service Request bit. BIT 9 (RT) Busy Mode Enable. Setting this bit sets the RT status word Busy bit and inhibits all data transfers to the
subsystem. (See Forced Busy Mode, section 8.2.4.) BIT 8 BC/RT Mode Select. This bit’s state reflects the external pin BCRTSEL. It does not necessarily reflect the state
of the chip, since the BC/RT Mode Select is software-programmable via bit 10 of Register 0. This bit is
read-only. BIT 7 Change Lock-Out. This bit’s state reflects the external pin LOCK. When set, this bit indicates that changes to the
RT address or the BC/RT Mode Select are not allowed using internal registers. This bit is read-only. BIT 6 Remote Terminal Address Parity Error. This bit indicates a Remote Terminal Address Parity error. It appears
after the Remote Terminal Address is latched if a parity error exists. BIT 5 Remote Terminal Address Parity. This is an odd parity input bit used with the Remote Terminal Address. It
ensures accurate recognition of the Remote Terminal Address. BITs 4-0 Remote Terminal Address (Bit 0 is the LSB). This reflects the RTA4-0 inputs at Master Reset. Modify the
Remote Terminal Address by writing to these bits.
#11 BIT Start Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location initiates the internal BIT routine, which lasts 100µs. Verify using the BIT-in-Progress bit in the Status Register. If the BCRTMP is online (Bit 0 of Register 1 is high), a programmed reset (write to Register 12) must precede a write to this register to initiate the internal BIT.
The BCRTMP’s self-test performs an internal wrap-around test between its Manchester encoder and its two Manchester decoders. If the BCRTMP detects a failure on either the primary or the secondary channel, it flags this failure by setting bit 14 of Register 4 (BIT Word Register) for Channel A and/or bit 15 for Channel B. When in the Remote Terminal mode, while the BCRTMP is performing its self-test, it ignores any commands on the 1553 bus until it has completed the self-test.
#12 Programmed Reset Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location initiates a reset sequence of the encoder/decoder and protocol sections of the BCRTMP which lasts less than 1µs. This is identical to the reset used for the Reset Remote Terminal Mode Code except that command processing halts. For a total reset (i.e., including registers), see the MRST signal description.
#13 RT Timer Reset Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location resets the RT Time Tag timer to zero. The BCRTMP’s Remote Terminal Timer time-tags message transactions. The time tag is generated from a free-running eight-bit timer of 64µs resolution. This timer can be reset to zero simply by writing to Register 13. When the timer is reset, it immediately starts running.
BCRTMP-22
#14 Activity Status/Operational Mode Register Bit
Number Description
BITs 15-14 Reserved. BIT 13 Ignore T/R bit in Mode Command. When high, this bit causes the BCRTMP to ignore the value of the T/R bit in
1553 Mode Commands 0-15 (mode codes without data) and prevents automatic execution of modes 18-19. This
feature is used in conjunction with Operational Mode 6 (input pin MD6). BIT 12 Stop Enable. When the BCRTMP is in the RT mode, this bit enables a feature that places the BCRTMP into the
Forced Busy Mode when an interrupt (either Standard or High-Priority) occurs. When the BCRTMP enters the
Forced Busy Mode, the device responds with the Busy bitset in the 1553 status word any time a valid 1553
command is received. When the interrupt iscleared, the BCRTMP exits the Forced Busy Mode.
For BC operation, setting the Stop Enable bit causes the BCRTMP to halt Command Block execution when an
enabled interrupt (either Standard or High-Priority) occurs. Command Block execution resumes when the user
clears the interrupt by writing a “1” to the appropriate bit in Register 8. BIT 11 Bus B Active. This bit goes high when the BCRTMP, acting as a Remote Terminal, receives a valid 1553 command
on the secondary bus. BIT 10 Bus A Active. This bit goes high when the BCRTMP, acting as a Remote Terminal, receives a valid 1553 command
on the primary bus. BIT 9 WRAPF Wrap-Around Test Fail. This bit reflects the state of the WRAPF output signal. BIT 8 ALTWRAP Alternate Channel Wrap-Around Test Enable. After Master Reset, this bit reflects the complement of
the state of the ALTWRAP input signal. This bit can be software-modified if the LOCK pin is low. Thus, to enable
the ALTWRAP feature, write a one to this bit location. BIT 7 WRAPEN Wrap-Around Test Enable. After Master Reset, this bit reflects the complement of the state of the
WRAPEN input signal. This bit can be software-modified if the LOCK pin is low. Thus, to enable the WRAPEN
feature, write a one to this bit location. BIT 6 MD6 Operational Mode 6. After Master Reset, this bit reflects the state of the corresponding input pin (MD6).
See section 8.1.7 for a summary of Operational Mode 6. This bit can be software-modified if the LOCK pin is low. BIT 5 MD5 Operational Mode 5. After Master Reset, this bit reflects the state of the corresponding input pin (MD5).
See section 8.1.6 for a summary of Operational Mode 5. This bit canbe software-modified if the LOCK pin
is low. BIT 4 MD4 Operational Mode 4. After Master Reset, this bit reflects the state of the corresponding input pin (MD4).
See section 8.1.5 for a summary of Operational Mode 4. This bit canbe software-modified if the LOCK pin
is low. BIT 3 MD3 Operational Mode 3. After Master Reset, this bit reflects the state of the corresponding input pin (MD3).
See section 8.1.4 for a summary of Operational Mode 3. This bit canbe software-modified if the LOCK pin
is low. BIT 2 MD2 Operational Mode 2. After Master Reset, this bit reflects the state of the corresponding input pin (MD2).
See section 8.1.3 for a summary of Operational Mode 2. This bit can be software-modified if the LOCK pin is low. BIT 1 MD1 Operational Mode 1. After Master Reset, this bit reflects the state of the corresponding input pin (MD1).
See section 8.1.2 for a summary of Operational Mode . This bit can be software-modified if the LOCK pin is low. BIT 0 MD0 Operational Mode 0. After Master Reset, this bit reflects the state of the corresponding input pin (MD0).
See section 8.1.1 for a summary of Operational Mode 0. This bit canbe software-modified if the LOCK pin
is low.
BCRTMP-23
#15 Programmable Status/Last Status Word Register (RT)
This register provides control of and access to the RT Status Word. Bits 15-12 (read/write) allow for special operations on some or all of the Status Word bits. Writing to bit 11 places the BCRTMP into the Forced Busy mode. Reading this bit will verify that the BCRTMP has entered the Forced Busy mode (see section 8.2.4). Writing to the remaining bits (bits 10-0) of this register allows control of the RT Status Word (see section 8.2.8). When reading from this register, bits 10-0 indicate the last Status Word sent by the BCRTMP.
Bit Number Description
BIT 15 Immediate Clear Mode Enable. When set, this bit will cause the BCRTMP to automatically clear all programmable
status bits (bits 10-0 of this register and bits 15-9 of Register 10) after the BCRTMP transmits the RT Status Word.
When this bit is set, the first Status Word sent outcontains the Status Word created from the programmable status
bits in this register, Register 10, and from internally generated conditions (see section 8.2.8). After Status Word
transmission, the BCRTMP clears bits 10-0 of this register and bits 15-9 of Register 10. There is one exception to
this automatic status bit clearing. When the next command received is the Transmit Status Word or Transmit Last
Command mode code, the BCRTMP will respond with the appropriate Status Word from the previous valid
command. This feature applies to all operational modes. Note that inhibition of the Terminal Flag bit (receipt of
Mode Code 6) is also cleared by this bit. BIT 14 Automatic Terminal Flag Bit Enable, Option 1. When set, this bit will cause the Terminal Flag to be automatically
set when any of the Status Word field bits are set (Status Word bit times 9 through 18). BIT 13 Automatic Terminal Flag Bit Enable, Option 2. When set, this bit will cause the Terminal Flag to be automatically
set when the Busy or Subsystem Flag Status Word bits are set. If both bits 14 and 13 of this register are set,
neither option is selected, and the Busy bit will not be set by the Forced Busy mode. These automatic Terminal
Flag bit options apply for all operational modes. BIT 12 Automatic Data Ready. This bit, when set, causes the BCRTMP to place the complement of the Busy Bit in the
Data Ready Bit (bit 8). Therefore, when the BCRTMP transmits the Status Word, bit 8 = NOT bit 3. BIT 11 Forced Busy. BIT 10 ME Message Error (Bit Time 9)/Last Status Word Message Error Bit. BIT 9 PSBT10 Programmable Status Bit Time 10/Last Status Word Bit Time 10. BIT 8 PSBT11 Programmable Status Bit Time 11/Last Status Word Bit Time 11. BIT 7 PSBT12 Programmable Status Bit Time 12/Last Status Word Bit Time 12. BIT 6 PSBT13 Programmable Status Bit Time 13/Last Status Word Bit Time 13. BIT 5 PSBT14 Programmable Status Bit Time 14/Last Status Word Bit Time 14. BIT 4 PSBT15 Programmable Status Bit Time 15/Last Status Word Bit Time 15. BIT 3 PSBT16 Programmable Status Bit Time 16/Last Status Word Bit Time 16. BIT 2 PSBT17 Programmable Status Bit Time 17/Last Status Word Bit Time 17. BIT 1 PSBT18 Programmable Status Bit Time 18/Last Status Word Bit Time 18. BIT 0 TF Terminal Flag (Bit Time 19)/Last Status Word Terminal Flag Bit.
BCRTMP-24
7 6 5 4 3 2 1 0
89101112131415
7 6 5 4 3 2 1 0
89101112131415
7 6 5 4 3 2 1 0
89101112131415
7 6 5 4 3 2 1 0
89101112131415
#0
RTYTO
UNUSEDUNUSEDUNUSEDUNUSED
RTOUNUSEDUNUSEDUNUSED
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
(BC) CURRENT COMMAND BLOCK REGISTER
TEST RTACT DYNBUS RT FLAG SRQ BUSY BIT RESET
BC/RT BUSA/B SSFAIL CMBKPG
BC/RT STATUS REGISTER
EXTOVR BC/RT RTYALTB BUSBEN
BUSAEN
CHNSEL
RTYCNT RTYBCME RTYME RTYBSY STEN
BC/RT CONTROL REGISTER
#3
#2
#1
7 6 5 4 3 2 1 0
89101112131415
(RT) REMOTE TERMINAL DESCRIPTOR SPACE ADDRESS REGISTER
POLLING COMPARE REGISTER
TFSWBT18SWBT17SWBT16SWBT15 SWBT14SWBT13SWBT12
SWBT11SWBT10MSGERRXXXXX
D7 D6 D5 D4 D3 D2 D1 D0
CURRENT COMMAND REGISTER
RTTO D9 D8
#4#5BIT WORD REGISTER
CHBFAIL CHAFAIL WCERR PARERR MANERR
7 6 5 4 3 2 1 0
89101112131415
D7 D6 D5 D4 D3 D2 D1 D0
D10 D9 D8D15 D14 D13 D12 D11
UNUSEDUNUSEDUNUSEDUNUSEDUNUSEDUNUSED
#7
#6 INTERRUPT LOG LIST POINTER REGISTER
A0A1A2A3A4A5A6A7
A8A9A10A11A12A13A14A15
BCRTMP HIGH-PRIORITYINTERRUPT ENABLE REGISTER
STDINTMSGERREOLBITFAILENDBITSSFAILDYNBUSILLCMD
DATOVRUNUSED
7 6 5 4 3 2 1 0
89101112131415
7 6 5 4 3 2 1 0
89101112131415
Table 1. BCRTMP Registers
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