UTMC 5962-0323602VXX, 5962-0323602VXC, 5962-0323602VXA, 5962-0323602QXX, 5962-0323602QXC, 5962-0323602QXA, 5962-0323601VXC, 5962-0323601VXA, 5962-0323601QXX, 5962-0323601QXC, 5962-0323601QXA, UT8R128K32-15WWX, UT8R128K32-15WWC, UT8R128K32-15WPC, UT8R128K32-15WCC, UT8R128K32-15WCA Datasheet

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DQ(15) to DQ(0)
DQ(31) to DQ(16)
G
IN
LHWE
W
E1
E2
HHWE
- QML compliant part
q
q
- 68-lead ceramic quad flatpack
Packaging options:
- Latchup >1.0E11 rad(Si)/sec
- Upset 1.0E9 rad(Si)/sec
- Dose Rate (estimated)
- Neutron Fluence: 3.0E14n/cm2
q
- Total-dose: 100K rad(Si)
Radiation performance
- I/O Voltage 3.3 volts, 1.8 volt core
15ns maximum access time
q q
FEATURES
Standard Products
UT8R128K32 128K x 32 SRAM
Advanced Data Sheet

May 29, 2003

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTRODUCTION

Asynchronous operation, functionally compatible with

 

The UT8R128K32 is a high-performance CMOS static RAM

 

organized as 131,072 words by 32 bits. Easy memory expansion

industry-standard 128K x 32 SRAMs

 

 

 

 

 

 

is provided by active LOW and HIGH chip enables ( E1, E2), an

q CMOS compatible inputs and output levels, three-state

 

 

active LOW output enable (G), and three-state drivers. This

bidirectional data bus

 

 

 

 

 

 

device has a power-down feature that reduces power

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

consumption by more than 90% when deselected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Writing to the device is accomplished by taking chip enable one

- SEL Immune >100 MeV-cm2 /mg

 

 

 

(E1) input LOW, chip enable two (E2) HIGH and write enable

 

 

 

(W) input LOW. Data on the 32 I/O pins (DQ0 through DQ31)

- Onset LET > TBD

 

 

 

is then written into the location specified on the address pins

- Memory Cell Saturated Cross Section: TBD

 

 

(A0 through A16). Reading from the device is accomplished by

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

taking chip enable one (E1) and output enable (G) LOW while

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

forcing write enable (W) and chip enable two (E2) HIGH. Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

these conditions, the contents of the memory location specified

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

by the address pins will appear on the I/O pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The 32 input/output pins (DQ0 through DQ31) are placed in a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

Standard Microcircuit Drawing 5962-03236

 

 

 

high impedance state when the device is deselected (E1 HIGH

 

 

 

or E2 LOW), the outputs are disabled (G HIGH), or during a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

write operation (E1 LOW, E2 HIGH and W LOW).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pre-Charge Circuit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A2

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3

 

 

Memory Array

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

256K x 16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A4

 

 

Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

 

E

A6

 

 

Row

 

 

I/O Circuit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Column Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low Byte

Data Control

 

Read Circuit

 

 

 

 

Data Control

 

 

A10 A11

A12 A13A14 A15 A16

High Byte

Read Circuit

Figure 1. UT8R128K32 SRAM Block Diagram

1

DEVICE OPERATION

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VSS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

V

 

A0

A1

A2

A3

A4

A5

HHWE

 

V

LHWE

W

A6

A7

A8

A9

A10

V

 

 

 

SS

 

 

 

 

 

 

 

 

 

SS

 

 

 

 

 

 

 

DD1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

51

DQ16

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50

DQ17

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

49

DQ18

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

48

DQ19

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Top View

 

 

 

 

 

 

47

DQ20

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

46

DQ21

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

45

DQ22

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

44

DQ23

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

43

VSS

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

42

DQ24

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

41

DQ25

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

40

DQ26

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

39

DQ27

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

38

DQ28

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

37

DQ29

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

DQ30

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

35

DQ31

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DD1

A11

A12

A13

A14

A15

A16

E1

G

E2

DD2

SS

NC

NC

NC

DD2

SS

 

 

 

 

 

 

V

V

V

V

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The UT8R128K32 has six control inputs called Enable 1 (E1), Enable 2 (E2), Write Enable (W), Half-word Enables (HHWE/ LHWE) and Output Enable ( G); 17 address inputs, A(16:0); and 32 bidirectional data lines, DQ(15:0). E1 and E2 device enables control device selection, active, and standby modes. Asserting E1 and E2 enables the device, causes IDD to rise to its active value, and decodes the 17 address inputs to select one of 131,072 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

G

W

E2

E1

LHWE

HHWE

I/O Mode

Mode

X

X

X

H

X

X

DQ(31:16)

Standby

 

 

 

 

 

 

3-State

 

 

 

 

 

 

 

DQ(15:0)

 

 

 

 

 

 

 

3-State

 

X X

L

X

X

X

DQ(31:16) Standby

 

Figure 2. 15ns SRAM Pinout (68)

 

 

 

 

 

 

 

 

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

 

H

 

L

N

H

 

 

 

 

 

 

 

 

 

 

 

 

L

 

PIN NAMES

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

H

 

H

 

L

 

H

 

L

A(16:0)

Address

 

W

 

 

Write Enable

 

 

 

M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ(31:0)

Data Input/Output

 

G

 

 

Output Enable

 

L

H

 

H

 

L

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

E1

Enable (Active Low)

 

VDD1

 

 

Power (1.8V)

O

 

 

 

 

 

 

 

 

 

E2

Enable (Active High)

 

VDD2

 

 

Power (3.3V)

 

 

 

 

 

 

 

 

 

 

 

 

 

P

H

 

L

 

L

 

L

 

 

 

 

 

 

 

L

 

X

L

 

 

 

 

HHWE

High half-word enable

VS S

 

 

Ground

 

 

 

 

 

 

 

 

 

 

 

LWHE

Low half-word enable

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

L

 

H

 

L

 

L

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

 

 

X

L

 

H

 

L

 

H

 

L

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

D

 

 

 

 

 

H

H

 

H

 

L

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

X

 

H

 

L

 

H

 

H

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

3-State

 

DQ(15:0)

 

3-State

 

DQ(31:16)

Low Half-Word

3-State

Read

DQ(15:0)

 

Data Out

 

DQ(31:16)

High Half-Word

Data Out

Read

DQ(15:0)

 

3-State

 

DQ(31:16)

Word Read

Data Out

 

DQ(15:0)

 

Data Out

 

DQ(31:16)

Word Write

Data In

 

DQ(15:0)

 

Data In

 

DQ(31:16)

Low Half-Word

3-State

Write

DQ(15:0)

 

Data In

 

DQ(31:16)

High Half-Word

Data In

Write

DQ(15:0)

 

3-State

 

DQ(31:16)

3-State

DQ(15:0)

 

All 3-State

 

DQ(31:16)

3-State

DQ(15:0)

 

All 3-State

 

2

READ CYCLE

 

 

 

high-impedance state by G, the user must wait tWLQZ before

A combination of W and E2 greater than VIH (min) and E1

 

applying data to the sixteen bidirectional pins DQ(31:0) to

 

avoid bus contention.

 

 

 

less than VIL (max) defines a read cycle. Read access time is

 

WORD ENABLES

 

 

 

measured from the latter of device enable, output enable, or

 

 

 

 

valid address to valid data output.

 

 

Separate byte enable controls (LHWE and HHWE) allow

 

 

 

 

SRAM Read Cycle 1, the Address Access in Figure 3a, is

 

individual bytes to be accessed. LHWE controls the lower

initiated by a change in address inputs while the chip is

 

bits DQ(15:0). HHWE controls the upper bits DQ(31:16).

enabled with G asserted andW deasserted. Valid data appears

Writing to the device is performed by asserting E1, E2 and

on data outputs DQ(31:0) after the specified tAVQV is

 

the byte enables. Reading the device is performed by

satisfied. Outputs remain active throughout the entire cycle.

 

asserting E1, E2, G, and the byte enables while W is held

As long as device enable and output enable are active, the

 

inactive (HIGH).

 

 

 

 

address inputs may change at a rate equal to the minimum

 

 

 

 

 

 

 

 

 

 

 

 

read cycle time (tAVAV ).

 

 

 

 

 

HHWE

 

LHWE

 

OPERATION

SRAM Read Cycle 2, the Chip Enable-controlled Access in

 

 

 

0

 

0

 

32-bit read or write cycle

Figure 3b, is initiated by the latter of E1 and E2 going active

 

 

 

0

 

1

 

16-bit high half-word read or write

while G remains asserted, W remains deasserted, and the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cycle (low byte bi-direction pins

addresses remain stable for the entire cycle. After the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ(15:0) are in 3 -state)

specified tETQV is satisfied, the 32-bit word addressed by

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A(16:0) is accessed and appears at the data outputs DQ(31:0).

 

 

1

 

0

 

32-bit low half-word read or write

 

 

 

 

 

 

 

 

 

 

 

 

cycle (high half word bi-direction

SRAM Read Cycle 3, the Output Enable-controlled Access

 

 

 

 

 

 

 

 

 

pins DQ(31:16)T are in 3 -state)

in Figure 3c, is initiated by G going active while E1 and E2

 

 

 

1

 

1

 

High and Low byte bi-directional

are asserted, W is deasserted, and the addresses are stable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

Read access time is tGLQV unless tAVQV or tETQV have not

 

 

 

 

 

 

 

 

 

pins remain in 3-state, write function

 

 

 

 

 

 

 

 

 

disabled

 

 

 

 

 

 

 

 

 

 

 

 

been satisfied.

 

 

 

 

 

 

 

 

 

 

E

Write Cycle

 

 

 

RADIATION HARDNESS

 

 

 

 

 

 

 

M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A combination of W and E1 less than VIL(max) and E2

 

The UT8R128K32 SRAM incorporates special design,

 

layout, and process features which allows operation in a

greater than VIH(min) defines a write cycle. The state ofG is

 

 

 

 

P

 

 

 

 

 

 

 

limited radiation environment.

a “don’t care” for a write cycle. The outputs are placed in the

OTable 2. Radiation Hardness Design Specifications1

high-impedance state when eitherG is greater than VIH(min),

L

 

 

 

 

 

 

 

 

 

 

 

or when W is less than VIL(max).

 

 

Total Dose

 

 

100K

 

rad(Si)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle 1, the Write Enable-controlled Access in Figure

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

Heavy Ion

 

 

TBD

 

Errors/Bit-Day

 

4a, is defined by a write terminated by W going high, with

 

 

 

 

 

 

 

 

Error Rate2

 

 

 

 

 

 

E1 and E2 still active. The write pulse width is defined by

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

tWLWH when the write is initiated by W, and by tETWH when

 

Notes:

 

 

 

 

 

 

 

 

the write is initiated by E1 or E2. Unless theEoutputs have

 

1. The SRAM is immune to latchup to particles of 128MeV-cm2/mg.

been previously placed in the high-impedance state byG, the

 

2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils

 

 

 

of Aluminum.

 

 

 

 

 

 

user must wait user must wait t

 

before applying data to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WLQZD

 

Supply Sequencing

 

 

 

the 32 bidirectional pins DQ(15:0) to avoid bus contention.

 

 

 

 

Write Cycle 2, the Chip EnableN-controlled Access in Figure

 

No supply voltage sequencing is required between V DD1 and

 

V

 

.

 

 

 

 

 

 

 

I

 

 

 

DD2

 

 

 

 

 

 

 

4b, is defined by a write terminated by the latter of E1 or E2

 

 

 

 

 

 

 

 

 

 

 

going inactive. The write pulse width is defined by tWLEF

when the write is initiated byW, and by tETEF when the write is initiated by either E1or E2 going active. For the W initiated write, unless the outputs have been previously placed in the

3

ABSOLUTE MAXIMUM RATINGS1

(Referenced to VSS)

SYMBOL

PARAMETER

LIMITS

VDD1

DC supply voltage

-0.3 to 2.0V

VDD2

DC supply voltage

-0.3 to 3.8V

VI/O

Voltage on any pin

-0.3 to 3.8V

TSTG

Storage temperature

-65 to +150°C

PD

Maximum power dissipation

1.2W

TJ

Maximum junction temperature

+150°C

ΘJC

Thermal resistance, junction-to-case2

5°C/W

II

DC input current

±5 mA

Notes:

1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended.TExposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.

2.Test per MIL-STD-883, Method 1012. NE

SYMBOL

PARAMETER

 

M

LIMITS

VDD1

Positive supply voltage

 

1.7 to 1.9V

P

 

VDD2

Positive supply voltage

 

3.0 to 3.6V

 

 

 

TC

 

O

 

 

 

Case temperature range

 

 

(C) Screening: -55 to +125°C

 

L

 

 

(W) Screening: -40 to +125°C

VIN

 

 

 

0V to VDD2

DC input voltage

 

 

 

 

 

E

 

 

 

 

 

 

V

 

 

 

 

 

 

E

 

 

 

 

 

N

D

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

4

UTMC 5962-0323602VXX, 5962-0323602VXC, 5962-0323602VXA, 5962-0323602QXX, 5962-0323602QXC, 5962-0323602QXA, 5962-0323601VXC, 5962-0323601VXA, 5962-0323601QXX, 5962-0323601QXC, 5962-0323601QXA, UT8R128K32-15WWX, UT8R128K32-15WWC, UT8R128K32-15WPC, UT8R128K32-15WCC, UT8R128K32-15WCA Datasheet

DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*

(-55°C to +125°C for (C) screening and -40°C to +125°C for (W) screening)

SYMBOL

PARAMETER

 

 

CONDITION

 

 

MIN

 

VIH

High-level input voltage

 

 

 

 

 

 

 

.7*VDD2

 

VIL

Low-level input voltage

 

 

 

 

 

 

 

 

 

VOL

Low-level output voltage

 

IOL = 8mA,V DD2 =VDD2 (min)

 

 

VOH

High-level output voltage

 

IOH = -4mA,VDD2 =VDD2 (min)

 

.8*VDD2

 

1

Input capacitance

 

 

¦ = 1MHz @ 0V

 

 

 

 

 

CIN

 

 

 

 

 

 

 

 

 

 

 

CIO

Bidirectional I/O capacitance

 

¦ = 1MHz @ 0V

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

IIN

Input leakage current

 

 

VIN = VDD2 and VSS

 

 

 

-2

 

IOZ

Three-state output leakage current

VO = VDD2 and V SS

 

 

 

-2

 

 

 

 

 

 

VDD2 = VDD2 (max), G = VDD2 (max)

 

I

2, 3

Short-circuit output current

 

VDD2 = VDD2 (max), V O = VDD2

 

-100

OS

 

 

 

 

VDD2 = VDD2 (max), V O = VSS

 

T

 

 

 

 

 

 

 

 

 

 

 

 

N

 

IDD1(OP1 )

VDD1 Supply current operating

 

Inputs : VIL

= VSS + 0.2V,

 

 

 

 

 

E

 

 

 

@ 1MHz

 

 

 

VIH = VDD2 -0.2V , IOUT = 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M

 

 

 

 

 

 

 

 

VDD1 =VDD1 (max), V DD2

= VDD2

(max)

 

IDD1(OP2 )

VDD1 Supply current operating

 

Inputs : VIL

= VSS

+ 0.2V,

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

@ 66MHz,

 

 

 

VIH = VDD2 -0.2V, IOUT = 0

 

 

 

 

 

 

 

 

 

 

O

 

= VDD2

 

 

 

 

 

 

 

 

VDD1 =VDD1 (max), V DD2

(max)

 

IDD2(OP1 )

VDD2 Supply current operating

 

Inputs : VIL

= VSS + 0.2V,

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

@ 1MHz

 

 

 

VIH = VDD2

-0.2V , IOUT = 0

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

VDD1 =VDD1 (max), V DD2 = VDD2

(max)

 

IDD2(OP2 )

VDD2 Supply current operating

V

= VSS + 0.2V,

 

 

 

 

 

Inputs : VIL

 

 

 

 

 

 

@ 66MHz,

 

 

 

VIH = VDD2 -0.2V, IOUT = 0

 

 

 

 

 

Supply current standby @ E0Hz

VDD1 =VDD1 (max), V DD2 = VDD2 (max)

 

IDD1(SB)4

CMOS inputs , IOUT = 0

 

 

 

 

 

 

 

 

D

 

E1 = VDD2 -0.2, E2 = GND

 

 

 

IDD2(SB)4

 

 

 

VDD1 =VDD1 (max), V DD2 = VDD2 (max)

 

I

(SB)4

Supply current standby A(16:0)

 

CMOS inputs , IOUT = 0

 

 

 

 

DD1

@ 66MHz

N

 

 

E1 = VDD2 - 0.2, E2 = GND,

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

IDD2(SB)4

 

 

 

 

VDD1 =VDD1 (max), V DD2 = VDD2 (max)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1.0E5 rad(Si).

1.Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2.Supplied as a design limit but not guaranteed or tested.

3.Not more than one output may be shorted at a time for maximum duration of one second.

4.VIH = VDD2 (max), VIL = 0V.

MAX

UNIT

 

V

.3*VDD2

V

.2*VDD2

V

 

V

7

pF

7

pF

2

mA

2

mA

+100

mA

15

mA

85

mA

1

mA

12

mA

11

mA

100

mA

11

mA

100

mA

 

 

5

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