UTMC 5962P0153301TXC, 5962P0153301QXC, 5962L0153301TXC, 5962-0153301TXC, 5962-0153301QXC, UT8Q512K32-SPC, UT8Q512K32-SWC Datasheet

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Standard Products

QCOTSTM UT8Q512K32 16Megabit SRAM MCM

Data Sheet

June, 2003

FEATURES

q25ns maximum (3.3 volt supply) address access time

qMCM contains four (4) 512K x 8 industry-standard asynchronous SRAMs; the control architecture allows operation as 8, 16, 24, or 32-bit data width

qTTL compatible inputs and output levels, three-state bidirectional data bus

qTypical radiation performance

-Total dose: 50krads

-SEL Immune >80 MeV-cm2 /mg

-LETTH(0.25) = >10 MeV-cm2/mg

-Saturated Cross Section cm2 per bit, 5.0E-9

-<1E-8 errors/bit-day, Adams 90% geosynchronous heavy ion

qPackaging options:

-68-lead dual cavity ceramic quad flatpack (CQFP) - (weight 7.37 grams)

qStandard Microcircuit Drawing 5962-01533

-QML T and Q compliant part

INTRODUCTION

The QCOTST M UT8Q512K32 Quantified Commercial Off-the-Shelf product is a high-performance 2M byte (16Mbit) CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 x 8 bit SRAMs with a common output enable. Memory expansion is provided by an active LOW chip enable (En), an active LOW output enable (G), and three-state drivers. This device has a powerdown feature that reduces power consumption by more than 90% when deselected.

Writing to each memory is accomplished by taking the chip enable (En) input LOW and write enable ( Wn) inputs LOW. Data on the I/O pins is then written into the location specified on the address pins (A0 through A18 ). Reading from the device is accomplished by taking the chip enable (En) and output enable (G) LOW while forcing write enable (Wn) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The input/output pins are placed in a high impedance state when the device is deselected (En HIGH), the outputs are disabled (G HIGH), or during a write operation (En LOW and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by making Wn along with En a common input to any combination of the discrete memory die.

W3

W2

W1

W0

E3

E2

E1

E0

A(18:0)

G

512K x 8

 

512K x 8

 

512K x 8

 

512K x 8

 

 

 

 

 

 

 

DQ(31:24)

DQ(23:16)

DQ(15:3)

DQ(7:0)

or

or

or

or

DQ3(7:0)

DQ2(7:0)

DQ1(7:0)

DQ0(7:0)

Figure 1. UT8Q512K32 SRAM Block Diagram

 

NC

 

A0

A1

A2

A3

A4

A5

E2

 

SS

E3

 

W0

 

A6

A7

A8

A9

A10

DD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ0(0)

10

9

8

7

6

5

4

3

2

 

1

68 67 66 65 64 63 62 61

 

DQ0(2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

DQ1(0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ1(2)

DQ2(0)

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

59

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ2(2)

DQ3(0)

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

58

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ3(2)

DQ4(0)

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

57

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ4(2)

DQ5(0)

14

 

 

 

 

 

 

 

 

Top View

 

 

 

 

 

 

56

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ5(2)

DQ6(0)

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

55

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

54

DQ6(2)

DQ7(0)

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

53

DQ7(2)

VSS

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

52

V

DQ0(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SS

DQ1(1)

19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

51

DQ0(3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ1(3)

DQ2(1)

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50

DQ2(3)

DQ3(1)

21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

49

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ3(3)

DQ4(1)

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

48

DQ4(3)

DQ5(1)

23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

47

DQ5(3)

DQ6(1)

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

46

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ6(3)

DQ7(1)

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

45

DQ7(3)

 

26

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

 

 

 

DD

A11

A12

A13

A14

A15

A16

E0

G

E1

A17

 

 

W1

W2

W3

A18

NC

NC

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2. 25ns SRAM Pinout (68)

PIN NAMES

 

 

 

 

 

A(18:0)

 

Address

 

Wn

 

WriteEnable

 

 

 

 

 

DQ(7:0)

 

Data Input/Output

 

G

 

Output Enable

 

En

 

Device Enable

 

VDD

 

Power

 

 

 

 

 

VSS

 

Ground

DEVICE OPERATION

Each die in the UT8Q512K32 has three control inputs called Enable (En), Write Enable (Wn), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). The device enable (En) controls device selection, active, and standby modes. Asserting En enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to each memory die by selecting the 2,048,000 byte of memory. Wn controls read and write operations. During a read cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

G

Wn

En

I/O Mode

Mode

X

1

X

1

3-state

Standby

 

 

 

 

 

 

X

0

0

Data in

Write

1

1

0

3-state

Read

2

 

 

 

 

 

 

0

1

0

Data out

Read

 

 

 

 

 

 

 

 

Notes:

1.“X” is defined as a “don’t care” condition.

2.Device active; outputs disabled.

READ CYCLE

A combination of Wn greater than V IH (min) with En and G less than VIL (max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output.

SRAM read Cycle 1, the Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and Wn deasserted. Valid data appears on data outputs DQn(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t AVAV).

SRAM read Cycle 2, the Chip Enable-controlled Access is initiated by En going active while G remains asserted, Wn remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQn(7:0).

SRAM read Cycle 3, the Output Enable-controlled Access is initiated by G going active while En is asserted, Wn is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.

2

WRITE CYCLE

A combination of Wn less than VIL(max) and En less than

VIL(max) defines a write cycle. The state of G is a “don’t care” for a write cycle. The outputs are placed in the high-impedance state when eitherG is greater than V IH(min), or when Wn is less than VIL(max).

Write Cycle 1, the Write Enable-controlled Access is defined by a write terminated by Wn going high, with En still active. The write pulse width is defined by tWLWH when the write is initiated byWn, and by tETWH when the write is initiated byEn. Unless the outputs have been previously placed in the highimpedance state byG, the user must wait t WLQZ before applying data to the eight bidirectional pins DQn(7:0) to avoid bus contention.

Write Cycle 2, the Chip Enable-controlled Access is defined by a write terminated by the former of En or Wn going inactive. The write pulse width is defined by tWLEF when the write is initiated by Wn, and by tETEF when the write is initiated by the En going active. For the Wn initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQn(7:0) to avoid bus contention.

TYPICAL RADIATION HARDNESS

The UT8Q512K32 SRAM incorporates features which allow operation in a limited radiation environment.

Table 2. Typical Radiation Hardness

Design Specifications1

Total Dose

50

krad(Si) nominal

Heavy Ion

<1E-8

Errors/Bit-Day

Error Rate 2

 

 

 

 

 

Notes:

1.The SRAM will not latchup during radiation exposure under recommended operating conditions.

2.90% worst case particle environment, Geosynchronous orbit, 100 mils of Aluminum.

3

ABSOLUTE MAXIMUM RATINGS1

(Referenced to VSS)

SYMBOL

PARAMETER

VDD

DC supply voltage

VI/O

Voltage on any pin

TSTG

Storage temperature

PD

Maximum power dissipation

TJ

Maximum junction temperature2

ΘJC

Thermal resistance, junction-to-case3

II

DC input current

 

 

Notes:

LIMITS

-0.5 to 4.6V -0.5 to 4.6V -65 to +150°C 1.0W (per byte) +150°C

10°C/W

±10 mA

1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.

2.Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.

3.Test per MIL-STD-883, Method 1012.

RECOMMENDED OPERATING CONDITIONS

 

 

 

SYMBOL

 

PARAMETER

 

LIMITS

 

 

 

 

VDD

 

Positive supply voltage

 

3.0 to 3.6V

 

TC

 

Case temperature range

 

-40 to +125°C

 

VIN

 

DC input voltage

 

0V to VDD

4

UTMC 5962P0153301TXC, 5962P0153301QXC, 5962L0153301TXC, 5962-0153301TXC, 5962-0153301QXC, UT8Q512K32-SPC, UT8Q512K32-SWC Datasheet

DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*

(-40°C to +125°C) (VDD = 3.3V + 0.3)

SYMBOL

PARAMETER

CONDITION

 

VIH

High-level input voltage

(CMOS)

 

VIL

Low-level input voltage

(CMOS)

VOL1

Low-level output voltage

IOL = 8mA, V DD =3.0V

VOL2

Low-level output voltage

IOL = 200mA,VDD =3.0V

VOH1

High-level output voltage

IOH = -4mA,VDD =3.0V

VOH2

High-level output voltage

IOH = -200mA,VDD =3.0V

 

 

1

Input capacitance

¦ = 1MHz @ 0V

CIN

 

 

 

 

1

Bidirectional I/O capacitance

¦ = 1MHz @ 0V

CIO

 

 

 

IIN

Input leakage current

VSS < VIN < VDD, VDD = VDD (max)

 

IOZ

Three-state output leakage current

0V < VO < VDD

 

 

 

 

VDD = VDD (max)

 

 

 

 

G = VDD (max)

I

 

2, 3

Short-circuit output current

0V < VO < VDD

OS

 

 

I

 

(OP)

Supply current operating

Inputs: VIL = 0.8V,

DD

 

@ 1MHz

VIH = 2.0V

 

 

 

 

 

 

(per byte)

IOUT = 0mA

 

 

 

 

 

 

 

 

VDD = VDD (max)

IDD1(OP)

Supply current operating

Inputs: VIL = 0.8V,

 

 

 

@40MHz

VIH = 2.0V

 

 

 

(per byte)

IOUT = 0mA

 

 

 

 

 

 

 

 

VDD = VDD (max)

IDD2 (SB)

Nominal standby supply current

Inputs: VIL = VSS

 

 

 

@0MHz

IOUT = 0mA

 

 

 

(per byte)

En = VDD - 0.5, VDD = VDD (max)

 

 

 

 

 

 

 

 

VIH = VDD - 0.5V

 

 

 

 

 

Notes:

* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 101 9 .

1.Measured only for initial qualification and after process or design changes that could affect input/output capacitance.

2.Supplied as a design limit but not guaranteed or tested.

3.Not more than one output may be shorted at a time for maximum duration of one second.

MIN

MAX

UNIT

2.0

 

V

 

0.8

V

 

0.4

V

 

 

 

0.08

V

2.4

 

V

VDD-0.10

 

V

 

32

pF

 

16

pF

-2

2

mA

-2

2

mA

-90

90

mA

 

125

mA

180 mA

-40°C and

6

mA

25°C

 

 

+125°C

40

mA

 

 

5

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