UTMC 5962R0150202VYC, 5962R0150202VXC, 5962R0150202QYC, 5962R0150202QXC, 5962R0150201VYC, 5962R0150201VXX, 5962R0150201VXC, 5962R0150201QYC, 5962R0150201QXX, 5962R0150201QXC, 5962H0150202VXX, 5962H0150202VXC, 5962H0150202VXA, 5962H0150202QYC, 5962H0150202QXX, 5962H0150202QXC, 5962H0150202QXA, 5962H0150201VYC, 5962H0150201VXX, 5962H0150201VXC, 5962H0150201VXA, 5962H0150201QYC, 5962H0150201QXX, 5962H0150201QXC, 5962H0150201QXA, 5962G0150202VYC, 5962G0150202VXC, 5962G0150202QYC, 5962G0150202QXX, 5962G0150202QXC, 5962G0150201VYC, 5962G0150201VXX, 5962G0150201VXC, 5962G0150201VXA, 5962G0150201QXX, 5962G0150201QXC, 5962G0150201QXA, 5962F0150202VYC, 5962F0150202VXX, 5962F0150202VXC, 5962F0150202VXA, 5962F0150202QYC, 5962F0150202QXC, 5962F0150202QXA, 5962F0150201VYC, 5962F0150201VXX, 5962F0150201VXC, 5962F0150201QYC, 5962F0150201QXX, 5962F0150201QXA, 5962-0150202VYC, 5962-0150202VXC, 5962-0150202VXA, 5962-0150202QYC, 5962-0150202QXX, 5962-0150202QXC, 5962-0150202QXA, 5962-0150201VYC, 5962-0150201VXX, 5962-0150201VXC, 5962-0150201QXX, 5962-0150201QXC, 5962-0150201QXA, UT1750AR16WPX, UT1750AR16WCC, UT1750AR16GCC, UT1750AR12WPC, UT1750AR12WCC, UT1750AR12GPC, UT1750AR12GCA Datasheet

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UTMC 5962R0150202VYC, 5962R0150202VXC, 5962R0150202QYC, 5962R0150202QXC, 5962R0150201VYC, 5962R0150201VXX, 5962R0150201VXC, 5962R0150201QYC, 5962R0150201QXX, 5962R0150201QXC, 5962H0150202VXX, 5962H0150202VXC, 5962H0150202VXA, 5962H0150202QYC, 5962H0150202QXX, 5962H0150202QXC, 5962H0150202QXA, 5962H0150201VYC, 5962H0150201VXX, 5962H0150201VXC, 5962H0150201VXA, 5962H0150201QYC, 5962H0150201QXX, 5962H0150201QXC, 5962H0150201QXA, 5962G0150202VYC, 5962G0150202VXC, 5962G0150202QYC, 5962G0150202QXX, 5962G0150202QXC, 5962G0150201VYC, 5962G0150201VXX, 5962G0150201VXC, 5962G0150201VXA, 5962G0150201QXX, 5962G0150201QXC, 5962G0150201QXA, 5962F0150202VYC, 5962F0150202VXX, 5962F0150202VXC, 5962F0150202VXA, 5962F0150202QYC, 5962F0150202QXC, 5962F0150202QXA, 5962F0150201VYC, 5962F0150201VXX, 5962F0150201VXC, 5962F0150201QYC, 5962F0150201QXX, 5962F0150201QXA, 5962-0150202VYC, 5962-0150202VXC, 5962-0150202VXA, 5962-0150202QYC, 5962-0150202QXX, 5962-0150202QXC, 5962-0150202QXA, 5962-0150201VYC, 5962-0150201VXX, 5962-0150201VXC, 5962-0150201QXX, 5962-0150201QXC, 5962-0150201QXA, UT1750AR16WPX, UT1750AR16WCC, UT1750AR16GCC, UT1750AR12WPC, UT1750AR12WCC, UT1750AR12GPC, UT1750AR12GCA Datasheet

Standard Products

UT1750AR RadHard RISC Microprocessor

Data Sheet

May 2003

FEATURES

qOperates in either RISC (Reduced Instruction Set Computer) mode or MIL-STD-1750A mode

qSupports MIL-STD-1750A 32-bit floating-point operations and 48-bit extended-precision floating-point operations on chip

qBuilt-in 9600 baud UART

qSupports defined MIL-STD-1750A Console Mode of Operation

qFull 64K-word address space. Expandable to 1M words with optional MMU (operand port)

qRegister-oriented architecture has 21 user-accessible registers

qRegisters may be in 16-bit word or 32-bit double-word configurations

qBuilt-in multiprocessor bus arbitration and Direct Memory Access support (DMA)

qTTL-compatible I/O

qStable 1.5-micron CMOS technology

qFull military operating range, -55°C to +125°C, in accordance with MIL-PRF-38535 for Class Q and V

qTypical radiation performance

-Total dose: 1.0E6 rads(Si)

-SEL Immune . 100 MeV-cm2/mg

-LETTH(0.25) = 60 MeV-cm2/mg

-Saturated Cross Section (cm2) per bit, 1.2E-7

-2.3E-11 errors/bit-day, Adams to 90% geosynchronous heavy ion

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OSCOUT

 

 

 

 

 

 

 

 

q Standard Military Drawing 5962-01502

 

 

 

OE

 

 

 

 

 

 

RISC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MEMORY

 

 

 

 

 

 

 

 

OSCIN

 

SYSCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UART

 

 

 

 

 

 

 

 

 

TIMCLK

BRQ

 

 

 

 

 

 

BUS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST

BGNT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GENERAL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TBR

 

 

 

 

 

 

 

 

 

UARTOUT

 

 

 

 

 

ARBITRA-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUSY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OSCILLATOR

 

 

PURPOSE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RBR

 

 

 

 

 

 

 

 

 

UARTIN

 

 

 

 

 

 

TION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BGACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

/CLOCK

 

 

REGISTERS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NUI1

 

 

 

 

 

PROCES-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NUI2

 

 

 

 

 

 

SOR

 

 

 

 

 

 

 

 

 

 

 

 

 

SHIFT REG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TR

 

16

 

 

 

 

 

 

 

 

 

M1750

 

 

 

 

 

 

STATUS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

 

 

3 2

 

 

BIT REG

 

 

32

 

 

 

 

 

 

 

 

TB

 

1 6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STATE1

 

 

 

 

 

 

 

 

 

 

 

 

 

PROCESSOR

 

 

 

 

TEMP DEST

 

TEMP SRC

 

 

 

 

 

 

 

 

 

 

 

 

 

IM

 

16

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MME

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FR

 

16

 

 

MUX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NUO3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PI

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONSOLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S T

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IR

 

 

 

RISC MAP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SW

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RISC DATA

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 2

 

32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

PS0-3

RISC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

AS0-3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 6

 

 

 

OPERAND

ADDRESS

 

 

4

 

 

 

 

 

 

 

 

 

IC/ICs

 

 

 

 

 

 

ACC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

or O/P DISC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

RISC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OP/IN

 

 

 

 

 

 

 

 

 

 

 

 

 

3 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIPELINE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DTACK

RISC 1 6

 

ADD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS

 

 

 

 

 

 

 

 

 

3 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDRESS

 

 

 

 

 

MUX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PR

 

CONTROL

 

 

 

M/IO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W R

SYSFL

 

 

 

 

 

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A MUX

 

 

 

B MUX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AS

BTERR

 

 

 

 

 

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 6

 

 

 

 

 

 

DS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OPERAND

MPAR

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1750 SP

1 6

 

 

 

 

 

 

 

 

 

 

 

ADDRESS

MPROT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32-BIT ALU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PFAIL

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDR

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 2

 

 

 

 

MUX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1750 PC

 

 

 

 

 

 

 

 

 

 

 

 

 

IOLINT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 6

 

 

 

 

 

 

 

 

 

 

 

 

 

IOLINT0

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT0-5

 

6

 

 

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1. UT1750AR Functional Block Diagram

MRST

RA19/CS

RA18/OD1

RA17/OD2

RA16/OD3

RA15

RA14

RA13

RA12

RA11

RA10

RA9

RA8

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RA0

NUI1

NUI2

M1750

MME CONSOLE STATE1 OSCIN OSCOUT

UARTIN

UARTOUT TIMCLK TEST

SYSFLT BTERR MPAR MPROT INT5 INT4 INT3 INT2 INT1 INT0 PFAIL IOLINT0 IOLINT1

MRST

RD0 - RD15

RISC DATA PORT

BUS

ARBITRATION

BUS

CONTROL UT1750AR

RISC

ADDRESS BUS

CLOCK

MODE

PROCESSOR

STATUS

OSCILLATOR

MEMORY

UART

 

OPERAND

INTERRUPTS/

ADDRESS

EXCEPTIONS

BUS

OPERAND

DATA BUS

D0 - D15

Figure 2. UT1750AR Pin Function Diagram

BRQ

BGNT

BUSY

BGACK

OP/IN

DTACK

M/IO

R/WR

AS

DS

SYSCLK

AS0

AS1

AS2

AS3

PS0

PS1

PS2

PS3

NUO3

O E

WE

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

2

GENERAL DESCRIPTION

The UT1750AR (figures 1 and 2) is a high performance monolithic CMOS 16-bit RISC microprocessor that supports the complete MIL-STD-1750A Instruction Set Architecture (ISA). Underlying the MIL-STD-1750A support is a highperformance RISC that provides MIL-STD-1750A emulation capability. Developed to provide effective real-time avionics processing, the high performance of the native RISC machine is available to the MIL-STD-1750A systems designer through the MIL-STD-1750A Built-In-Function (BIF) opcode.

The UT1750AR is the first member of a family of highperformance MIL-STD-1750 processors and support peripherals from UTMC.

PRODUCT DESCRIPTION

The UTMC UT1750AR operates in its native RISC language mode or MIL-STD-1750A ISA mode. As a MIL-STD-1750A microprocessor, the UT1750AR requires 8K x 16 of ROM to map the MIL-STD-1750A instruction set into the native RISC machine language instructions. Each MIL-STD-1750A opcode has a unique RISC code macro in the external ROM. The UT1750AR executes the corresponding resident RISC code macro to perform the MIL-STD-1750A instruction requirements. When in this mode and operating with a 12 MHz clock, the UT1750AR can throughput 600 KIPS using the DAIS mix (800 KIPS @ 16 MHz).

The native RISC language mode is available to the user when the UT1750AR is operating as MIL-STD-1750A processor through MIL- STD-1750A’s Built-In Function (BIF) opcode. When operating as a RISC processor, the UT1750AR executes most RISC instructions in two clock cycles. Thus, a 12 MHz operating clock frequency provides up to 6 MIPS of RISC throughput (8 MIPS @16 MHz). This high execution rate, along with its efficient architecture, make the RISC mode especially effective in applications requiring real-time processing.

The architecture of the UT1750AR is based around 20 useraccessible, 16-bit general purpose registers providing the programmer with extensive register support. The UT1750AR’s flexibility is enhanced by its ability to concatenate the 16-bit registers into ten 32-bit registers. In addition, all registers are available for use as either the source or the destination for any register operation.

The UT1750AR fully supports multiprocessor, DMA, and complex bus arbitration for managing the system bus and preventing bus contention. Bus control passes among bus masters operating on the same bus. The bus masters can be several UT1750ARs or any other device requiring Direct Memory Access, such as a MIL-STD-1553B interface.

The UT1750AR supports 16 levels of vectored interrupts. Ten of these are external interrupts, eight of which are userdefinable. All 16 interrupt levels are prioritized and serviced in order of priority.

When used as a MIL-STD-1750A microprocessor, the UT1750AR’s instruction set supports 16-bit fixed-point singleprecision and 32-bit fixed-point double-precision data formats. Also, the UT1750AR can emulate 32-bit floating-point and 48bit floating-point extended-precision data in two’s complement representation.

In its native RISC mode, the UT1750AR’s three basic instruction formats support 16-bit and 32-bit instructions. The formats are Register-to-Register, Register-to-Literal, and Register-to-Long-Immediate instructions.

Figure 3 shows the UT1750AR’s general system architecture, its emulation ROM, instruction and data memory, and the system interface. The emulation ROM is isolated from the system; only the UT1750AR microprocessor accesses it.

 

RISC DATA

 

OPERAND DATA

MIL-STD-1750A

 

 

16

 

16

 

MEMORY

 

 

 

EMULATION

 

CONTROL

INSTRUCTIONS

 

 

 

 

 

 

ROM

RISC ADDRESS

UT1750AR

OPERAND ADDRESS

 

(8K X 16)

16

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3. UT1750AR MIL-STD-1750A General System Architecture

3

FUNCTIONAL PINOUT

Legend for TYPE and ACTIVE fields:

TO

=

TTL output

TI

=

TTL input

TUI

=

TTL input (pull-up)

TDI

=

TTL input (pull-down)

TTO

=

Three-state TTL output

OSCILLATOR AND CLOCK SIGNALS

TTB

=

Three-state TTL bidirectional

CO

=

CMOS output

OSC

= Oscillator input to a Pierce Oscillator inverter

AH

=

Active High

AL

=

Active Low

PIN NAME

PIN NUMBER

TYPE

ACTIVE

FLTPK

PGA

 

 

 

OSCIN

50

P14

OSC

--

OSCOUT

51

P15

CO

--

SYSCLK

52

M14

TO

--

 

 

 

 

 

DESCRIPTION

Oscillator Input. A 50% duty cycle crystal-drive input for driving the UT1750AR.

Oscillator Output. A 50% duty cycle, single-phase clock output at the same frequency as the OSCIN input.

System Output. The buffered equivalent of the OSCOUT signal.

PROCESSOR STATUS

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

PGA

 

 

 

 

NUI1

129

H2

TI

--

Not used input 1. Internal UTMC use only. Tie either high

 

 

 

 

 

or low.

NUI2

44

P12

TUI

--

Not used input 2. Internal UTMC use only. Tie low.

NUO3

126

G3

TTO

--

Not used output 3. Internal UTMC use only. NUO3 enter

 

 

 

 

 

high impedance state when the UT1750AR is in the test

 

 

 

 

 

mode (TEST=0)

M1750

45

N11

TDI

AH

Mode Select RISC/1750. A high on M1750 places the

 

 

 

 

 

UT1750AR into the MIL-STD-1750A emulation mode.

 

 

 

 

 

A low on M1750 places the UT1750AR into the RISC

 

 

 

 

 

mode. It is tied to an internal pull-down resistor.

STATE1

54

N15

TTO

--

Processor State. This signal indicates the internal state of

 

 

 

 

 

the UT1750AR. A low on STATE1 indicates the

 

 

 

 

 

UT1750AR is executing a new RISC instruction. A high

 

 

 

 

 

on STATE1 indicates the UT1750AR is fetching a RISC

 

 

 

 

 

instruction. STATE1 enters a high-impedance state when

 

 

 

 

 

the UT1750AR is in the test mode (TEST=0).

4

OPERAND DATA BUS ARBITRATION

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

 

PGA

 

 

 

 

 

BRQ

118

 

D2

TTO

AL

Bus Request. The UT1750AR asserts this signal to indicate

 

 

 

 

 

 

it is requesting control of the Operand data bus (D0 - D15).

 

 

 

 

 

 

BRQ enters a high-impedance state when the UT1750AR is

 

 

 

 

 

 

in the test mode (TEST = 0).

BGNT

119

 

E3

TUI

AL

Bus Grant. When asserted, this signal indicates the

 

 

 

 

 

 

UT1750AR may take control of the Operand data bus. It is

 

 

 

 

 

 

tied to an internal pull-up resistor.

BUSY

120

 

C1

TUI

AL

Bus Busy. A bus master asserts this input to inform the

 

 

 

 

 

 

UT1750AR that another bus master is using the Operand

 

 

 

 

 

 

data bus. It is tied to an internal pull-up resistor.

BGACK

117

 

B1

TTO

AL

Bus Grant Acknowledge Output. The UT1750AR asserts

 

 

 

 

 

 

this signal to indicate it is the current bus master. When low,

 

 

 

 

 

 

BGACK inhibits other devices from becoming the bus

 

 

 

 

 

 

master. When the UT1750AR relinquishes control of the

 

 

 

 

 

 

bus, BGACK enters a high-impedance state.

 

 

 

 

 

 

 

OPERAND DATA BUS CONTROL

 

 

 

 

 

 

 

 

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

 

PGA

 

 

 

 

 

OP/IN

113

 

A2

TTO

--

Operand/Instruction. This indicates whether the

 

 

 

 

 

 

UT1750AR’s current bus cycle is for Data (high) or

 

 

 

 

 

 

Instruction (low) acquisition. OP/IN remains in a high

 

 

 

 

 

 

state whenever a bus cycle (Memory or I/O) is not an

 

 

 

 

 

 

instruction fetch.

DTACK

121

 

E2

TUI

AL

Data Transfer Acknowledge. This signal tells the

 

 

 

 

 

 

UT1750AR that a data transfer has been acknowledged

 

 

 

 

 

 

and the UT1750AR can complete the bus cycle. To assure

 

 

 

 

 

 

the UT1750AR operates with no wait states,DTACK can

 

 

 

 

 

 

be tied low. DTACK is tied to an internal pull-up resistor.

M/IO

112

 

B3

TTO

--

Memory or I/O. Indicates whether the current bus cycle

 

 

 

 

 

 

is for memory (high) or I/O (low). It remains in the high-

 

 

 

 

 

 

impedance state during bus cycles when the UT1750AR

 

 

 

 

 

 

does not control the Operand busses.

R/WR

114

 

C4

TTO

--

Read/Write. Indicates the direction of data flow with

 

 

 

 

 

 

respect to the UT1750AR. R/WR high means the

 

 

 

 

 

 

UT1750AR is attempting to read data from an external

 

 

 

 

 

 

device, and R/WR low means the UT1750AR is

 

 

 

 

 

 

attempting to write data to an external device. R/WR

 

 

 

 

 

 

remains in a high-impedance state when the UT1750AR

 

 

 

 

 

 

does not control the Operand busses.

 

 

 

 

 

 

 

 

 

 

 

 

 

Continued on page 6.

5

OPERAND DATA BUS CONTROL

 

Continued from page 5.

 

 

 

 

 

 

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

PGA

 

 

 

 

AS

115

C3

TTO

AL

Address Strobe. Indicates a valid address on the Operand

 

 

 

 

 

Address bus. UT1750AR places AS in a high-impedance

 

 

 

 

 

state when it does not control the Operand busses.

DS

116

B2

TTO

AL

Data Strobe. Indicates valid data is on the Operand Data bus.

 

 

 

 

 

The UT1750AR places DS in a high-impedance state when

 

 

 

 

 

it does not control the Operand busses.

 

 

 

 

 

 

RISC MEMORY CONTROL

 

 

 

 

 

 

 

 

 

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

PGA

 

 

 

 

OE

42

R12

TTO

AL

Output Enable RISC Memory. This signal

 

 

 

 

 

allows RISC memory to place data on the RISC instruction

 

 

 

 

 

data bus. The Store Register to Instruction Memory (STRI)

 

 

 

 

 

instruction removes OE during the CK2 internal clock

 

 

 

 

 

cycle. OE enters a high-impedance state when the

 

 

 

 

 

UT1750AR is in the test mode (TEST = 0).

WE

43

R13

TTO

AL

Write Enable RISC Memory. This signal allows the

 

 

 

 

 

UT1750AR to write to RISC instruction memory. The

 

 

 

 

 

Store Register to Instruction Memory (STRI) instruction

 

 

 

 

 

asserts WE during the CK2 internal clock cycle. WE

 

 

 

 

 

enters a high-impedance state when the UT1750AR is in

 

 

 

 

 

the test mode (TEST = 0).

 

 

 

 

 

 

UART CONTROL/TIMER CLOCK

 

 

 

 

 

 

 

 

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

PGA

 

 

 

 

UARTIN

127

F1

TUI

AH

UART Input. The UT1750AR receives serial data

 

 

 

 

 

through this input. The serial data is stored in the

 

 

 

 

 

UT1750AR’s Receiver Buffer Register (RCVR). It is tied

 

 

 

 

 

to an internal pull-up resistor.

UARTOUT

128

G1

TTO

AH

UART Output. The serial data stored in the UT1750AR’s

 

 

 

 

 

Transmitter Buffer Register (TXMT) is transmitted

 

 

 

 

 

through this output. The UART output is fixed at 9600

 

 

 

 

 

baud, with eight data bits, odd-parity, and one stop bit.

 

 

 

 

 

UARTOUT enters a high-impedance state when the

 

 

 

 

 

UT1750AR is in the test mode (TEST=0). (9600 baud @

 

 

 

 

 

TIMCLK = 12MHz)

 

 

 

 

 

Continued on page 7.

6

UART CONTROL/TIMER CLOCK

 

Continued from page 6

 

 

 

 

 

 

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

PGA

 

 

 

 

TIMCLK

53

L13

TI

--

Timer Clock. This 12 MHz clock input generates the baud

 

 

 

 

 

rate for the UT1750AR’s internal UART. The input also

 

 

 

 

 

provides the clock for the UT1750AR’s two internal MIL-

 

 

 

 

 

STD-1750A timers (TIMER A and TIMER B).

CONSOLE

48

N12

TDI

AH

Console (Command). Asserting this input sets bit 3 in the

 

 

 

 

 

System Status Register. Bit 3 is read with the Input Register

 

 

 

 

 

Instruction (INR). When the UT1750AR is operating in the

 

 

 

 

 

MIL-STD-1750 mode, asserting CONSOLE during a

 

 

 

 

 

Master Reset invokes the maintenance console option. Tied

 

 

 

 

 

to an internal pull-down resistor.

TEST

46

P13

TUI

AL

Test (Input). Asserting this input places the UT1750AR

 

 

 

 

 

into a test mode. In this mode, all the UT1750AR’s

 

 

 

 

 

outputs, except OSCOUT and SYSCLK, enter a high-

 

 

 

 

 

impedance state. When using TEST, the UT1750AR

 

 

 

 

 

must have a MRST. MRST must be held active for at

 

 

 

 

 

least one SYSCLK period after TEST is

 

 

 

 

 

deasserted to assure proper operation (see figure 42b).

 

 

 

 

 

TEST is tied to an internal pull-up resistor.

MME

49

N13

TDI

AH

Memory Management Enable. This signal indicates to

 

 

 

 

 

the UT1750AR that a Memory Management Unit

 

 

 

 

 

(MMU) is present and that the memory management

 

 

 

 

 

option is enabled. MME is tied to an internal pull-down

 

 

 

 

 

resistor.

PROCESSOR MODE

 

 

 

 

 

 

 

 

 

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

PGA

 

 

 

 

AS0

104

B7

TTO

AH

Address State. These outputs indicate the current address

AS1

105

B6

 

 

state of the UT1750AR. Using these outputs with a

AS2

106

C6

 

 

Memory Management Unit (MMU) allows selecting the

AS3

107

A5

 

 

 

 

MMU’s page register group. These outputs enter a

 

 

 

 

 

 

 

 

 

 

high-impedance state when the UT1750AR is placed in

 

 

 

 

 

the test mode (TEST=0) or during bus cycles not assigned

 

 

 

 

 

to this processor.

PS0

108

A4

TTO

AH

Processor State. These outputs indicate the current state

PS1

109

A3

 

 

of the processor. These outputs enter a high-impedance

PS2

110

B4

 

 

state when the UT1750AR is in the test mode (TEST=0)

PS3

111

C5

 

 

 

 

or during bus cycles not assigned to this processor.

 

 

 

 

 

 

 

 

 

 

 

7

INTERRUPTS/EXCEPTIONS

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

PGA

 

 

 

 

SYSFLT

125

G2

TUI

AH

System Fault. This positive edge-triggered input sets bit 8

 

 

 

 

 

(SYSFLT) in the UT1750AR’s Fault Register. Under no

 

 

 

 

 

circumstances should SYSFLT be tied in its active state. It

 

 

 

 

 

is tied to an internal pull-up resistor.

BTERR

122

D1

TUI

AL

Bus Time Error. It is asserted when a bus error or a timeout occurs.

 

 

 

 

 

During I/O bus cycles, an active BTERR sets bit 10 of the Fault

 

 

 

 

 

Register. During Memory bus cycles, an active BTERR sets bit 7

 

 

 

 

 

of the Fault Register. Under no circumstances should BTERR be

 

 

 

 

 

tied in its active state. It is tied to an internal pull-up resistor.

 

 

 

 

 

Interrupt is not cleared via software until the negation of the input

 

 

 

 

 

signal.

MPAR

124

F2

TDI

AH

Memory Parity (Error). Asserting this input indicates a MIL-STD-

 

 

 

 

 

1750 memory parity error. Bit 13 of the UT1750AR’s Fault

 

 

 

 

 

Register, Memory Parity Fault, is set when MPAR is active. Under

 

 

 

 

 

no circumstances should MPAR be tied in its active state. It is tied

 

 

 

 

 

to an internal pull-down resistor. Interrupt is not cleared via

 

 

 

 

 

software until the negation of the input signal.

MPROT

123

F3

TUI

AH

Memory Protect Fault. When asserted, it informs the UT1750AR that

 

 

 

 

 

a memory-protect fault has occurred on the Operand Data Bus. An

 

 

 

 

 

access fault, a write-protect fault, or an execute-protect fault causes a

 

 

 

 

 

memory-protect fault. If the UT1750AR is using the bus and MPROT

 

 

 

 

 

is asserted, bit 15 of the Fault Register (CPU Fault) is set. If the

 

 

 

 

 

UT1750AR is not using the bus and MPROT is asserted, bit 14 of the

 

 

 

 

 

Fault Register (DMA Error) is set. It is tied to an internal pull-up

 

 

 

 

 

resistor. Interrupt is not cleared via software until the negation of the

 

 

 

 

 

input signal.

INT0

56

M15

TUI

AL

User Interrupts. These interrupts are active on a negative-

INT1

57

K13

 

 

going edge and each will set, when active, its associated bit

INT2

58

K14

 

 

in the Pending Interrupt Register. The interrupts are maskable

INT3

59

J14

 

 

 

 

by setting the associated bits in the Interrupt Mask Register.

INT4

60

J13

 

 

 

 

Asserting MRST resets all interrupts. They are tied to an

INT5

61

K15

 

 

 

 

internal pull-up resistor.

 

 

 

 

 

IOLINT0

62

J15

TUI

AL

I/O Level Interrupts. These inputs are active on a negative-

IOLINT1

63

H14

 

 

going edge and each sets, when active, its associated bit in

 

 

 

 

 

the Pending Interrupt Register. The interrupts are maskable

 

 

 

 

 

by setting the associated bits in the Interrupt Mask Register.

 

 

 

 

 

Asserting MRST resets all interrupts. They are tied to an

 

 

 

 

 

internal pull-up resistor.

PFAIL

55

L14

TUI

AL

Power Fail (Interrupt). Asserting this input informs the

 

 

 

 

 

UT1750AR that a power failure has occurred and the present

 

 

 

 

 

process will be interrupted. This input sets bit 15 in the Pending

 

 

 

 

 

Interrupt Register. A Power Fail Interrupt (bit 15) cannot be

 

 

 

 

 

disabled. When operating in the RISC mode, the UT1750AR

 

 

 

 

 

must be reset after a PFAIL to assure normal operation. It is

 

 

 

 

 

tied to an internal pull-up resistor.

MRST

47

R14

TUI

AL

Master Reset. This input initializes the UT1750AR to a

 

 

 

 

 

reset state. The UT1750AR must be reset after power

 

 

 

 

 

(Vcc) is within specification and stable to ensure proper

 

 

 

 

 

operation. The system must hold MRST active for at least

 

 

 

 

 

one period of SYSCLK to assure the UT1750AR will be

 

 

 

 

 

reset. It is tied to an internal pull-up resistor.

 

 

 

 

 

 

8

OPERAND BUSSES

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

PGA

 

 

 

 

A0

84

A14

TTO

--

Address Bus - Operand. When asserted, this bus is

A1

85

B12

 

 

unidirectional and represents the Operand Address. The bus

A2

86

C11

 

 

is in the high-impedance state when the UT1750AR does

A3

87

A13

 

 

 

 

not control the bus. A15 is the most significant bit. The

A4

88

B11

 

 

 

 

Operand Address enters a high-impedance state when the

A5

89

A12

 

 

A6

90

C10

 

 

UT1750AR is in the test mode (TEST = 0).

A7

91

B10

 

 

 

A8

92

B9

 

 

 

A9

93

C9

 

 

 

A10

94

A10

 

 

 

A11

95

A9

 

 

 

A12

96

B8

 

 

 

A13

97

A8

 

 

 

A14

102

A7

 

 

 

A15

103

A6

 

 

 

D0

64

H15

TTB

--

Data Bus - Operand. This bidirectional data bus remains

D1

69

G15

 

 

in a high-impedance state when the UT1750AR does not

D2

70

F15

 

 

 

 

control the bus. D15 is the most significant bit. The

D3

71

G14

 

 

 

 

Operand Data Bus enters a high-impedance state when

D4

72

F14

 

 

 

 

the UT1750AR is in the test mode (TEST = 0).

D5

73

F13

 

 

D6

74

E15

 

 

 

D7

75

D15

 

 

 

D8

76

C15

 

 

 

D9

77

D14

 

 

 

D10

78

E13

 

 

 

D11

79

C14

 

 

 

D12

80

B15

 

 

 

D13

81

D13

 

 

 

D14

82

C13

 

 

 

D15

83

B14

 

 

 

RISC BUSSES

 

 

 

 

 

 

 

 

 

 

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

 

FLTPK

PGA

 

 

 

RA0

18

R2

TTO

--

RISC (Instruction) Address Bus. This unidirectional bus

RA1

19

P4

 

 

represents the address of the data in RISC memory. With the

RA2

20

N5

 

 

MIL-STD-1750A mode of operation selected (M1750 = 1),

RA3

21

R3

 

 

 

 

the data from RISC memory is from the emulation ROMs. This

RA4

22

P5

 

 

 

 

data is the RISC instructions that the UT1750AR executes to

RA5

23

R4

 

 

 

 

emulate MIL-STD-1750A instructions. RA15 is the most

RA6

24

N6

 

 

RA7

25

P6

 

 

significant bit. The RISC address enters a high-impedance

RA8

26

P7

 

 

state when the UT1750AR is in the test mode (TEST = 0).

RA9

27

N7

 

 

 

RA10

28

R6

 

 

 

RA11

29

R7

 

 

 

RA12

30

P8

 

 

 

RA13

31

R8

 

 

 

RA14

36

R9

 

 

 

RA15

37

R10

 

 

 

Continued on page 10.

9

RISC BUSSES

Continued from page 9.

PIN NAME

PIN NUMBER

TYPE

ACTIVE

FLTPK

PGA

 

 

 

RA16/OD3

38

P9

TTO

--

RA17/OD2

39

P10

 

 

RA18/OD1

40

N10

 

 

RA19/CS

41

R11

 

 

RD0

130

H1

TTB

--

RD1

3

J1

 

 

RD2

4

K1

 

 

RD3

5

J2

 

 

RD4

6

K2

 

 

RD5

7

K3

 

 

RD6

8

L1

 

 

RD7

9

M1

 

 

RD8

10

N1

 

 

RD9

11

M2

 

 

RD10

12

L3

 

 

RD11

13

N2

 

 

RD12

14

P1

 

 

RD13

15

M3

 

 

RD14

16

N3

 

 

RD15

17

P2

 

 

DESCRIPTION

RISC Instruction Address Bus/Output Discretes. When the UT1750AR is operating in the RISC mode (M1750 = 0) these four bits represent the four most significant address bits. In the MIL- STD-1750A mode (M1750 = 1) these four bits are user-programmable output discretes defined as follows:

RA19/ CS = Chip Select (AL) RA18/OD1 = Output Discrete 1 RA17/OD2 = Output Discrete 2 RA16/OD3 = Output Discrete 3

These output discretes are programmed with the Output Register (OTR) RISC opcode. These signals enter a high- impedance state when the UT1750AR is in the test mode (TEST = 0).

RISC Instruction Data Bus. This bidirectional data bus is the interface with the RISC memory. When the UT1750AR is in the MIL-STD-1750A mode of operation, the data comes from the emulation ROMs. This data is executed to emulate the MIL-STD-1750A Instruction Set. RD15 is the most significant bit. The RISC Data Bus enters a high-impedance state only when the UT1750AR is in the test mode (TEST = 0).

POWER AND GROUND

PIN NAME

PIN NUMBER

TYPE

ACTIVE

DESCRIPTION

FLTPK

PGA

 

 

 

 

VDD

34

H3

--

--

+5 VDC Power. Power supply input.

 

67

N9

 

 

 

 

100

G13

 

 

 

 

132

C7

 

 

 

VSS

1

J3

--

--

Reference Ground. Zero VDC logic ground.

 

33

N8

 

 

 

 

66

H13

 

 

 

 

99

C8

 

 

 

 

 

 

 

 

 

10

GENERAL OPERATION

The UT1750AR can operate in two modes. The first operating mode is the Reduced Instruction Set Computer (RISC) mode; the second is the MIL-STD-1750A Instruction Set Architecture (ISA) emulation mode. The mode-select input pin (M1750) determines the UT1750AR’s operating mode. M1750 must be tied high to enable the MIL-STD-1750A ISAemulation mode of operation; otherwise, an internal pull-down resistor pulls M1750 low, selecting the RISC mode.

The UT1750AR has a Harvard architecture when it operates in the RISC mode (M1750 = 0). A processor with a Harvard architecture has two sets of address and data busses; one set interfaces with instruction memory and the other set interfaces with operand memory. This architecture allows the UT1750AR to perform overlapping instruction fetch-and-execute bus cycles that enhance processor throughput.

The UT1750AR’s reduced instruction set consists of 30 separate instructions. The UT1750AR executes most of these instructions in two clock cycles providing fast execution of RISC-coded programs. All the UT1750AR’s processing capabilities in the RISC mode are available to the system programmer by using the companion RISC Assembler (RASM)/Linker (RLNK), RISC Interactive Software Simulator (IRSIM), and hardware development debug tools.

In the MIL-STD-1750A mode of operation (M1750 = 1), the UT1750AR has a Von Neumann architecture. A processor with a Von Neumann architecture has a common set of address and data busses that make instructions and operand data available to the processor.

The UT1750AR emulates the MIL-STD-1750A instruction set when it has a specially programmed set of RISC PROMs. These PROMs contain RISC-coded macros that correspond to each MIL-STD-1750 instruction. When the UT1750AR fetches a 1750 instruction from memory, it decodes this instruction’s opcode and generates an address for the RISC PROMs. This address points to a RISC macro that, when executed, performs the operation the 1750 instruction requires.

The high execution rate of the UT1750AR’s native RISC language is also available when the UT1750AR is in the MIL- STD-1750 mode of operation by using the MIL-STD-1750 Built-in-Function (BIF) opcode. The system designer can develop a RISC macro for a specific function, such as poweron self-test routines, built-in-test routines, signal-processing routines, or any routine that requires real-time processing. The UT1750AR executes this function when it encounters the BIF in the MIL-STD-1750 program flow.

The RISC Mode of Operation

The configuration for the UT1750AR in the RISC mode of operation is shown in figure 4. RISC is the default mode of operation for the UT1750AR since the M1750 input is tied to an internal pull-down resistor.

When the UT1750AR operates in the RISC mode, the system designer stores the executable RISC program in RISC memory. The UTMC RISC Assembler generates this executable RISC program. All 20 of the RISC address lines can access a userdefined program in RISC memory. This means the maximum length of any RISC program is 1 megaword.

Although the executable RISC program is all that is stored in RISC memory, two RISC instructions allow the programmer to manipulate the data in RISC memory. These instructions are the Load Register from (RISC) Instruction Memory (LRI) and the Store Register to (RISC) Instruction Memory (STRI).

When operating in the RISC mode, the UT1750AR first generates an address on the RISC address bus for the instruction it stores in the Primary Instruction Register (PIR). After the UT1750AR stores the RISC instruction in the PIR, the UT1750AR begins executing the instruction in the Instruction Register (IR). If the present instruction in the IR requires only internal processing, the UT1750AR does not exercise the Operand Address and data busses. If, on the other hand, the instruction in the IR requires some type of Operand Data, the UT1750AR begins an Operand bus arbitration cycle midway through the next processor clock cycle.

The Operand bus arbitration cycle begins with the UT1750AR asserting the Bus Request (BRQ) signal. The UT1750AR samples the Bus Grant (BGNT) and the Bus Busy (BUSY) signals on every falling edge of the processor clock. When the UT1750AR detects that the previous bus controller has relinquished control of the bus, the UT1750AR generates the Bus Grant Acknowledge ( BGACK) signal signifying that it has taken control of the bus.

After the UT1750AR has taken control of the bus, it generates the Operand address and data. The Address Strobe (AS) and Data Strobe (DS) signals indicate when the Operand address and data are valid. If the UT1750AR is interfacing to slow memory or other peripheral devices that require long memoryaccess times, the Data Transfer Acknowledge (DTACK) signal extends the memory cycle time. By holding off the assertion of DTACK, the slow memory device lengthens the memory cycle until it can provide data for the UT1750AR.

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

RISC INSTRUCTION MEMORY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CAN ONLY BE ACCESSED

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BY THE UT1750AR

 

 

 

 

BRQ

 

 

 

 

 

 

 

 

 

 

BUS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BGNT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ARBITER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUSY

 

 

 

 

 

 

 

 

 

 

RISC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RISC

 

BGACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MEMORY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1M X 16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RISC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(MAX)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADD

 

OP ADD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

OP DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTERNALLY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M1750

 

 

 

 

 

 

GENERAL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PULLED LOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PURPOSE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USER-

 

 

 

 

 

UT1750AR

 

 

 

 

MEMORY

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEFINED

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYSTEM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTERRUPTS

 

 

 

 

 

 

 

UART

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/F

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DMA

 

DMA

DEVICE

 

DEVICE

#1

 

#2

1553

 

 

I/F

 

 

 

 

 

16

16

6

I/O

 

I/O

DEVICE #1

 

DEVICE #2

 

 

 

SERIAL I/O

Figure 4. The UT1750AR in the RISC Mode of Operation

All user-definable interrupts are available when the UT1750AR is operating as a RISC. In addition, the system programmer can read or write to virtually all of the UT1750AR’s internal registers, either general purpose or specialized, when the UT1750AR is in the RISC mode by using the Internal I/O command (INR) or the Output Register command (OTR), respectively.

The 1750A Mode of Operation

The configuration for the UT1750AR in the MIL-STD-1750A mode of operation is shown in figure 5. The UT1750AR enters the 1750 mode of operation when the mode input, M1750, is pulled high.

The functional operation of the UT1750AR in the MIL-STD- 1750 mode is similar to the RISC mode of operation, although it has two important differences. The first difference is that when the system designer selects the MIL-STD-1750 mode, the UT1750AR requires a specific set of RISC PROMs specially programmed to allow the UT1750AR to emulate the 1750 ISA.

This special set of RISC PROMs contains a set of RISC-coded macros that allow the UT1750AR to serve as a full-feature MIL- STD-1750A microprocessor. In this respect, the RISC PROMs hold external microcode, or “Mili”-code. This “Mili”-code tells the UT1750AR how to function as a 1750 processor and, if necessary, the user can change the “Mili”-code if the application requires additional capability for real-time processing.

The second difference between the operation of the UT1750AR in the 1750 mode and the RISC mode is that in the 1750 mode the RISC address bus is limited to 16 address lines or 64K words instead of the UT1750AR’s 20-bit RISC address bus in the RISC mode. When in the 1750 mode, the UT1750AR uses the four most significant bits of the RISC address bus for output discretes. The output discrete that replaces the most significant address bit (RA19) is a dedicated chip select.

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTAINS RISC MACROS TO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMULATE THE MIL-STD-1750A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISA

 

 

 

 

 

 

 

BRQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DMA

 

 

 

 

DMA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS

 

 

 

 

DEVICE

 

 

 

DEVICE

 

 

 

 

 

 

 

 

 

 

 

 

 

BGNT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

#1

 

 

 

 

 

 

#2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ARBITER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUSY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1553

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RISC

BGACK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1750

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMULATION

 

 

 

 

 

 

DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ROM

 

 

 

 

 

 

RISC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(8K X 16)

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADD

OP ADD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OP DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

+5V

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M1750

 

 

 

 

 

 

1750

 

 

 

 

 

 

 

 

 

 

I/O

 

 

 

 

 

 

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PROGRAM/DATA

 

 

 

 

DEVICE #1

 

 

 

 

DEVICE #2

 

USER-

 

 

 

 

 

 

UT1750AR

 

 

 

 

 

MEMORY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEFINED

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYSTEM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTERRUPTS

 

 

 

 

 

 

 

UART

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

MIL-STD-1750

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/F

 

 

 

 

 

C

 

 

 

 

 

 

PROGRAMMER’S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONSOLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5. The UT1750AR in the MIL-STD-1750 Mode of Operation

 

 

 

 

 

 

 

 

 

 

 

 

The next three RISC address bits (RA16-RA18) are userdefinable discrete outputs. These outputs are defined as:

RA16/OD3 DMA enable ( DMAEN) RA17/OD2 power-up ( GOOD)

RA18/OD1 start-up ROM enable ( SUREN) After reset these signals will be in the following states: RA16 1, RA17 0, RA18 0.

When the UT1750AR operates in the MIL-STD-1750 mode, it generates an address on the Operand address bus for the next 1750 instruction. If the UT1750AR has just been initialized or has just been reset, the first memory location placed on the Operand Address Bus is 0000H; this instruction is the first one fetched from the 1750 memory. After this instruction is fetched and entered into the UT1750AR, the UT1750AR uses the opcode to “map” or point to a specific address in the RISC memory. Since the RISC PROM programming provides 1750 emulation capability, this address in RISC memory contains a specific RISC-coded macro allowing the UT1750AR to perform the requisite 1750 function.

When the UT1750AR begins executing this RISC macro for 1750 emulation, the UT1750AR begins to operate as if it were in the RISC mode (see the previous section on RISC mode of operation). The processor cycles of all the RISC instructions

that make up the particular macro are executed as if the UT1750AR were operating purely as a RISC.

During RISC macro execution for the MIL-STD-1750 instruction, the internal registers of the UT1750AR hold the intermediate results from the execution of the RISC instructions. When the macro is complete, the UT1750AR’s registers contain the data the MIL-STD-1750A instruction requires.

If the UT1750AR receives an interrupt during RISC macro execution, the RISC macro completes execution before the UT1750AR recognizes the interrupt. This is similar to completing a single 1750 instruction rather than allowing its interruption. The only exception is with the multiple-word MOV 1750 instruction. For this instruction, the UT1750AR interrupts macro execution after transferring the current word.

After the RISC macro is complete, all the UT1750AR’s internal registers, including the status registers and/or memory locations, contain the results of the MIL-STD-1750A instruction that has just completed execution. The UT1750AR now fetches the next 1750 instruction from Operand memory and the process repeats.

13

The advanced architecture of the UT1750AR allows the system designer to define RISC macros accessible through the MIL- STD-1750A Built-In Function (BIF) opcode. These userdefined RISC macros can be any regularly-used function requiring the UT1750AR’s high-speed, real-time processing capabilities. The UT1750AR fetches the BIF instruction from Operand memory just like any other 1750 instruction; it then decodes the BIF. The resulting UT1750AR-generated RISC address points to the location of the user-defined macro in RISC memory. RISC macro execution proceeds just as it would for any other 1750 instruction. MIL-STD-1750A permits the system designer to define up to 256 BIF variations.

REGISTER ARCHITECTURE

The UT1750AR has a register-oriented architecture (figure 1). The registers within the UT1750AR fall into two categories: general purpose registers, and specialized registers. All the UT1750AR’s registers are accessible to the programmer through the RISC instruction set. The programmer uses data from these registers to perform arithmetic and logical functions, alter program flow, detect various system and processor faults, determine processor status, provide control for UART and timer functions, and provide interrupt processing and exception- handling control.

16 BITS

16 BITS

CONCATENATED 32-BIT

REGISTER PAIR

 

 

R0

R1

XR0

R2

R3

XR2

R4

R5

XR4

R6

R7

XR6

R8

R9

XR8

R10

R11

XR10

R12

R13

XR12

R14

R15

XR14

R16

R17

XR16

R18

R19

XR18

 

 

 

ACCUMULATOR

ACC

 

 

 

Figure 6. General Register Set

General Purpose Registers

Figure 6 shows the UT1750AR’s 20 general purpose registers. All RISC instructions use these registers; any register or register pair can be either the source or the destination for any RISC instruction. The UT1750AR normally accesses these registers as single-word 16-bit registers although the UT1750AR can

concatenate these registers into 32-bit double-word register pairs. When the programmer uses the general purpose registers as a double-word register pair, the most significant 16 bits of the 32-bit words are stored in the even-numbered register of the register pair. For instance, if a 32-bit word is stored in Register Pair XR6, the most significant word is stored in register R6 and the least significant word is stored in register R7.

In addition to the 20 general purpose registers, the UT1750AR has a 32-bit Accumulator (ACC). The ACC is normally a destination register, although under certain circumstances it can be the source register. The Accumulator retains the most significant half of the product during a multiply instruction or the remainder during a divide operation.

Specialized Registers

The UT1750AR has 16 special purpose registers (figures 7 through 24). The values in the brackets indicate the power-up condition. They are:

1.Stack Pointer Register (SP) [XXXX16]

2.System Status Register (STATUS)

3.UART Receiver Buffer Register (RCVR) [XX0016]

4.UART Transmitter Buffer Register (TXMT) [XX0016]

5.Pending Interrupt Register (PI) [000016]

6.Fault Register (FT) [000016]

7.Interrupt Mask Register (MK) [XXXX16]

8.1750 Status Register (SW) [000016]

9.RISC Instruction Counter Register (IC) [0000016]

10.RISC Instruction Counter Save Register (ICS) [XXXXX16]

11.RISC Instruction Register (IR) [000016]

12.1750 Pipeline Register (PIPE) [XXXX16]

13.1750 Program Register (PR) [XXXX16]

14.1750 Program Counter (PC) [XXXX16]

15.1750 Timer A Register (TA) [000016]

16.1750 Timer B Register (TB) [000016]

The RISC instruction set provides access to most of the special purpose registers.

The Stack Pointer Register

Figure 7. The UT1750AR uses the 16-bit Stack Pointer Register as an address pointer on Push and

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

S

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

P

1

1

 

1

1

1

1

9

8

7

6

5

4

3

 

2

1

0

5

4

 

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

MSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB

 

 

Figure 7. The Stack Pointer Register (SP)

 

 

 

14

Pop instructions. When the UT1750AR is operating in the RISC mode, it pre-increments (pops) and post-decrements (pushes) the SP. In the 1750 mode, the UT1750AR pre-increments (pops) and post-increments (pushes) the SP.

The programmer accesses the SP by using local I/O commands to Load and Store the Stack Pointer.

The System Status Register

Figure 8. The System Status Register provides additional status information on the UT1750AR’s internal signals, including the status of the internal UART. The bit definitions for STATUS are given below.

15

14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

I

M

R

O

F

P

C

T

T

D

C

P

Z

N

V

J

M

B

 

 

 

 

 

 

E

E

E

E

E

E

N

E

E

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSB

 

 

 

 

 

 

 

 

LSB

Figure 8. The System Status Register (STATUS)

Bit Definitions

All bits in the System Status Register are active high. The values in the brackets indicate the power-up state.

BIT

 

 

NUMBER

MNEMONIC

DESCRIPTION

15

C

Carry. This conditional

 

 

status is set if a carry

 

 

generated. [0]

14

P

Positive. This conditional

 

 

status is set if the result of

 

 

operation is positive. [0]

13

Z

Zero. This conditional status

is

 

set if the result of an operation

 

 

 

 

is equal to zero. [0]

12

N

Negative. This conditional

 

 

status is set if the result of an

 

 

operation is negative. [0]

11

V

Overflow. This conditional

 

 

status is set when an overflow

 

 

condition occurs. [0]

10

J

Normalized. Thisconditional

 

 

status is set as the result of a

 

 

long instruction. [0]

9

IE

Interrupts enabled. [0]

8

MME

Memory Management

 

 

enabled. [0]

7

RE

Receiver Error. This bit is the

 

 

logical OR combination of the

 

 

OE, FE, and PE status bits.

[0]

 

 

6

OE

Overrun Error. When active,

 

 

this bit indicates that at least

 

 

one data word was lost because

 

 

the Data Ready (DR is bit 0

of

 

the STATUS) signal was

 

 

 

 

active twice consecutively

 

 

without an RBR read. [0]

5

FE

Framing Error. When active,

 

 

this bit indicates a stop bit was

 

 

missing from the serial

 

 

transmission. [0]

4

PE

Parity Error. When active,

this

 

 

 

 

bit indicates the serial

 

 

transmission was received

with

 

 

 

 

the incorrect parity. [0]

3

CN

MIL-STD-1750A Console

 

 

Enabled. When active, this bit

 

 

indicates the CONSOLE

 

 

discrete input is active.

 

 

CONSOLE active sets bit 3 in

the

 

 

 

 

System Status Register.

2

TBE

UART Transmitter Buffer

 

 

Empty. This bit indicates the

 

 

Transmitter Buffer Register is

 

 

empty and ready for data. [0]

1

TE

UART Transmitter Empty.

 

 

This bit is low while the

 

 

UART is transmitting data and

 

 

goes high when the

 

 

transmission is complete. [0]

0

DR

UART Data Ready. This

 

 

active-high signal indicates

the

 

 

 

 

UART received a serial data

 

 

word and this data is

 

 

available. [0]

15

UART Receiver Register (RCVR)

The UART Receiver Buffer Register (see figure 9) receives 9600-baud asynchronous serial data through the UARTIN input pin on the UT1750AR. Each serial data string contains an activelow Start bit, eight Data bits, an odd Parity bit, and an activehigh Stop bit. Figure 10 shows a single serial data string.

15

14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

R

R

R

R

R

R

R

R

 

 

 

 

 

 

 

 

C

C

C

C

C

C

C

C

 

 

 

 

 

 

 

 

D

D

D

D

D

D

D

D

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

MSB

 

 

 

 

 

 

 

 

 

 

 

 

LSB

 

Figure 9. The UART Receiver

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

 

R

R

R

R

R

R

R

R

 

 

S

DATA

 

T

 

C

C

C

C

C

C

C

C

 

P

T

FLOW

 

R

 

D

D

D

D

D

D

D

D

 

A

O

 

 

 

 

 

 

T

 

0

1

2

3

4

5

6

7

 

R

P

Figure 10. UART Receiver Data String

UART Transmitter Buffer Register (TXMT)

The UT1750AR’s internal UART forms an 11-bit serial data string by combining a Start bit, the eight Data bits from the Transmitter Buffer Register (TXMT), an odd Parity bit, and a Stop bit. Figure 11 shows the composition of the serial data string.

The UT1750AR transmits this serial data string through the UARTOUT pin at a rate of 9600 baud.

DIRECTION

S

 

T

T

T

T

T

T

T

T

 

 

S

OF DATA

 

 

 

T

 

X

X

X

X

X

X

X

X

 

P

T

FLOW OUT

 

 

OF THE

R

 

D

D

D

D

D

D

D

D

 

A

O

UT1750AR

 

 

T

 

0

1

2

3

4

5

6

7

 

R

P

 

 

 

Figure 11. UART Transmitter Data String

Two status signals are associated with transmitting serial data. These signals are the UART Transmitter Buffer Empty (TBE) and UART Transmitter Register Empty (TE). TBE and TE are both active high and provide information on the status of double buffering the UART’s transmitted data. TBE and TE are read from the System Status Register as bits 2 and 1, respectively.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The UT1750AR’s internal UART has a double-buffered data

While receiving a serial data string, the UT1750AR generates

 

transmission scheme (figure 12). The UT1750AR first loads the

four status flags: Data Ready (DR); Overrun Error (OE);

 

 

 

data for transmission into the Transmitter Buffer Register. If the

Framing Error (FE); and Parity Error (PE). The UT1750AR

 

UART Transmitter Register is empty, data from the TXMT

 

 

 

 

 

 

 

 

THE UT1750AR’S INTERNAL

 

 

 

 

 

 

 

 

 

 

 

stores these status bits in the System Status Register (STATUS).

 

automatically transfers to the UART Transmitter Register. At

 

 

 

 

 

 

 

 

 

 

 

 

DATA BUS

 

this time, the TBE bit goes active indicating more data may be

Receiver buffer register bits 15-8 are always low. Bit

numbers

 

loaded into the TXMT. This double-buffering scheme allows

7-0 (RCD7-RCD0) contain data the UT1750AR receiv

es via the

 

contiguous transmission of serial data streams and also

 

UART TRANSMITTER BUFFER

 

 

 

16

 

 

 

 

REGISTER (TBR)

 

 

 

 

 

 

 

 

 

decreases the UT1750AR’s requiredSTATUSoverheadOFfor THEthe UART

serial data port. RCD7 is the MSB; RCD0 is the LSB.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

T

interfaceT T.

 

T

T

T

T

TBR IS READ

 

D

D

D

 

D

 

D

 

D

 

D

 

D

 

 

 

FROM BIT 2

 

 

 

 

 

 

 

X

 

X

X

X

 

X

X

X

X

 

C

C

C

 

C

 

C

 

C

 

C

 

C

 

D

 

D

D

D

 

D

D

D

D

OF THE SYSTEM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

6

5

4

 

3

2

1

0

STATUS REGISTER

DATA IS LOADED INTO THE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TBR WITH AN OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REGISTER (OTR) INSTRUCTION

 

 

UART TRANSMITTER

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REGISTER

 

 

 

 

 

 

 

 

 

 

 

STATUS OF THE UART

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

 

P

 

T

 

T

T

T

 

T

T

T

T

S

 

 

 

TRANSMITTER REGISTER IS

 

 

 

 

 

 

 

 

 

 

 

 

 

READ FROM BIT 1

 

 

 

 

 

 

T

A

X

X

X

X

 

X

X

X

X

T

 

 

 

OF THE SYSTEM STATUS

 

 

O

R

7

6

5

4

 

3

2

1

0

R

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

DIRECTION OF

REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA FLOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 12. The UT1750AR UART Double-Buffered Transmitter Register

 

 

16

The UT1750AR loads the eight bits of serial data into the lower eight bits of the TXMT (figure 13).

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

T

T

T

T

T

T

T

T

D

D

D

D

D

D

D

D

X

X

X

X

X

X

X

X

C

C

C

C

C

C

C

C

D

D

D

D

D

D

D

D

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MSB

LSB

DC = Don’t Care

 

Figure 13. The UART Transmitter

 

The Pending Interrupt Register (PI)

The Pending Interrupt Register (PI) contains information on pending interrupts attempting to vector the Instruction Counter Register (IC) to a new location. Software or hardware controls the PI. Any system interrupt, when active, sets the corresponding bit in the PI. RISC I/O instructions can also set, clear, and read the PI (figure 14).

15

14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

M

I

F

F

E

F

T

I

T

I

I

I

I

I

I

W

C

N

L

I

X

L

I

N

I

N

N

O

N

O

N

D

H

T

P

P

C

P

M

T

M

T

T

L

T

L

T

N

E

O

O

O

L

U

A

1

B

2

3

1

4

2

5

MSB

 

 

 

 

 

 

 

 

LSB

Figure 14. The Pending Interrupt Register (PI)

The Fault Register (FT)

The UT1750AR uses the Fault Register (FT) (figure 15) to indicate the occurrence of a machine-error fault. A machineerror fault cannot be disabled. The UT1750AR uses the logical OR combination of the 16 FT bits to generate the Machine Error interrupt, bit 14 of the PI. Any bits in the FT the UT1750AR does not use are set to a logic zero. The UT1750AR reads, loads, and clears the FT with RISC I/O instructions. The configuration of the FT is shown in figure 15.

15

14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

S

ILLEGAL

 

R

BUILT-

MEM

PARITY

I/O

 

Y

INSTRUC-

E

 

IN-

 

 

TION AND

 

TEST

 

PROT

 

 

 

F

ADD FAULT

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

 

 

 

 

 

 

MSB

 

 

 

 

 

 

 

 

LSB

 

 

Figure 15. The Fault Register (FT)

 

 

 

Bit Definitions

All bits in the Fault Register are active when high.

BIT

 

 

NUMBER

MNEMONIC

DESCRIPTION

15

CMPF

CPU Memory Protect Fault.

 

 

This bit indicates the

 

 

UT1750AR has detected an

 

 

access fault, write-protect

 

 

fault, or an execute-protect

 

 

fault. [0]

14

DMPF

DMA Memory Protect Fault.

 

 

This bit indicates a DMA

 

 

device has detected an access

 

 

fault or a write-protect fault.

 

 

[0]

13

MPF

Memory Parity Fault. [0]

12

PCPF

Parallel I/O (PIO) Channel

 

 

Parity Fault. [0] No user

 

 

access.

11

DCPF

DMA Channel Parity Fault.

 

 

[0] No user access.

10

ICF

Illegal Command Fault. This

 

 

bit indicates an attempt to

 

 

execute an unimplemented or

 

 

reserved I/O command. [0]

9

PTF

PIO Transmission Fault. Can

 

 

wire-OR I/O error-checking

 

 

devices together and feed

them

 

 

 

 

into this input to indicate an

 

 

error. [0] No user access.

8

SYSFLT

System Fault. [0]

7

IAF

Illegal Address Fault. This bit

 

 

indicates addressing a memory

 

 

location not physically

 

 

present. [0]

6

IIF

Illegal Instruction Fault. This

 

 

bit indicates an attempt to

17

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