UC3714DP
application
INFO
available
UC1714/5
UC2714/5
UC3714/5
Complementary Switch FET Drivers
FEATURES
•Single Input (PWM and TTL Compatible)
•High Current Power FET Driver, 1.0A Source/2A Sink
•Auxiliary Output FET Driver, 0.5A Source/1A Sink
•Time Delays Between Power and Auxiliary Outputs Independently Programmable from 50ns to 500ns
•Time Delay or True Zero-Voltage Operation Independently Configurable for Each Output
•Switching Frequency to 1MHz
•Typical 50ns Propagation Delays
•ENBL Pin Activates 220 A Sleep Mode
•Power Output is Active Low in Sleep Mode
DESCRIPTION
These two families of high speed drivers are designed to provide drive waveforms for complementary switches. Complementary switch configurations are commonly used in synchronous rectification circuits and active clamp/reset circuits, which can provide zero voltage switching. In order to facilitate the soft switching transitions, independently programmable delays between the two output waveforms are provided on these drivers. The delay pins also have true zero voltage sensing capability which allows immediate activation of the corresponding switch when zero voltage is applied. These devices require a PWM-type input to operate and can be interfaced with commonly available PWM controllers.
In the UC1714 series, the AUX output is inverted to allow driving a p-channel MOSFET. In the UC1715 series, the two outputs are configured in a true complementary fashion.
• Synchronous Rectifier Driver
BLOCK DIAGRAM
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50ns –500ns |
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2 |
PWR |
INPUT |
6 |
TIMER |
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Q |
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T1 |
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R |
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UC1714 |
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VREF |
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ONLY |
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50ns –500ns |
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4 |
AUX |
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TIMER |
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1 |
VCC |
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S |
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Q |
VCC |
5V |
LOGIC |
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T2 |
5 |
R |
BIAS |
GATES |
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VREF |
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ENBL |
3V |
TIMER |
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GND |
REF |
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3 |
GND |
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1.4V |
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ENBL |
8 |
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ENABLE |
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J, N and D packages.
UDG-99028
1999 - REVISED JANUARY 2002
UC1714/5
UC2714/5
UC3714/5
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Power Driver IOH
continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −200mA peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1A
Power Driver IOL
continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2A
Auxiliary Driver IOH
continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −100mA peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −500mA
Auxiliary Driver IOL
continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
CONNECTION DIAGRAMS
Input Voltage Range (INPUT, ENBL) . . . . . . . . . . −0.3V to 20V Storage Temperature Range . . . . . . . . . . . . . . −65°C to 150°C Operating Junction Temperature (Note 1) . . . . . . . . . . . . 150°C Lead Temperature (Soldering 10 seconds) . . . . . . . . . . . 300°C
Note 1: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals.
Note 2: Consult Packaging Section of databook for thermal limitations and specifications of packages.
DIL-8, SOIC-8 (Top View) |
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SOIC-16 (Top View) |
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J or N, D Packages |
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DP Package |
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ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 15V, ENBL ≥ 2V, RT1 = 100kΩ from T1 to GND, RT2 = 100kΩ from T2 to GND, and −55°C < TA < 125°C for the UC1714/5, −40°C < TA < 85°C for the UC2714/5, and 0°C < TA < 70°C for the UC3714/5, TA = TJ.
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
Overall |
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VCC |
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7 |
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20 |
V |
ICC, nominal |
ENBL = 2.0V |
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18 |
24 |
mA |
ICC, sleep mode |
ENBL = 0.8V |
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200 |
300 |
µA |
Power Driver (PWR) |
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Pre Turn-on PWR Output, Low |
VCC = 0V, IOUT = 10mA, ENBL 0.8V |
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0.3 |
1.6 |
V |
PWR Output Low, Sat. (VPWR) |
INPUT = 0.8V, IOUT = 40mA |
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0.3 |
0.8 |
V |
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INPUT = 0.8V, IOUT = 400mA |
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2.1 |
2.8 |
V |
PWR Output High, Sat. (VCC − VPWR) |
INPUT = 2.0V, IOUT = −20mA |
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2.1 |
3 |
V |
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INPUT = 2.0V, IOUT = −200mA |
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2.3 |
3 |
V |
Rise Time |
CL = 2200pF |
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30 |
60 |
ns |
Fall Time |
CL = 2200pF |
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25 |
60 |
ns |
T1 Delay, AUX to PWR |
INPUT rising edge, RT1 = 10kΩ (Note 4) |
20 |
35 |
80 |
ns |
T1 Delay, AUX to PWR |
INPUT rising edge, RT1 = 100kΩ (Note 4) |
350 |
500 |
700 |
ns |
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INPUT falling edge, 50% (Note 3) |
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35 |
100 |
ns |
2
UC1714/5
UC2714/5
UC3714/5
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 15V, ENBL ≥ 2V, RT1 = 100kΩ from T1 to GND, RT2 = 100kΩ from T2 to GND, and −55°C < TA < 125°C for the UC1714/5, −40°C < TA < 85°C for the UC2714/5, and 0°C < TA < 70°C for the UC3714/5, TA = TJ.
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNITS |
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Auxiliary Driver (AUX) |
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AUX Output Low, Sat |
(VAUX) |
VIN = 2.0V, IOUT = 20mA |
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0.3 |
0.8 |
V |
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VIN = 2.0V, IOUT = 200mA |
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1.8 |
2.6 |
V |
AUX Output High, Sat |
(VCC – VAUX) |
VIN = 0.8V, IOUT = -10mA |
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2.1 |
3.0 |
V |
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VIN = 0.8V, IOUT = -100mA |
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2.3 |
3.0 |
V |
Rise Time |
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CL = 1000pF |
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45 |
60 |
ns |
Fall Time |
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CL = 1000pF |
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30 |
60 |
ns |
T2 Delay, PWR to AUX |
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INPUT falling edge, RT2 = 10kΩ (Note 4) |
20 |
50 |
80 |
ns |
T2 Delay, PWR to AUX |
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INPUT falling edge, RT2 = 100kΩ (Note 4) |
250 |
350 |
550 |
ns |
AUX Prop Delay |
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INPUT rising edge, 50% (Note 3) |
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35 |
80 |
ns |
Enable (ENBL) |
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Input Threshold |
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0.8 |
1.2 |
2.0 |
V |
Input Current, IIH |
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ENBL = 15V |
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1 |
10 |
µA |
Input Current, IIL |
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ENBL = 0V |
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−1 |
−10 |
µA |
T1 |
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Current Limit |
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T1 = 0V |
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−1.6 |
−2 |
mA |
Nominal Voltage at T1 |
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2.7 |
3 |
3.3 |
V |
Minimum T1 Delay |
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T1 = 2.5V, (Note 4) |
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40 |
70 |
ns |
T2 |
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Current Limit |
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T2 = 0V |
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−1.2 |
−2 |
mA |
Nominal Voltage at T2 |
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2.7 |
3 |
3.3 |
V |
Minumum T2 Delay |
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T2 = 2.5V, (Note 4) |
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50 |
100 |
ns |
Input (INPUT) |
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Input Threshold |
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0.8 |
1.4 |
2.0 |
V |
Input Current, IIH |
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INPUT = 15V |
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1 |
10 |
µA |
Input Current, IIL |
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INPUT = 0V |
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−5 |
−20 |
µA |
Note 3: Propagation delay times are measured from the 50% point of the input signal to the 10% point of the output signal’s transition with no load on outputs.
Note 4: T1 delay is defined from the 50% point of the transition edge of AUX to the 10% of the rising edge of PWR. T2 delay is defined from the 90% of the falling edge of PWR to the 50% point of the transition edge of AUX.
PIN DESCRIPTIONS
AUX: The AUX switches immediately at INPUT’s rising edge but waits through the T2 delay after INPUT’s falling edge before switching. AUX is capable of sourcing 0.5A and sinking 1.0A of drive current. See the Time Relationships diagram below for the difference between the UC1714 and UC1715 for INPUT, MAIN, and AUX. During sleep mode, AUX is inactive with a high impedance.
switches at TTL logic levels (apinput range is from 0V to 20V.
The ENBL input will place the device into sleep mode when it is a logical low. The current into VCC during the sleep mode is typically 220 A.
GND: This is the reference pin for all input voltages and the return point for all device currents. It carries the full peak sinking current from the outputs. Any tendency for the outputs to ring below GND voltage must be damped or clamped such that GND remains the most negative potential.
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