UNITRODE UC1525A, UC1527A, UC2525A, UC2527A, UC3525A Technical data

UC2527AQTR

UC1525A/27A

UC2525A/27A

UC3525A/27A

Regulating Pulse Width Modulators

FEATURES

∙8 to 35V Operation

∙5.1V Reference Trimmed to

±1%

∙100Hz to 500kHz Oscillator Range

∙Separate Oscillator Sync Terminal

∙Adjustable Deadtime Control

∙Internal Soft-Start

∙Pulse-by-Pulse Shutdown

∙Input Undervoltage Lockout with Hysteresis

∙Latching PWM to Prevent Multiple Pulses

∙Dual Source/Sink Output Drivers

DESCRIPTION

The UC1525A/1527A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip +5.1V reference is trimmed to ±1% and the input common-mode range of the error amplifier includes the reference voltage, eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provides a wide range of dead-time adjustment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200mA. The UC1525A output stage features NOR logic, giving a LOW output for an OFF state. The UC1527A utilizes OR logic which results in a HIGH output level when OFF.

BLOCK DIAGRAM

2/96

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage, (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Collector Supply Voltage (VC) . . . . . . . . . . . . . . . . . . . . . . +40V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN Output Current, Source or Sink . . . . . . . . . . . . . . . . . . . 500mA Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . . 50mA Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . 5mA Power Dissipation at TA = +25°C (Note 2) . . . . . . . . . . 1000mW Power Dissipation at TC = +25°C (Note 2) . . . . . . . . . . 2000mW Operating Junction Temperature . . . . . . . . . . . -55°C to +150°C Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 seconds). . . . . . . . . . +300°C

Note 1: Values beyond which damage may occur.

Note 2: Consult packaging Section of Databook for thermal limitations and considerations of package.

CONNECTION DIAGRAMS

DIL-16 (TOP VIEW)

J or N Package

UC1525A/27A

UC2525A/27A

UC3525A/27A

RECOMMENDED OPERATING CONDITIONS

(Note 3)

Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . +8V to +35V Collector Supply Voltage (VC) . . . . . . . . . . . . . . +4.5V to +35V Sink/Source Load Current (steady state) . . . . . . . . 0 to 100mA Sink/Source Load Current (peak) . . . . . . . . . . . . . . 0 to 400mA Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA Oscillator Frequency Range . . . . . . . . . . . . . . 100Hz to 400kHz Oscillator Timing Resistor. . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ Oscillator Timing Capacitor. . . . . . . . . . . . . . . . .001μF to 0.1μF Dead Time Resistor Range . . . . . . . . . . . . . . . . . . . . 0 to 500Ω Operating Ambient Temperature Range

UC1525A, UC1527A . . . . . . . . . . . . . . . . . . -55°C to +125°C UC2525A, UC2527A . . . . . . . . . . . . . . . . . . . -25°C to +85°C UC3525A, UC3527A . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Note 3: Range over which the device is functional and parameter limits are guaranteed.

PLCC-20, LCC-20 (TOP VIEW)

Q, L Package

PACKAGE PIN FUNCTION

FUNCTION	PIN
N/C	1
Inv. Input	2
N.I. Input	3
SYNC	4
OSC. output	5
N/C	6
CT	7
RT	8
Discharge	9
Softstart	10
N/C	11
Compensation	12
Shutdown	13
Output A	14
Ground	15
N/C	16
VC	17
Output B	18
+VIN	19
VREF	20

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UC1525A/27A

UC2525A/27A

UC3525A/27A

ELECTRICAL CHARACTERISTICS: +VIN = 20V, and over operating temperature, unless otherwise specified, TA = TJ

		UC1525A/UC2525A				UC3525A				UNITS
PARAMETER	TEST CONDITIONS	UC1527A/UC2527A				UC3527A
		MIN	TYP	MAX	MIN		TYP	MAX
Reference Section
Output Voltage	TJ = 25°C	5.05	5.10	5.15	5.00		5.10		5.20	V
Line Regulation	VIN = 8 to 35V		10	20			10		20	mV
Load Regulation	IL = 0 to 20mA		20	50			20		50	mV
Temperature Stability (Note 5)	Over Operating Range		20	50			20		50
Total Output Variation (Note 5)	Line, Load, and Temperature	5.00		5.20	4.95				5.25	V
Shorter Circuit Current	VREF = 0, TJ = 25°C		80	100			80		100	mA
Output Noise Voltage (Note 5)	10Hz ≤ 10kHz, TJ = 25°C		40	200			40		200	μVrms
Long Term Stability (Note 5)	TJ = 125°C		20	50			20		50	mV
Oscillator Section (Note 6)
Initial Accuracy (Notes 5 & 6)	TJ = 25°C		± 2	± 6			± 2		± 6	%
Voltage Stability (Notes 5 & 6)	VIN = 8 to 35V		± 0.3	± 1			± 1		± 2	%
Temperature Stability (Note 5)	Over Operating Range		± 3	± 6			± 3		± 6	%
Minimum Frequency	RT = 200kW, CT = 0.1mF			120					120	Hz
Maximum Frequency	RT = 2kW, CT = 470pF	400			400					kHz
Current Mirror	IRT = 2mA	1.7	2.0	2.2	1.7		2.0		2.2	mA
Clock Amplitude (Notes 5 & 6)		3.0	3.5		3.0		3.5			V
Clock Width (Notes 5 & 6)	TJ = 25°C	0.3	0.5	1.0	0.3		0.5		1.0	μs
Sync Threshold		1.2	2.0	2.8	1.2		2.0		2.8	V
Sync Input Current	Sync Voltage = 3.5V		1.0	2.5			1.0		2.5	mA
Error Amplifier Section (VCM = 5.1V)
Input Offset Voltage			0.5	5			2		10	mV
Input Bias Current			1	10			1		10	μA
Input Offset Current				1					1	μA
DC Open Loop Gain	RL ³ 10MW	60	75		60		75			dB
Gain-Bandwidth Product	AV = 0dB, TJ = 25°C	1	2		1		2			MHz
(Note 5)
DC Transconductance	TJ = 25°C, 30kW £ RL £ 1MW	1.1	1.5		1.1		1.5			mS
(Notes 5 & 7)
Output Low Level			0.2	0.5			0.2		0.5	V
Output High Level		3.8	5.6		3.8		5.6			V
Common Mode Rejection	VCM = 1.5 to 5.2V	60	75		60		75			dB
Supply Voltage Rejection	VIN = 8 to 35V	50	60		50		60			dB

Note 5: These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production. Note 6: Tested at fOSC = 40kHz (RT = 3.6kΩ, CT = 0.01μF, RD = 0Ω). Approximate oscillator frequency is defined by:

f = 1

CT (0.7RT + 3RD)

Note 7: DC transconductance (gM) relates to DC open-loop voltage gain (AV) according to the following equation: AV = gMRL where RL is the resistance from pin 9 to ground..

The minimum gM specification is used to calculate minimum AV when the error amplifier output is loaded.

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