4-Bit Bidirectional Voltage-Level Translator for Open-Drain and
Push-Pull Application
UM3204 CSP12 1.9 X1.4
QFN143.5 X3.5
General Description
The UM3204 is ±15kV quad channel ESD-protected level translator provide the level shifting
necessary to allow data transfer in a multi-voltage system. Externally applied voltages, V
V
, set the logic levels on either side of the device. A low-voltage logic signal present on the
CCA
V
side of the device appears as a high-voltage logic signal on the V
CCA
side of the device, and
CCB
CCB
and
vice-versa. The UM3204 bidirectional level translator utilizes a transmission-gate based design to
allow data translation in either direction (V
accepts V
from +1.65V to +3.6V and V
CCA
CCA↔VCCB
from +2.3V to +5.5V, making it ideal for data
CCB
) on any single data line. The UM3204
transfer between low-voltage ASICs / PLDs and higher voltage systems.
The UM3204 enters a three-state output mode to reduce supply current when output enable (OE)
is low. The UM3204 is designed so that the OE input circuit is supplied by V
protection on the V
side for greater protection in applications that route signals externally. The
CCB
. ±15kV ESD
CCA
UM3204 is a quad level translator available in 1.9 x 1.4 CSP12 and 3.5 x 3.5 QFN14 package.
Applications
z SPI, MICROWIRE, and I2C Level
Translation
z Low-Voltage ASIC Level Translation
z Smart Card Readers
z Cell-phone Cradles
z Portable POS Systems
z Portable Communication Devices
z Low-Cost Serial Interfaces
z Cell-Phones
z GPS
Features
z Max Data Rates:
24Mbps(Push Pull),
2Mbps(Open Drain)
z Bidirectional Level Translation
z 1.65V to 3.6V on A port and 2.3V to 5.5V
on B port(V
z ±15kV ESD Protection on B port
z No Power-Supply Sequencing Required
A1 Input/Output 1. Referenced to V
A2 Input/Output 2. Referenced to V
A3 Input/Output 3. Referenced to V
A4 Input/Output 4. Referenced to V
GND Ground
OE
3-state output enable. Pull OE low to place all outputs in 3-state mode.
Referenced to V
CCA
B4 Input/Output 4. Referenced to V
B3 Input/Output 3. Referenced to V
B2 Input/Output 2. Referenced to V
B1 Input/Output 1. Referenced to V
V
B-Port supply voltage. 2.3V≤V
CCB
Ordering Information
Part NumberPackaging TypeMarking Code Shipping Qty
UM3204H
UM3204Q
CSP12 1.9×1.4
QFN14 3.5×3.5
Absolute Maximum Ratings (Note 1)
Over operating free-air temperature range (unless otherwise noted)
Symbol Parameter Value Unit
V
Supply Voltage Range -0.5 to +4.5 V
CCA
V
Supply Voltage Range -0.5 to +6.5 V
CCB
VI Input Voltage Range
VO
VO
IIK Input Clamp Current
IOK Output Clamp Current
IO Continuous Output Current ±50 mA
Continuous Current through V
TOP Operating Temperature Range -40 to +85 °C
T
STG
Voltage Range applied to any output in
the high-impedance or power-off state
Voltage Range applied to any output in
the high or low state (Note 2)
CCA
Storage Temperature Range -65 to +150 °C
≤3.6V and V
CCA
CCA
CCA
CCA
CCA
CCB
CCB
CCB
CCB
≤5.5V
CCB
CCA≤VCCB
AAB
UM3204Q
3000pcs/7Inch
Tape & Reel
3000pcs/13Inch
Tape & Reel
A ports -0.5 to +4.5
B ports -0.5 to +6.5
A ports -0.5 to +4.5
B ports -0.5 to +6.5
A ports -0.5 to ( V
B ports -0.5 to ( V
<0
V
I
<0
V
O
, V
, or GND ±100 mA
CCB
CCA
CCB
-50 mA
-50 mA
+0.5)
+0.5)
V
V
V
Note1. Stresses beyond those listed under "absolute maximum ratings" may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
Note2. The value of V
CCA
and V
are provided in the recommended operating conditions table.
The UM3204 can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The UM3204 is ideal for use in
application where an open-drain driver is connected to the data I/Os. The UM3204 can also be
used in applications where a push-pull driver is connected to the data I/Os, but the UM3304 might
be a better option for such push-pull applications.
Block Diagram
The UM3204 (block diagram see Figure 1) does not require a direction-control signal to control
the direction of data flow from A to B or from B to A. Each A-port I/O has an internal 10-kΩ
pull-up resistor to V
During a rising edge, the one-shot turns on the PMOS transistors (PU1, PU2) for a short duration,
which speeds up the low-to-high transition.
, and each B-port I/O has an internal 10-kΩ pull-up resistor to V
CCA
CCB
.
Figure 1 Block Diagram of UM3204 I/O Cell
Input Driver Requirements
The fall time (tfA, tfB) of a signal depends on the output impedance of the external device
driving the data I/Os of the UM3204. Similarly, the t
depend on the output impedance of the external driver. The values for tfA, tfB, t
and the maximum date rates also
PHL
PHL
, and the
maximum date rates in the data sheet assume that the output impedance of the external
driver is less than 50Ω.
Power Up
During operation, ensure that V
CCA≤VCCB
at all times. During power-up sequencing, V
CCA
≥ V
CCB
does not damage the device, so any power supply can be ramped up first.
Enable and Disable
The UM3204 has an OE input that is used to disable the device by setting OE = low, which places
all I/Os in the high-impedance (Hi-Z) state. The disable time (tdis) indicates the delay between the
time when OE goes low and when the outputs actually get disabled (Hi-Z). The enable time (ten)
indicates the amount of time the user must allow for the one-shot circuitry to become operational
after OE is taken high.
Each A-port I/O has an internal 10-kΩ pull-up resistor to V
internal 10-kΩ pull-up resistor to V
external resistor must be added from the I/O to V
. If a smaller value of pull-up resistor is required, an
CCB
or V
CCA
CCB
resistor).
Test Circuits
UM3204
, and each B-port I/O has an
CCA
(in parallel with the internal 10-kΩ
A. C
includes probe and jig capacitances.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by
the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by
the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤100MHz, Z
dv/dt≥1V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. T
and T
PLZ
F. T
and T
PZL
G. T
H. V
I. V
and T
PLH
is the VCC associated with the input port.
CCI
is the VCC associated with the output port.
CCO
are the same as tdis.
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
J. All parameters and waveforms are not applicable to all devices.
The information in this document has been carefully reviewed and is believed to be
accurate. Nonetheless, this document is subject to change without notice. Union assumes
no responsibility for any inaccuracies that may be contained in this document, and makes
no commitment to update or to keep current the contained information, or to notify a
person or organization of any update. Union reserves the right to make changes, at any
time, in order to improve reliability, function or design and to attempt to supply the best
product possible.