SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222B – APRIL 1999 – REVISED FEBRUARY 2000
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
I
Feature Supports Partial-Power-Down
off
Mode Operation
D
Supports 5-V V
D
Package Options Include Plastic
Operation
CC
DBV OR DCK PACKAGE
(TOP VIEW)
V
5
Y
4
GND
A
1
B
2
3
CC
Small-Outline Transistor (DBV, DCK)
Packages
description
This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true
form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
This device is fully specified for partial-power-down applications using I
preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G86 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
A B
L L L
L HH
H LH
H H L
OUTPUT
Y
off
. The I
circuitry disables the outputs,
off
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
†
1
A
2
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
=1
4
Y
Copyright 2000, Texas Instruments Incorporated
PRODUCT PREVIEW
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222B – APRIL 1999 – REVISED FEBRUARY 2000
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative
logic symbols.
EXCLUSIVE OR
= 1
These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
= 2k 2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
PRODUCT PREVIEW
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 3): DBV package 347°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DCK package 389°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCCSuppl
oltage
V
VIHHigh-level input voltage
V
VILLow-level input voltage
V
V
V
V
V
SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222B – APRIL 1999 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
p
p
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Input voltage 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.65 5.5
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × V
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × V
VCC = 1.65 V –4
VCC = 2.3 V –8
= 3
CC
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
= 3
CC
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 5
CC
CC
CC
–16
–24
16
24
10
CC
CC
V
mA
mA
ns/V
PRODUCT PREVIEW
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74LVC1G86
V
V
3 V
V
V
3 V
(INPUT)
(OUTPUT)
PARAMETER
TEST CONDITIONS
UNIT
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222B – APRIL 1999 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 5.5 V VCC–0.1
IOH = –4 mA 1.65 V 1.2
OH
OL
I
I
I
off
I
CC
∆I
CC
C
†
i
All typical values are at VCC = 3.3 V, TA = 25°C.
IOH = –8 mA 2.3 V 1.7
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA 4.5 V 3.8
IOL = 100 µA 1.65 V to 5.5 V 0.2
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.7
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA 4.5 V 0.55
VI = 5.5 V or GND 0 to 5.5 V ±5 µA
VI or VO = 5.5 V 0 ±10 µA
VI = VCC or GND, IO = 0 1.65 V to 5.5 V 10 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 µA
VI = VCC or GND 3.3 V pF
V
CC
MIN TYP†MAX UNIT
2.4
2.3
0.4
0.55
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 4)
PARAMETER
t
pd
FROM
A or B
TO
VCC = 1.8 V
± 0.15 V
MIN MAX MIN MAX MIN MAX MIN MAX
Y
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
ns
operating characteristics, T
PRODUCT PREVIEW
C
Power dissipation capacitance f = 10 MHz pF
pd
A
= 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
TYP TYP TYP TYP
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222B – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1 kΩ
1 kΩ
S1
SN74LVC1G86
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
PRODUCT PREVIEW
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222B – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
= 2.5 V ± 0.2 V
CC
2 × V
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
PRODUCT PREVIEW
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2 VCC/2
VCC/2
dis
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
V
CC
0 V
V
CC
0 V
V
CC
S1 at 2 × V
0 V
t
PHL
V
OH
V
OL
.
Input
Output
Control
Output
Waveform 1
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
VCC/2
t
PZH
VCC/2
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222B – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 3.3 V ± 0.3 V
V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
PLH
Output
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
S1
t
PHL
6 V
Open
GND
3 V
0 V
3 V
0 V
3 V
0 V
V
V
OH
OL
Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
w
1.5 V
1.5 V
Open
6 V
GND
1.5 V1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
V
V
0 V
OL
OH
PRODUCT PREVIEW
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 3. Load Circuit and Voltage Waveforms
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7
SN74LVC1G86
SINGLE 2-INPUT EXCLUSIVE-OR GATE
SCES222B – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
Input
500 Ω
500 Ω
LOAD CIRCUIT
t
w
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
S1
= 5 V ± 0.5 V
V
CC
11 V
Open
GND
V
CC
0 V
Timing Input
Data Input
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Open
11 V
GND
VCC/2
t
h
VCC/2
V
0 V
V
0 V
CC
CC
Input
t
PLH
Output
t
PHL
PRODUCT PREVIEW
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VCC/2 VCC/2
VCC/2
VOLTAGE WAVEFORMS
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
VCC/2
Figure 4. Load Circuit and Voltage Waveforms
t
PHL
t
VCC/2
.
dis
PLH
V
0 V
V
V
V
V
CC
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at 11 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2 VCC/2
t
PZL
VCC/2
t
PZH
VCC/2
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
VOL + 0.3 V
VOH – 0.3 V
t
PLZ
t
PHZ
V
CC
0 V
5.5 V
V
OL
V
OH
≈ 0 V
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 2000, Texas Instruments Incorporated
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