Texas Instruments PCI7412 (PC Card, FireWire, Memory Ctrl.) PCIxx12 Data Manual

Download

PCIxx12 Single Socket CardBus

Controller with Integrated

1394a-2000 OHCI Two-Port

PHY/Link-Layer Controller

Data Manual

Includes: PCI4512GHK, PCI4512ZHK, PCI6412GHK, PCI6412ZHK, PCI6612GHK, PCI6612ZHK,

PCI7402GHK, PCI7402ZHK, PCI7412GHK, PCI7412ZHK, PCI7612GHK, PCI7612ZHK, PCI8402GHK,

PCI8402ZHK, PCI8412GHK, PCI8412ZHK

Literature Number: SCPS110

September 2005

Printed on Recycled Pape

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.

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Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless

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Contents

Section Page

1 PCIxx12 Features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Introduction 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Controller Functional Description 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 PCI4512 Controller 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 PCI6412 Controller 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 PCI6612 Controller 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4 PCI7402 Controller 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5 PCI7412 Controller 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.6 PCI7612 Controller 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.7 PCI8402 Controller 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.8 PCI8412 Controller 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.9 Multifunctional Terminals 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.10 PCI Bus Power Management 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.11 Power Switch Interface 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Related Documents 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Trademarks 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Document Conventions 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Terms and Definitions 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Ordering Information 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 PCIxx12 Data Manual Document History 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Terminal Assignments 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Detailed Terminal Descriptions 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Principles of Operation 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Power Supply Sequencing 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 I/O Characteristics 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Clamping Voltages 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Peripheral Component Interconnect (PCI) Interface 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.1 1394 PCI Bus Master 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.2 Device Resets 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.3 Serial EEPROM I2C Bus 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.4 Function 0 (CardBus) Subsystem Identification 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.5 Function 1 (OHCI 1394) Subsystem Identification 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.6 Function 2 (Flash Media) Subsystem Identification 47 . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.7 Function 3 (SD Host) Subsystem Identification 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.8 Function 4 (Smart Card) Subsystem Identification 47 . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 PC Card Applications 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 PC Card Insertion/Removal and Recognition 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2 Low Voltage CardBus Card Detection 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.3 PC Card Detection 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.4 Flash Media and Smart Card Detection 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.5 Power Switch Interface 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.6 Internal Ring Oscillator 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.7 Integrated Pullup Resistors for PC Card Interface 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.8 SPKROUT and CAUDPWM Usage 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.9 LED Socket Activity Indicators 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.10 CardBus Socket Registers 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.11 48-MHz Clock Requirements 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

September 2005 SCPS110

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Contents

Section Page

3.6 Serial EEPROM Interface 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1 Serial-Bus Interface Implementation 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.2 Accessing Serial-Bus Devices Through Software 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.3 Serial-Bus Interface Protocol 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.4 Serial-Bus EEPROM Application 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Programmable Interrupt Subsystem 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.1 PC Card Functional and Card Status Change Interrupts 58 . . . . . . . . . . . . . . . . . . . . . .

3.7.2 Interrupt Masks and Flags 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.3 Using Parallel IRQ Interrupts 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.4 Using Parallel PCI Interrupts 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.5 Using Serialized IRQSER Interrupts 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.6 SMI Support in the PCIxx12 Controller 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 Power-Management Overview 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.1 1394 Power Management (Function 1) 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR) 63 . . . . . . . . . . . . . . . . . . . . . . . .

3.8.3 Clock Run Protocol 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.4 CardBus PC Card Power Management 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.5 16-Bit PC Card Power Management 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.6 Suspend Mode 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.7 Requirements for Suspend Mode 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.8 Ring Indicate 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.9 PCI Power Management 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.10 CardBus Bridge Power Management 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.11 ACPI Support 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.12 Master List of PME Context Bits and Global Reset-Only Bits 69 . . . . . . . . . . . . . . . . . .

3.9 IEEE 1394 Application Information 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.1 PHY Port Cable Connection 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.2 Crystal Selection 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.3 Bus Reset 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 PC Card Controller Programming Model 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 PCI Configuration Register Map (Function 0) 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Vendor ID Register 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Device ID Register Function 0 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Command Register 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Status Register 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Revision ID Register 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Class Code Register 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 Cache Line Size Register 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9 Latency Timer Register 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 Header Type Register 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11 BIST Register 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12 CardBus Socket Registers/ExCA Base Address Register 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.13 Capability Pointer Register 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14 Secondary Status Register 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15 PCI Bus Number Register 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16 CardBus Bus Number Register 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.17 Subordinate Bus Number Register 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.18 CardBus Latency Timer Register 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

September 2005SCPS110

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4.19 CardBus Memory Base Registers 0, 1 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.20 CardBus Memory Limit Registers 0, 1 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.21 CardBus I/O Base Registers 0, 1 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.22 CardBus I/O Limit Registers 0, 1 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23 Interrupt Line Register 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.24 Interrupt Pin Register 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.25 Bridge Control Register 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.26 Subsystem Vendor ID Register 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.27 Subsystem ID Register 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.29 System Control Register 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.30 General Control Register 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.31 General-Purpose Event Status Register 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.32 General-Purpose Event Enable Register 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.33 General-Purpose Input Register 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.34 General-Purpose Output Register 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.35 Multifunction Routing Status Register 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.36 Retry Status Register 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.37 Card Control Register 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.38 Device Control Register 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.39 Diagnostic Register 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.40 Capability ID Register 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.41 Next Item Pointer Register 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.42 Power Management Capabilities Register 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.43 Power Management Control/Status Register 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.44 Power Management Control/Status Bridge Support Extensions Register 102 . . . . . . . . . . . . . . . . .

4.45 Power-Management Data Register 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.46 Serial Bus Data Register 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.47 Serial Bus Index Register 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.48 Serial Bus Slave Address Register 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.49 Serial Bus Control/Status Register 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 ExCA Compatibilty Registers (Function 0) 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 ExCA Identification and Revision Register 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 ExCA Interface Status Register 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 ExCA Power Control Register 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 ExCA Interrupt and General Control Register 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 ExCA Card Status-Change Register 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 ExCA Card Status-Change Interrupt Configuration Register 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 ExCA Address Window Enable Register 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 ExCA I/O Window Control Register 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers 118 . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers 118 . . . . . . . . . . . . . . . . . . . . . . . . .

5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers 118 . . . . . . . . . . . . . . . . . . . . . . . . . .

5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers 119 . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers 119 . . . . . . . . . . . . . . . . . . . . . . . .

5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers 120 . . . . . . . . . . . . . . . . . . . . . . . .

5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers 120 . . . . . . . . . . . . . . . . . . . . . . . . .

5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers 121 . . . . . . . . . . . . . . . . . . . . . . . . .

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5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers 121 . . . . . . . . . . . . . . . . . . . . . . .

5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers 122 . . . . . . . . . . . . . . . . . . . . . . .

5.19 ExCA Card Detect and General Control Register 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.20 ExCA Global Control Register 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers 124 . . . . . . . . . . . . . . . . . . . . . . . .

5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers 125 . . . . . . . . . . . . . . . . . . . . . . . .

5.23 ExCA Memory Windows 0−4 Page Registers 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 CardBus Socket Registers (Function 0) 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Socket Event Register 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Socket Mask Register 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Socket Present State Register 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Socket Force Event Register 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Socket Control Register 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6 Socket Power Management Register 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 OHCI Controller Programming Model 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Vendor ID Register 135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 Device ID Register 135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Command Register 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Status Register 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Class Code and Revision ID Register 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 Latency Timer and Class Cache Line Size Register 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 Header Type and BIST Register 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8 OHCI Base Address Register 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.9 TI Extension Base Address Register 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.10 CardBus CIS Base Address Register 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.11 CardBus CIS Pointer Register 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.12 Subsystem Identification Register 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.13 Power Management Capabilities Pointer Register 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.14 Interrupt Line Register 142 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.15 Interrupt Pin Register 142 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.16 Minimum Grant and Maximum Latency Register 143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.17 OHCI Control Register 143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.18 Capability ID and Next Item Pointer Registers 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.19 Power Management Capabilities Register 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.20 Power Management Control and Status Register 146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.21 Power Management Extension Registers 146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.22 PCI PHY Control Register 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.23 PCI Miscellaneous Configuration Register 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.24 Link Enhancement Control Register 149 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.25 Subsystem Access Register 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.26 GPIO Control Register 151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 OHCI Registers 153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 OHCI Version Register 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 GUID ROM Register 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Asynchronous Transmit Retries Register 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 CSR Data Register 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5 CSR Compare Register 158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6 CSR Control Register 158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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8.7 Configuration ROM Header Register 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.8 Bus Identification Register 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.9 Bus Options Register 160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.10 GUID High Register 161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.11 GUID Low Register 161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.12 Configuration ROM Mapping Register 161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.13 Posted Write Address Low Register 162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.14 Posted Write Address High Register 162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.15 Vendor ID Register 162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.16 Host Controller Control Register 163 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.17 Self-ID Buffer Pointer Register 164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.18 Self-ID Count Register 165 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.19 Isochronous Receive Channel Mask High Register 166 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.20 Isochronous Receive Channel Mask Low Register 167 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.21 Interrupt Event Register 168 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.22 Interrupt Mask Register 170 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.23 Isochronous Transmit Interrupt Event Register 172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.24 Isochronous Transmit Interrupt Mask Register 172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.25 Isochronous Receive Interrupt Event Register 173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.26 Isochronous Receive Interrupt Mask Register 173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.27 Initial Bandwidth Available Register 174 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.28 Initial Channels Available High Register 174 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.29 Initial Channels Available Low Register 175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.30 Fairness Control Register 175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.31 Link Control Register 176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.32 Node Identification Register 177 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.33 PHY Layer Control Register 178 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.34 Isochronous Cycle Timer Register 178 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.35 Asynchronous Request Filter High Register 179 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.36 Asynchronous Request Filter Low Register 181 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.37 Physical Request Filter High Register 182 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.38 Physical Request Filter Low Register 184 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.39 Physical Upper Bound Register (Optional Register) 184 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.40 Asynchronous Context Control Register 185 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.41 Asynchronous Context Command Pointer Register 186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.42 Isochronous Transmit Context Control Register 187 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.43 Isochronous Transmit Context Command Pointer Register 188 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.44 Isochronous Receive Context Control Register 188 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.45 Isochronous Receive Context Command Pointer Register 189 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.46 Isochronous Receive Context Match Register 190 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 TI Extension Registers 191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 DV and MPEG2 Timestamp Enhancements 191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2 Isochronous Receive Digital Video Enhancements 192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3 Isochronous Receive Digital Video Enhancements Register 192 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4 Link Enhancement Register 194 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.5 Timestamp Offset Register 195 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 PHY Register Configuration 196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1 Base Registers 196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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10.2 Port Status Register 199 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3 Vendor Identification Register 200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4 Vendor-Dependent Register 201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.5 Power-Class Programming 202 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 Flash Media Controller Programming Model 203 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1 Vendor ID Register 203 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 Device ID Register 204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3 Command Register 204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.4 Status Register 205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.5 Class Code and Revision ID Register 206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.6 Latency Timer and Class Cache Line Size Register 206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.7 Header Type and BIST Register 207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.8 Flash Media Base Address Register 207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.9 Subsystem Vendor Identification Register 207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.10 Subsystem Identification Register 208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.11 Capabilities Pointer Register 208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.12 Interrupt Line Register 208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.13 Interrupt Pin Register 209 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.14 Minimum Grant Register 209 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.15 Maximum Latency Register 210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.16 Capability ID and Next Item Pointer Registers 210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.17 Power-Management Capabilities Register 211 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.18 Power-Management Control and Status Register 212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.19 Power-Management Bridge Support Extension Register 212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.20 Power-Management Data Register 212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.21 General Control Register 213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.22 Subsystem Access Register 214 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.23 Diagnostic Register 214 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 SD Host Controller Programming Model 215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1 Vendor ID Register 216 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2 Device ID Register 216 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3 Command Register 217 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.4 Status Register 218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.5 Class Code and Revision ID Register 219 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.6 Latency Timer and Class Cache Line Size Register 219 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.7 Header Type and BIST Register 220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.8 SD Host Base Address Register 220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.9 Subsystem Vendor Identification Register 221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.10 Subsystem Identification Register 221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.11 Capabilities Pointer Register 221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.12 Interrupt Line Register 221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.13 Interrupt Pin Register 222 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.14 Minimum Grant Register 222 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.15 Maximum Latency Register 223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.16 Slot Information Register 223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.17 Capability ID and Next Item Pointer Registers 223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.18 Power-Management Capabilities Register 224 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.19 Power-Management Control and Status Register 225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

September 2005SCPS110

Section Page

12.20 Power-Management Bridge Support Extension Register 225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.21 Power-Management Data Register 225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.22 General Control Register 226 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.23 Subsystem Access Register 226 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.24 Diagnostic Register 227 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.25 Slot 0 3.3-V Maximum Current Register 227 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 Smart Card Controller Programming Model 228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1 Vendor ID Register 229 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2 Device ID Register 229 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3 Command Register 230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4 Status Register 231 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.5 Class Code and Revision ID Register 232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.6 Latency Timer and Class Cache Line Size Register 232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.7 Header Type and BIST Register 233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.8 Smart Card Base Address Register 0 233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.9 Smart Card Base Address Register 1 234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.10 Subsystem Vendor Identification Register 234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.11 Subsystem Identification Register 234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.12 Capabilities Pointer Register 234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.13 Interrupt Line Register 235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.14 Interrupt Pin Register 235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.15 Minimum Grant Register 235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.16 Maximum Latency Register 236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.17 Capability ID and Next Item Pointer Registers 236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.18 Power-Management Capabilities Register 237 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.19 Power-Management Control and Status Register 238 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.20 Power-Management Bridge Support Extension Register 238 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.21 Power-Management Data Register 238 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.22 General Control Register 239 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.23 Subsystem ID Alias Register 239 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.24 Class Code Alias Register 240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.25 Smart Card Configuration 1 Register 240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.26 Smart Card Configuration 2 Register 241 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14 Electrical Characteristics 242 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.1 Absolute Maximum Ratings Over Operating Temperature Ranges 242 . . . . . . . . . . . . . . . . . . . . . . .

14.2 Recommended Operating Conditions 242 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.3 Electrical Characteristics Over Recommended Operating Conditions 244 . . . . . . . . . . . . . . . . . . . .

14.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions 244 . . . . . . . . . . .

14.4.1 Device 244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.4.2 Driver 245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.4.3 Receiver 245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and

Operating Free-Air Temperature 245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.6 Switching Characteristics for PHY Port Interface 246 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.7 Operating, Timing, and Switching Characteristics of XI 246 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.8 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air

Temperature 246 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.9 Reset Timing 248 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15 Mechanical Data 249 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

September 2005 SCPS110

Figures

List of Figures

Figure Page

2−1 PCI4512 GHK/ZHK-Package Terminal Diagram 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 PCI6412 GHK/ZHK-Package Terminal Diagram 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 PCI6612 GHK/ZHK-Package Terminal Diagram 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 PCI7402 GHK/ZHK-Package Terminal Diagram 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 PCI7412 GHK/ZHK-Package Terminal Diagram 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 PCI7612 GHK/ZHK-Package Terminal Diagram 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7 PCI8402 GHK/ZHK-Package Terminal Diagram 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 PCI8412 GHK/ZHK-Package Terminal Diagram 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 PCIxx12 System Block Diagram 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 3-State Bidirectional Buffer 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 PCI Reset Requirement 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 Serial ROM Application 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 SPKROUT Connection to Speaker Driver 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−6 Sample LED Circuit 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−7 Serial-Bus Start/Stop Conditions and Bit Transfers 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−8 Serial-Bus Protocol Acknowledge 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−9 Serial-Bus Protocol—Byte Write 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−10 Serial-Bus Protocol—Byte Read 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11 EEPROM Interface Doubleword Data Collection 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−12 IRQ Implementation 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13 System Diagram Implementing CardBus Device Class Power Management 63 . . . . . . . . . . . . . . . . . .

3−14 Signal Diagram of Suspend Function 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−15 RI_OUT Functional Diagram 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−16 Block Diagram of a Status/Enable Cell 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−17 TP Cable Connections 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−18 Typical Compliant DC Isolated Outer Shield Termination 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−19 Non-DC Isolated Outer Shield Termination 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−20 Load Capacitance for the PCIxx12 PHY 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−21 Recommended Crystal and Capacitor Layout 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 ExCA Register Access Through I/O 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 ExCA Register Access Through Memory 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1 Accessing CardBus Socket Registers Through PCI Memory 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14−1 Test Load Diagram 245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14−2 Cold Reset Sequence 247 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14−3 Warm Reset Sequence 247 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14−4 Contact Deactivation Sequence 248 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14−5 Reset Timing Diagram 248 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

September 2005SCPS110

List of Tables

Table Page

2−1 Functional Summary 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Terms and Definitions 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 Signal Names by GHK Terminal Number 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 CardBus PC Card Signal Names Sorted Alphabetically 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 16-Bit PC Card Signal Names Sorted Alphabetically 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 Power Supply Terminals 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7 Serial PC Card Power Switch Terminals 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 Parallel PC Card Power Switch Terminals 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9 PCI System Terminals 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 PCI Address and Data Terminals 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−11 PCI Interface Control Terminals 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−12 Multifunction and Miscellaneous Terminals 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−13 16-Bit PC Card Address and Data Terminals 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−14 16-Bit PC Card Interface Control Terminals 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−15 CardBus PC Card Interface System Terminals 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−16 CardBus PC Card Address and Data Terminals 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−17 CardBus PC Card Interface Control Terminals 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−18 Reserved Terminals 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−19 IEEE 1394 Physical Layer Terminals 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−20 No Connect Terminals 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−21 SD/MMC Terminals 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−22 Memory Stick/PRO Terminals 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−23 Smart Media/XD Terminals 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−24 Smart Card Terminals 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 PCI Bus Support 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 PC Card—Card Detect and Voltage Sense Connections 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 TPS2228 Control Logic—xVPP/VCORE 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 TPS2228 Control Logic—xVCC 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 TPS2226 Control Logic—xVPP 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−6 TPS2226 Control Logic—xVCC 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−7 CardBus Socket Registers 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−8 PCIxx12 Registers Used to Program Serial-Bus Devices 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−9 EEPROM Loading Map 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−10 Interrupt Mask and Flag Registers 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11 PC Card Interrupt Events and Description 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−12 Interrupt Pin Register Cross Reference 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13 SMI Control 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−14 Requirements for Internal/External 1.5-V Core Power Supply 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−15 Power-Management Registers 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−16 Function 1 Power-Management Registers 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−17 Function 2 Power-Management Registers 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−18 Function 3 Power-Management Registers 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−19 Function 4 Power-Management Registers 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 Bit Field Access Tag Descriptions 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 Function 0 PCI Configuration Register Map 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3 Command Register Description 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4 Status Register Description 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

September 2005 SCPS110

Tables

Table Page

4−5 Secondary Status Register Description 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6 Interrupt Pin Register Cross Reference 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−7 Bridge Control Register Description 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8 System Control Register Description 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−9 General Control Register Description 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−10 General-Purpose Event Status Register Description 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−11 General-Purpose Event Enable Register Description 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−12 General-Purpose Input Register Description 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−13 General-Purpose Output Register Description 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−14 Multifunction Routing Status Register Description 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−15 Retry Status Register Description 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−16 Card Control Register Description 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−17 Device Control Register Description 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−18 Diagnostic Register Description 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−19 Power Management Capabilities Register Description 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−20 Power Management Control/Status Register Description 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−21 Power Management Control/Status Bridge Support Extensions Register Description 102 . . . . . . . . . .

4−22 Serial Bus Data Register Description 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−23 Serial Bus Index Register Description 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−24 Serial Bus Slave Address Register Description 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−25 Serial Bus Control/Status Register Description 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 ExCA Registers and Offsets 108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 ExCA Identification and Revision Register Description 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−3 ExCA Interface Status Register Description 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−4 ExCA Power Control Register Description—82365SL Support 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−5 ExCA Power Control Register Description—82365SL-DF Support 112 . . . . . . . . . . . . . . . . . . . . . . . . . .

5−6 ExCA Interrupt and General Control Register Description 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−7 ExCA Card Status-Change Register Description 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−8 ExCA Card Status-Change Interrupt Configuration Register Description 115 . . . . . . . . . . . . . . . . . . . . .

5−9 ExCA Address Window Enable Register Description 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−10 ExCA I/O Window Control Register Description 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−11 ExCA Memory Windows 0−4 Start-Address High-Byte Registers Description 120 . . . . . . . . . . . . . . . .

5−12 ExCA Memory Windows 0−4 End-Address High-Byte Registers Description 121 . . . . . . . . . . . . . . . . .

5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description 122 . . . . . . . . . . . . . . .

5−14 ExCA Card Detect and General Control Register Description 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−15 ExCA Global Control Register Description 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1 CardBus Socket Registers 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−2 Socket Event Register Description 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−3 Socket Mask Register Description 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−4 Socket Present State Register Description 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−5 Socket Force Event Register Description 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−6 Socket Control Register Description 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−7 Socket Power Management Register Description 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1 Function 1 Configuration Register Map 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−2 Command Register Description 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−3 Status Register Description 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−4 Class Code and Revision ID Register Description 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−5 Latency Timer and Class Cache Line Size Register Description 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xii

September 2005SCPS110

Table Page

7−6 Header Type and BIST Register Description 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−7 OHCI Base Address Register Description 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−8 TI Base Address Register Description 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−9 CardBus CIS Base Address Register Description 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−10 Subsystem Identification Register Description 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−11 Interrupt Line Register Description 142 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−12 PCI Interrupt Pin Register—Read-Only INTPIN Per Function 142 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−13 Minimum Grant and Maximum Latency Register Description 143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−14 OHCI Control Register Description 143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−15 Capability ID and Next Item Pointer Registers Description 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−16 Power Management Capabilities Register Description 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−17 Power Management Control and Status Register Description 146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−18 Power Management Extension Registers Description 146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−19 PCI PHY Control Register Description 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−20 PCI Miscellaneous Configuration Register Description 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−21 Link Enhancement Control Register Description 149 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−22 Subsystem Access Register Description 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−1 OHCI Register Map 153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−2 OHCI Version Register Description 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−3 GUID ROM Register Description 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−4 Asynchronous Transmit Retries Register Description 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−5 CSR Control Register Description 158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−6 Configuration ROM Header Register Description 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−7 Bus Options Register Description 160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−8 Configuration ROM Mapping Register Description 161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−9 Posted Write Address Low Register Description 162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−10 Posted Write Address High Register Description 162 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−11 Host Controller Control Register Description 163 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−12 Self-ID Count Register Description 165 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−13 Isochronous Receive Channel Mask High Register Description 166 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−14 Isochronous Receive Channel Mask Low Register Description 167 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−15 Interrupt Event Register Description 168 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−16 Interrupt Mask Register Description 170 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−17 Isochronous Transmit Interrupt Event Register Description 172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−18 Isochronous Receive Interrupt Event Register Description 173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−19 Initial Bandwidth Available Register Description 174 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−20 Initial Channels Available High Register Description 174 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−21 Initial Channels Available Low Register Description 175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−22 Fairness Control Register Description 175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−23 Link Control Register Description 176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−24 Node Identification Register Description 177 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−25 PHY Control Register Description 178 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−26 Isochronous Cycle Timer Register Description 178 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−27 Asynchronous Request Filter High Register Description 179 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−28 Asynchronous Request Filter Low Register Description 181 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−29 Physical Request Filter High Register Description 182 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−30 Physical Request Filter Low Register Description 184 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−31 Asynchronous Context Control Register Description 185 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

September 2005 SCPS110

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Tables

Table Page

8−32 Asynchronous Context Command Pointer Register Description 186 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−33 Isochronous Transmit Context Control Register Description 187 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−34 Isochronous Receive Context Control Register Description 188 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−35 Isochronous Receive Context Match Register Description 190 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−1 TI Extension Register Map 191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−2 Isochronous Receive Digital Video Enhancements Register Description 192 . . . . . . . . . . . . . . . . . . . . .

9−3 Link Enhancement Register Description 194 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−4 Timestamp Offset Register Description 195 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−1 Base Register Configuration 196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−2 Base Register Field Descriptions 197 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−3 Page 0 (Port Status) Register Configuration 199 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−4 Page 0 (Port Status) Register Field Descriptions 199 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−5 Page 1 (Vendor ID) Register Configuration 200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−6 Page 1 (Vendor ID) Register Field Descriptions 200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−7 Page 7 (Vendor-Dependent) Register Configuration 201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−8 Page 7 (Vendor-Dependent) Register Field Descriptions 201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10−9 Power Class Descriptions 202 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−1 Function 2 Configuration Register Map 203 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−2 Command Register Description 204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−3 Status Register Description 205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−4 Class Code and Revision ID Register Description 206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−5 Latency Timer and Class Cache Line Size Register Description 206 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−6 Header Type and BIST Register Description 207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−7 Flash Media Base Address Register Description 207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−8 PCI Interrupt Pin Register 209 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−9 Minimum Grant Register Description 209 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−10 Maximum Latency Register Description 210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−11 Capability ID and Next Item Pointer Registers Description 210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−12 Power-Management Capabilities Register Description 211 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−13 Power-Management Control and Status Register Description 212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−14 General Control Register 213 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−15 Subsystem Access Register Description 214 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11−16 Diagnostic Register Description 214 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−1 Function 3 Configuration Register Map 215 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−2 Command Register Description 217 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−3 Status Register Description 218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−4 Class Code and Revision ID Register Description 219 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−5 Latency Timer and Class Cache Line Size Register Description 219 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−6 Header Type and BIST Register Description 220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−7 SD Host Base Address Register Description 220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−8 PCI Interrupt Pin Register 222 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−9 Minimum Grant Register Description 222 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−10 Maximum Latency Register Description 223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−11 Maximum Latency Register Description 223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−12 Capability ID and Next Item Pointer Registers Description 223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−13 Power-Management Capabilities Register Description 224 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−14 Power-Management Control and Status Register Description 225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−15 General Control Register 226 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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September 2005SCPS110

Table Page

12−16 Subsystem Access Register Description 227 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12−17 Diagnostic Register Description 227 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−1 Function 4 Configuration Register Map 228 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−2 Command Register Description 230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−3 Status Register Description 231 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−4 Class Code and Revision ID Register Description 232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−5 Latency Timer and Class Cache Line Size Register Description 232 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−6 Header Type and BIST Register Description 233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−7 PCI Interrupt Pin Register 235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−8 Minimum Grant Register Description 235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−9 Maximum Latency Register Description 236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−10 Capability ID and Next Item Pointer Registers Description 236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−11 Power-Management Capabilities Register Description 237 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−12 Power-Management Control and Status Register Description 238 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−13 General Control Register 239 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−14 Subsystem ID Alias Register Description 239 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−15 Smart Card Configuration 1 Register Description 241 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13−16 Smart Card Configuration 2 Register Description 241 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

September 2005 SCPS110

Tables

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September 2005SCPS110

1 PCIxx12 Features

D PC Card Standard 8.1 Compliant D PCI Bus Power Management Interface

Specification 1.1 Compliant

D Advanced Configuration and Power

Interface (ACPI) Specification 2.0 Compliant

D PCI Local Bus Specification Revision 2.3

Compliant

D Windows Logo Program Compliant D PCI Bus Interface Specification for

PCI-to-CardBus Bridges

D Fully Compliant with Provisions of IEEE

Std 1394-1995 for a High-Performance Serial Bus and IEEE Std 1394a-2000

D Fully Compliant with 1394 Open Host

Controller Interface Specification 1.1

D 1.5-V Core Logic and 3.3-V I/O Cells with

Internal Voltage Regulator to Generate

1.5-V Core V

D Universal PCI Interfaces Compatible with

3.3-V and 5-V PCI Signaling Environments

D Supports PC Card or CardBus with Hot

Insertion and Removal

D Supports 132-MBps Burst Transfers to

Maximize Data Throughput on Both the PCI Bus and the CardBus

D Supports Serialized IRQ with PCI Interrupts D Programmable Multifunction Terminals D Many Interrupt Modes Supported D Serial ROM Interface for Loading

Subsystem ID and Subsystem Vendor ID

D ExCA-Compatible Registers Are Mapped in

Memory or I/O Space

D Intel 82365SL-DF Register Compatible

Features

D Supports Ring Indicate, SUSPEND, and PCI

CLKRUN

Protocols

D Provides VGA/Palette Memory and I/O, and

Subtractive Decoding Options, LED Activity Terminals

D Fully Interoperable with FireWireE and

i.LINKE Implementations of IEEE Std 1394

D Compliant with Intel Mobile Power

Guideline 2000

D Full IEEE Std 1394a-2000 Support Includes:

Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, and Port Disable/Suspend/Resume

D Power-Down Features to Conserve Energy

in Battery-Powered Applications Include: Automatic Device Power Down During Suspend, PCI Power Management for Link-Layer, and Inactive Ports Powered Down, Ultralow-Power Sleep Mode

D Two IEEE Std 1394a-2000 Fully Compliant

Cable Ports at 100M Bits/s, 200M Bits/s, and 400M Bits/s

D Cable Ports Monitor Line Conditions for

Active Connection to Remote Node

D Cable Power Presence Monitoring D Separate Cable Bias (TPBIAS) for Each Port D Physical Write Posting of up to Three

Outstanding Transactions

D PCI Burst Transfers and Deep FIFOs to

Tolerate Large Host Latency

D External Cycle Timer Control for

Customized Synchronization

D Extended Resume Signaling for

Compatibility with Legacy DV Components

MicroStar BGA is a trademark of Texas Instruments. Other trademarks are the property of their respective owners.

September 2005 SCPS110

Features

D PHY-Link Logic Performs System

Initialization and Arbitration Functions

D PHY-Link Encode and Decode Functions

Included for Data-Strobe Bit Level Encoding

D PHY-Link Incoming Data Resynchronized to

Local Clock

D Low-Cost 24.576-MHz Crystal Provides

Transmit and Receive Data at 100M Bits/s, 200M Bits/s, and 400M Bits/s

D Node Power Class Information Signaling

for System Power Management

D Register Bits Give Software Control of

Contender Bit, Power Class Bits, Link Active Control Bit, and IEEE Std 1394a-2000 Features

D Isochronous Receive Dual-Buffer Mode D Out-Of-Order Pipelining for Asynchronous

Transmit Requests

D Register Access Fail Interrupt When the

PHY SCLK Is Not Active

D PCI Power-Management D0, D1, D2, and D3

Power States

D Initial Bandwidth Available and Initial

Channels Available Registers

D PME Support Per 1394 Open Host

Controller Interface Specification

D Advanced Submicron, Low-Power CMOS

Technology

T able 1−1.

Figure 1−1.

September 2005SCPS110

2 Introduction

The Texas Instruments PCI4512 controller is an integrated single-socket PC Card controller, IEEE 1394 open HCI host controller and two-port PHY. This high-performance integrated solution provides the latest in PC Card and IEEE 1394 technology.

The Texas Instruments PCI6412 controller is an integrated single-socket PC Card controller and flash media controller. This high-performance integrated solution provides the latest in PC Card, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology.

The Texas Instruments PCI6612 controller is an integrated single-socket PC Card controller, Smart Card controller, and flash media controller. This high-performance integrated solution provides the latest in PC Card, Smart Card, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology.

The Texas Instruments PCI7402 controller is an integrated single-socket IEEE 1394 open HCI host controller and two-port PHY and flash media controller. This high-performance integrated solution provides the latest in IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology.

The Texas Instruments PCI7412 controller is an integrated single-socket PC Card controller, IEEE 1394 open HCI host controller and two-port PHY, and flash media controller. This high-performance integrated solution provides the latest in PC Card, IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology.

Introduction

The Texas Instruments PCI7612 controller is an integrated single-socket PC Card controller, Smart Card controller, IEEE 1394 open HCI host controller and two-port PHY, and flash media controller. This high-performance integrated solution provides the latest in PC Card, Smart Card, IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology.

The Texas Instruments PCI8402 controller is an integrated single-socket IEEE 1394 open HCI host controller and one-port PHY and flash media controller. This high-performance integrated solution provides the latest in IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology.

The Texas Instruments PCI8412 controller is an integrated single-socket PC Card controller, IEEE 1394 open HCI host controller and one-port PHY, and flash media controller. This high-performance integrated solution provides the latest in PC Card, IEEE 1394, SD, MMC, Memory Stick/PRO, SmartMedia, and xD technology.

For the remainder of this document, the PCIxx12 controller refers to the PCI4512, PCI6412, PCI6612, PCI7402, PCI7412, PCI7612, PCI8402, and PCI8412 controllers.

Table 2−1 shows a summary of the PCIxx12 functions listed by controller.

Table 2−1. Functional Summary

Controller

PCI4512 X X PCI6412 X X X PCI6612 X X X X PCI7402 X X X PCI7412 X X X X PCI7612 X X X X X PCI8402 X X X PCI8412 X X X X

Function 0

(CardBus)

Function 1

(1394 OHCI)

Function 2

(Flash Media)

Function 3

(SD Host)

Function 4

(Smart Card)

September 2005 SCPS110

Introduction

2.1 Controller Functional Description

2.1.1 PCI4512 Controller

The PCI4512 controller is a two-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.

Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI4512 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports Smart Card, 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI4512 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI4512 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI4512 controller can be programmed to accept posted writes to improve bus utilization.

Function 1 of the PCI4512 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI4512 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance.

2.1.2 PCI6412 Controller

The PCI6412 controller is a three-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.

Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI6412 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports Smart Card, 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI6412 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI6412 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI6412 controller can be programmed to accept posted writes to improve bus utilization.

Function 2 of the PCI6412 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance.

Function 3 of the PCI6412 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume.

September 2005SCPS110

2.1.3 PCI6612 Controller

The PCI6612 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.

Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI6612 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports Smart Card, 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI6612 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI6612 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI6612 controller can be programmed to accept posted writes to improve bus utilization.

Function 2 of the PCI6612 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance.

Function 3 of the PCI6612 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume.

Introduction

Function 4 of the PCI6612 controller is a PCI-based Smart Card controller used for communication with Smart Cards inserted in PC Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with many different types of Smart Cards.

2.1.4 PCI7402 Controller

The PCI7402 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.

Function 0 is a dummy PC Card controller function. The PC Card socket is non-functional and the pins associated with the PC card socket may be left unconnected. The function is required for device enumeration and is provided for BIOS compatibility with existing devices. The PC Card function may be hidden from the OS by the BIOS.

Function 1 of the PCI7402 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI7402 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance.

Function 2 of the PCI7402 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance.

Function 3 of the PCI7402 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume.

September 2005 SCPS110

Introduction

2.1.5 PCI7412 Controller

The PCI7412 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.

Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI7412 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI7412 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI7412 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI7412 controller can be programmed to accept posted writes to improve bus utilization.

Function 1 of the PCI7412 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI7412 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance.

Function 2 of the PCI7412 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance.

Function 3 of the PCI7412 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume.

2.1.6 PCI7612 Controller

The PCI7612 controller is a five-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.

Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI7612 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports Smart Card, 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI7612 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI7612 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI7612 controller can be programmed to accept posted writes to improve bus utilization.

Function 1 of the PCI7612 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 2-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI7612 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance.

Function 2 of the PCI7612 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance.

September 2005SCPS110

Function 3 of the PCI7612 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume.

Function 4 of the PCI7612 controller is a PCI-based Smart Card controller used for communication with Smart Cards inserted in PC Card adapters. Utilizing Smart Card technology from Gemplus, this function provides compatibility with many different types of Smart Cards.

2.1.7 PCI8402 Controller

The PCI8402 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.

Function 1 of the PCI8402 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 1-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI8402 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance.

Introduction

Function 2 of the PCI8402 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance.

Function 3 of the PCI8402 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume.

2.1.8 PCI8412 Controller

The PCI8412 controller is a four-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3.

Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard (Release 8.1). The PCI8412 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports Smart Card, 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI8412 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI8412 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI8412 controller can be programmed to accept posted writes to improve bus utilization.

Function 1 of the PCI8412 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 1-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI8412 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance.

September 2005 SCPS110

Introduction

Function 2 of the PCI8412 controller is a PCI-based Flash Media controller that supports Memory Stick, Memory Stick-Pro, SmartMedia, xD, SD, and MMC cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function includes DMA capabilities for improved Flash Media performance.

Function 3 of the PCI8412 controller is a PCI-based SD host controller that supports MMC, SD, and SDIO cards. This function controls communication with these Flash Media cards through a dedicated Flash Media socket. In addition, this function is compliant with the SD Host Controller Standard Specification and includes DMA capabilities, support for high-speed mode, and support for SD suspend/resume.

2.1.9 Multifunctional Terminals

Various implementation-specific functions and general-purpose inputs and outputs are provided through eight multifunction terminals. These terminals present a system with options in serial and parallel interrupts, PC Card activity indicator LEDs, flash media LEDs, and other platform-specific signals. PCI-compliant general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs.

2.1.10 PCI Bus Power Management

The PCIxx12 controller is compliant with the latest PCI Bus Power Management Specification, and provides several low-power modes, which enable the host power system to further reduce power consumption.

2.1.11 Power Switch Interface

The PCIxx12 controller supports both the three-pin serial interface compatible with the Texas Instruments TPS2228 (default), TPS2226, TPS2224, and TPS2223A power switches and the four-pin parallel interface compatible with the Texas Instruments TPS2211A and TPS2212 power switches.

The interface mode is selected by strapping the RSVD/VD0/VCCD1 mode) or low (four-pin parallel mode). Note that when using the four-pin parallel mode the Smart Card and Flash Media sockets must be powered via discrete power switches. All of the power switches provide power to the CardBus socket on the PCIxx12 controller. The power to each dedicated flash media socket is controlled through separate power control pins or it may be configured to source power through BVCC of a dual-socket PCMCIA power switch. The power to the dedicated Smart Card socket is controlled through a separate power control pin that can control an external 5-V power switch or it may be configured to source power through BVPP of a dual-socket PCMCIA power switch. Each of the dedicated power control pins can be connected to an external power switch.

2.2 Related Documents

• Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0)

• 1394 Open Host Controller Interface Specification (Release 1.1)

• IEEE Standard for a High Performance Serial Bus (IEEE Std 1394-1995)

• IEEE Standard for a High Performance Serial Bus—Amendment 1 (IEEE Std 1394a-2000)

• PC Card Standard (Release 8.1)

• PCI Bus Power Management Interface Specification (Revision 1.1)

• Serial Bus Protocol 2 (SBP-2)

terminal either high (three-pin serial

• Serialized IRQ Support for PCI Systems

• PCI Mobile Design Guide

• PCI Bus Power Management Interface Specification for PCI to CardBus Bridges

September 2005SCPS110

• PCI to PCMCIA CardBus Bridge Register Description

• Texas Instruments TPS2224 and TPS2226 product data sheet, SLVS317

• Texas Instruments TPS2223A product data sheet, SLVS428

• Texas Instruments TPS2228 product data sheet, SLVS419

• PCI Local Bus Specification (Revision 2.3)

• PCMCIA Proposal (262)

• The Multimedia Card System Specification, Version 3.31

• SD Memory Card Specifications, SD Group, March 2000

• Memory Stick Format Specification, Version 2.0 (Memory Stick-Pro)

• ISO Standards for Identification Cards ISO/IEC 7816

• SD Host Controller Standard Specification, rev. 1.0

• Memory Stick Format Specification, Sony Confidential, ver. 2.0

• SmartMedia Standard 2000, May 19, 2000

2.3 Trademarks

Intel is a trademark of Intel Corporation.

Introduction

TI and MicroStar BGA are trademarks of Texas Instruments. FireWire is a trademark of Apple Computer, Inc. i.LINK is a trademark of Sony Corporation of America. Memory Stick is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan. Other trademarks are the property of their respective owners.

2.4 Document Conventions

Throughout this data manual, several conventions convey information. These conventions are listed below:

1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary field.

2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit hexadecimal field.

3. All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format.

4. If the signal or terminal name has a bar above the name (for example, GRST logical NOT function. When asserted, this signal is a logic low, 0, or 0b.

5. RSVD indicates that the referenced item is reserved.

6. In Sections 4 through 13, the configuration space for the controller is defined. For each register bit, the software access method is identified in an access column. The legend for this access column includes the following entries:

), then this indicates the

r – read-only access ru – read-only access with updates by the controller internal hardware

September 2005 SCPS110

Introduction

rw – read and write access rcu – read access with the option to clear an asserted bit with a write-back of 1b including updates

by the controller internal hardware.

2.5 Terms and Definitions

Terms and definitions used in this document are given in Table 2−2.

Table 2−2. Terms and Definitions

TERM DEFINITIONS

AT AT (advanced technology, as in PC AT) attachment interface CIS Card information structure. Tuple list defined by the PC Card standard to communicate card information to the host computer. CSR Control and status register Flash Media SmartMedia, Memory Stick, MS/PRO, xD, MMC, or SD/MMC Flash operating in an ATA compatible mode ISO/IEC 7816 The Smart Card standard Memory Stick A small-form-factor flash interface that is defined, promoted, and licensed by Sony Memory Stick

Pro MMC MultiMediaCard. Specified by the MMC Association, and scope is encompassed by the SD Flash specification. OHCI Open host controller interface PCMCIA Personal Computer Memory Card International Association. Standards body that governs the PC Card standards. RSVD Reserved for future use SD Flash Secure Digital Flash. Standard governed by the SD Association. Smart Card The name applied to ID cards containing integrated circuits, as defined by ISO/IEC 7816-1 SPI Serial peripheral interface, a general-purpose synchronous serial interface. For more information, see the Multimedia Card

SSFDC Solid State Floppy Disk Card. The SSFDC Forum specifies SmartMedia. TI Smart Card

driver

UltraMedia De facto industry standard promoted by Texas Instruments that integrates CardBus, Smart Card, Memory Stick,

xD Extreme Digital, small form factor flash based on SmartMedia cards, developed by Fuji Film and Olympus Optical.

Memory Stick V ersion 2.0, same physical dimensions of MS with higher speed data exchange and higher data capacity than conventional Memory Stick.

System Specification, version 3.2.

A qualified software component provided by Texas Instruments that loads when an UltraMedia-based Smart Card adapter is inserted into a PC Card slot. This driver is logically attached to a CIS provided by the PCI7621 when the adapter and media are both inserted.

MultiMediaCard/Secure Digital and SmartMedia functionality into one controller.

September 2005SCPS110

Introduction

Single Socket CardBus Controller with Integrated 1394a-2000 OHCI

Single Socket CardBus Controller with Dedicated Flash Media

Single Socket CardBus Controller with Dedicated Flash Media and

Two-Port PHY/Link-Layer Controller with Dedicated Flash Media

One-Port PHY/Link-Layer Controller with Dedicated Flash Media

2.6 Ordering Information

ORDERING NUMBER NAME PACKAGE COMMENT

PCI4512GHK

PCI4512ZHK

PCI6412GHK

PCI6412ZHK

PCI6612GHK

PCI6612ZHK

PCI7402GHK

Single Socket CardBus Controller with Integrated 1394a-2000 OHC Two-Port PHY/Link-Layer Controller

Single Socket CardBus Controller with Dedicated Flash Media Socket

Single Socket CardBus Controller with Dedicated Flash Media and Smart Card Sockets

Single Socket CardBus Controller with Integrated 1394a-2000 OHC

216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device

216-ball PBGA Standard lead (Pb) device

PCI7402ZHK

PCI7412GHK

PCI7412ZHK

PCI7612GHK

PCI7612ZHK

PCI8402GHK

PCI8402ZHK

PCI8412GHK

PCI8412ZHK

Socket Single Socket CardBus Controller with Integrated 1394a-2000 OHC

and Smart Card Sockets Single Socket CardBus Controller with Integrated 1394a-2000 OHC

Socket Single Socket CardBus Controller with Integrated 1394a-2000 OHC

Socket

2.7 PCIxx12 Data Manual Document History

DATE PAGE NUMBER REVISION

05/2005 All Draft copy

2.8 Terminal Assignments

The PCIxx12 controller is available in the 216-terminal MicroStar BGA package (GHK) or the 216-terminal lead-free (Pb, atomic number 82) MicroStar BGA package (ZHK). Figure 2−1 is a terminal diagram of the PCI4512 package. Figure 2−2 is a terminal diagram of the PCI6412 package. Figure 2−3 is a terminal diagram of the PCI6612 package. Figure 2−4 is a terminal diagram of the PCI7402 package. Figure 2−5 is a terminal diagram of the PCI7412 package. Figure 2−6 is a terminal diagram of the PCI7612 package. Figure 2−7 is a terminal diagram of the PCI8402 package. Figure 2−8 is a terminal diagram of the PCI8412 package.

216-ball PBGA Lead-free (Pb-free) device 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device 216-ball PBGA Standard lead (Pb) device 216-ball PBGA Lead-free (Pb-free) device

September 2005 SCPS110

Introduction

12345678910111213141516171819

AD18 AD17 R0 R1

AD22 AD21 AD19 FRAME PERR AD14 AD8 AD5 AD0 CPS

VCCP C/BE3 AD23 AD20 VCC GND VCC GND VCC AD1 TEST0

AD26 AD25 AD24 IDSEL GND

AD31 AD30 AD29 AD27 AD28 GND

PCLK GNT REQ

VR_

VR_EN PRST GRST GND GND

PORT

AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N TPB1N TPA1N

IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P TPB1P TPA1P

DEV-

C/BE2

RI_OUT

/ PME

PAR AD13 AD9 AD6 AD2 NC AGND AGND

SEL

VCC VCC

TPBIAS

AVDD_

_33

AVDD_

_33

AGND VSSPLL XO XI

AVDD_

VDD

_33

PLL_15

CCD1 // CD1

CAD3

// D5

CAD9 // A10

CAD12

// A11

TPBIAS

PHY_

TEST_

CAD2 // D11

CAD6 // D13

CC/

BE0

CE1

CAD11

// OE

CAD1

// D4

CAD5

// D6

CAD8 // D15

CAD10

// CE2

VDD

PLL_33

CAD0

// D3

CAD4 // D12

RSVD

// D14

CAD7

// D7

VR_

PORT

CVS2 //

VS2

CAD20

// A6

CAD15

IOWR

RSVD // A18

CGNT // WE

CIRDY

// A15

CAD18

// A7

MFUNC4MFUNC5MFUNC

MFUNC3MFUNC

MFUNC

GND RSVD RSVD RSVD VCC GND RSVD VCC GND

RSVD RSVD RSVD NC RSVD RSVD RSVD RSVD

RSVD

SPKR

OUT

SCL SDA RSVD VCC GND

RSVD RSVD RSVD RSVD RSVD RSVD

SUS-

VCC VCC

PEND

MFUNC

GND

RSVD /

VD0 /

RSVD RSVD RSVD RSVD

VCCD1

RSVD RSVD RSVD RSVD RSVD

LATCH / VD3 / VPPD0

DATA /

VD2 /

VPPD1

CLOCK / VD1 / VCCD0

CAD29

// D1

USB_ENCAD28

// D8

CAD31

CAD27

// D10

// D0

RSVD

CCD2

// D2

// CD2

CCLK

RUN //

CAD30

// D9

(IOIS16

VCC GND VCC

CINT //

CC/

READY

BE3

)

REG

(IREQ

CSERR

CAD25

// WAIT

// A1

CAU-

DIO //

CAD26

BVD2

// A0

(SPKR

)

CSTS

CHG //

CVS1 //

BVD1

VS1

(STSC

)

HG/RI)

CAD14

// A9

CPAR

CBLOC K // A19

// A13

CTRDY

// A22

CAD17

// A24

CAD21

// A5

CREQ

CRST

// IN-

// RE-

PACK

SET

CAD23

CAD22

// A3

// A4

CAD24

VCCCB

// A2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CAD13 // IORD

CC/

BE1

CSTOP

// A20

CCLK // A16

CC/

BE2

A12

VCCCB

CAD16

// A17

CPERR

// A14

CDEV-

SEL //

A21

CFRAM

E // A23

CAD19

// A25

Figure 2−1. PCI4512 GHK/ZHK-Package Terminal Diagram

September 2005SCPS110

Introduction

12345678910111213141516171819

AD18 AD17 GND GND

AD22 AD21 AD19 FRAME PERR AD14 AD8 AD5 AD0 GND RSVD GND GND RSVD RSVD

VCCP C/BE3 AD23 AD20 VCC GND VCC GND VCC AD1 TEST0 VCC VCC RSVD

AD26 AD25 AD24 IDSEL GND

AD31 AD30 AD29 AD27 AD28 GND

PCLK GNT REQ

VR_

VR_EN PRST GRST GND GND

PORT

AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC RSVD RSVD RSVD RSVD RSVD

IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC RSVD RSVD RSVD RSVD

DEV-

C/BE2

RI_OUT

/ PME

PAR AD13 AD9 AD6 AD2 NC GND GND VCC VCC

SEL

PHY_

TEST_

VCC VCC

CCD1 // CD1

CAD3

// D5

CAD9 // A10

CAD12

// A11

CAD2 // D11

CAD6 // D13

CC/

BE0

CE1

CAD11

// OE

CAD1

// D4

CAD5

// D6

CAD8 // D15

CAD10

// CE2

CAD0

// D3

CAD4 // D12

RSVD // D14

CAD7

// D7

VR_

PORT

CVS2 //

VS2

CAD20

// A6

CAD15

IOWR

RSVD // A18

CGNT // WE

CIRDY

// A15

CAD18

// A7

MFUNC4MFUNC5MFUNC

MFUNC3MFUNC

MFUNC

CLK_48 RSVD RSVD RSVD VCC GND

RSVD RSVD RSVD NC

RSVD

SPKR

OUT

SCL SDA RSVD VCC GND

XD_CD

/ SM_

PHYS_

RSVD /

VD0 /

VCCD1

SM_ CLE

SD_

CLK /

SM_RE

SUS-

PEND

MFUNC

SD_

CMD /

SM_ ALE

SD_

DAT2 /

SM_D6

SD_

DAT1 /

SM_D5

VCC VCC

GND

MC_

SD_

DAT3 /

SM_D7

SD_

DAT0 /

SM_D4

MS_

DATA3 /

SD_

DAT3 /

SM_D3

MS_

DATA2 /

SD_

DAT2 /

SM_D2

SD_WP

SM_CE

MS_

DATA1 /

SD_

DAT1 /

SM_D1

MS_

SDIO

(DATA0)

/ SD_

DAT0 /

SM_D0

MS_

CLK /

SD_

CLK /

SM_EL_

PWR_

CTRL_

1 /

SM_R/B MS_BS

/ SD_

CMD /

SM_WE

MC_

PWR_

CTRL_

SM_CD

MS_CD

VCC GND

SD_CD

LATCH

/ VD3 /

VPPD0

DATA /

VD2 /

VPPD1

CLOCK

/ VD1 /

VCCD0

CAD29

// D1

USB_ENCAD28

// D8

CAD31

CAD27

// D10

// D0

RSVD

CCD2

// D2

// CD2

CCLK

RUN //

CAD30

// D9

(IOIS16

VCC GND VCC

CINT //

CC/

READY

BE3

)

REG

(IREQ

CSERR

CAD25

// WAIT

// A1

CAU-

DIO //

CAD26

// A0

BVD2

)

(SPKR

CSTS

CHG //

CVS1 //

BVD1

VS1

(STSC

)

HG/RI)

CAD21

CAD23

CAD24

CPAR // A13

// A5

CREQ

// IN-

PACK

// A3

// A2

CAD14

// A9

CBLOC K // A19

CTRDY

// A22

CAD17

// A24

CRST // RE-

SET

CAD22

// A4

VCCCB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CAD13 // IORD

CC/

BE1

CSTOP

// A20

CCLK // A16

CC/

BE2

A12

VCCCB

CAD16

// A17

CPERR

// A14

CDEV-

SEL //

A21

CFRAM

E // A23

CAD19

// A25

Figure 2−2. PCI6412 GHK/ZHK-Package Terminal Diagram

September 2005 SCPS110

Introduction

12345678910111213141516171819

AD18 AD17 GND GND

AD22 AD21 AD19 FRAME PERR AD14 AD8 AD5 AD0 GND RSVD AGND GND RSVD RSVD

VCCP C/BE3 AD23 AD20 VCC GND VCC GND VCC AD1 TEST0 VCC VCC RSVD

AD26 AD25 AD24 IDSEL GND

AD31 AD30 AD29 AD27 AD28 GND

PCLK GNT REQ

VR_

VR_EN PRST GRST GND GND

PORT

AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC RSVD RSVD RSVD RSVD RSVD

IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC RSVD RSVD RSVD RSVD

DEV-

C/BE2

RI_OUT

/ PME

PAR AD13 AD9 AD6 AD2 NC GND GND VCC VCC

SEL

PHY_

TEST_

VCC VCC

CCD1 // CD1

CAD3

// D5

CAD9 // A10

CAD12

// A11

CAD2 // D11

CAD6 // D13

CC/

BE0

CE1

CAD11

// OE

CAD1

// D4

CAD5

// D6

CAD8 // D15

CAD10

// CE2

CAD0

// D3

CAD4 // D12

RSVD

// D14

CAD7

// D7

VR_

PORT

CVS2 //

VS2

CAD20

// A6

CAD15

IOWR

RSVD // A18

CGNT // WE

CIRDY

// A15

CAD18

// A7

MFUNC4MFUNC5MFUNC

MFUNC3MFUNC

MFUNC

CLK_48 SC_OC SC_CD

SC_

DATA

SC_

RFU

SPKR

OUT

SCL SDA

SC_

CLK

FCB

XD_CD

/ SM_

PHYS_

SUS-

RSVD /

VD0 /

VCCD1

SM_

CLE /

SC_

GPIO0

SD_

CLK /

SM_RE

/ SC_

GPIO1

VCC VCC

PEND

MFUNC

GND

SC_

PWR_

VCC_

CTRL

MC_

SD_WP

SM_CE

MS_

DATA1 /

SD_

DAT1 /

SM_D1

MS_ SDIO

(DATA0)

/ SD_

DAT0 /

SM_D0

MS_

CLK /

SD_

CLK /

SM_EL_

PWR_

CTRL_

1 /

SM_R/B

MS_BS

/ SD_

CMD /

SM_WE

MC_

PWR_

CTRL_

SM_CD

MS_CD

VCC GND

SD_CD

LATCH / VD3 / VPPD0

DATA /

VD2 /

VPPD1

CLOCK

/ VD1 /

VCCD0

CAD29

// D1

USB_ENCAD28

// D8

CAD31

CAD27

// D10

// D0

RSVD

CCD2

// D2

// CD2

CCLK

RUN //

CAD30

// D9

(IOIS16

)

SC_ RST

SD_

CMD /

SM_

ALE /

SC_

GPIO2

SD_ DAT2 / SM_D6

/ SC_

GPIO4

SD_ DAT1 / SM_D5

/ SC_

GPIO5

VCC GND

SD_

DAT3 /

SM_D7

/ SC_

GPIO3

SD_

DAT0 /

SM_D4

/ SC_

GPIO6

MS_

DATA3 /

SD_

DAT3 /

SM_D3

MS_

DATA2 /

SD_

DAT2 /

SM_D2

VCC GND VCC

CINT //

CC/

READY

(IREQ

CSERR // WAIT

CAUDIO // BVD2

(SPKR)

CSTS

CHG //

BVD1

(STSC HG/RI)

BE3

)

REG

CAD25

// A1

CAD26

// A0

CVS1 //

VS1

CPAR

// A13

GND

CAD21

// A5

CREQ

// IN-

PACK

CAD23

// A3

CAD24

// A2

CAD14

// A9

CBLOC K // A19

CTRDY

// A22

CAD17

// A24

CRST // RE-

SET

CAD22

// A4

VCCCB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CAD13 // IORD

CC/

BE1

CSTOP

// A20

CCLK // A16

CC/

BE2

A12

VCCCB

CAD16

// A17

CPERR

// A14

CDEV-

SEL //

A21

CFRAM

E // A23

CAD19

// A25

Figure 2−3. PCI6612 GHK/ZHK-Package Terminal Diagram

September 2005SCPS110

Introduction

12345678910111213141516171819

AD18 AD17 R0 R1

AD22 AD21 AD19 FRAME PERR AD14 AD8 AD5 AD0 CPS

VCCP C/BE3 AD23 AD20 VCC GND VCC GND VCC AD1 TEST0

AD26 AD25 AD24 IDSEL GND RSVD RSVD RSVD RSVD

AD31 AD30 AD29 AD27 AD28 GND RSVD RSVD RSVD RSVD

PCLK GNT REQ

VR_

VR_EN PRST GRST GND GND RSVD RSVD RSVD

PORT

AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N TPB1N TPA1N

IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P TPB1P TPA1P

DEV-

C/BE2

RI_OUT

/ PME

PAR AD13 AD9 AD6 AD2 NC AGND AGND

SEL

TPBIAS

AVDD_

_33

VCC VCC RSVD RSVD RSVD RSVD

AVDD_

_33

AGND VSSPLL XO XI

AVDD_

VDD

_33

PLL_15

TPBIAS

PHY_

TEST_

VDD

PLL_33

RSVD

VR_

PORT

MFUNC4MFUNC5MFUNC

MFUNC3MFUNC

MFUNC

CLK_48 RSVD RSVD RSVD VCC GND

RSVD RSVD RSVD NC

RSVD RSVD

SPKR

OUT

SCL SDA RSVD VCC GND RSVD RSVD RSVD RSVD

XD_CD

/ SM_

PHYS_

RSVD /

VD0 /

VCCD1

SM_ CLE

SD_

CLK /

SM_RE

SUS-

VCC VCC RSVD RSVD RSVD RSVD

PEND

MFUNC

GND RSVD RSVD RSVD RSVD RSVD

MC_

PWR_

CTRL_

VCC GND RSVD VCC GND VCC RSVD RSVD RSVD RSVD

1 /

SM_R/B

SD_WP

SM_CE

MS_

DATA1 /

SD_

DAT1 /

SM_D1

MS_

SDIO

(DATA0)

/ SD_

DAT0 /

SM_D0

MS_

CLK /

SD_

CLK /

SM_EL_

MS_BS

/ SD_

SD_CD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

CMD /

SM_WE

MC_

LATCH

PWR_

/ VD3 /

CTRL_

SM_CD

MS_CD

RSVD RSVD RSVD RSVD RSVD RSVD

VPPD0

DATA /

VD2 /

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VPPD1

CLOCK

/ VD1 /

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCD0

SD_

CMD /

SM_ ALE

SD_

DAT2 /

SM_D6

SD_

DAT1 /

SM_D5

SD_

DAT3 /

SM_D7

SD_

DAT0 /

SM_D4

MS_

DATA3 /

SD_

DAT3 /

SM_D3

MS_

DATA2 /

SD_

DAT2 /

SM_D2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Figure 2−4. PCI7402 GHK/ZHK-Package Terminal Diagram

September 2005 SCPS110

Introduction

12345678910111213141516171819

AD18 AD17 R0 R1

AD22 AD21 AD19 FRAME PERR AD14 AD8 AD5 AD0 CPS

VCCP C/BE3 AD23 AD20 VCC GND VCC GND VCC AD1 TEST0

AD26 AD25 AD24 IDSEL GND

AD31 AD30 AD29 AD27 AD28 GND

PCLK GNT REQ

VR_

VR_EN PRST GRST GND GND

PORT

AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N TPB1N TPA1N

IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P TPB1P TPA1P

DEV-

C/BE2

RI_OUT

/ PME

PAR AD13 AD9 AD6 AD2 NC AGND AGND

SEL

VCC VCC

TPBIAS

AVDD_

_33

AVDD_

_33

AGND VSSPLL XO XI

AVDD_

VDD

_33

PLL_15

CCD1 // CD1

CAD3

// D5

CAD9 // A10

CAD12

// A11

TPBIAS

PHY_

TEST_

CAD2 // D11

CAD6 // D13

CC/

BE0

CE1

CAD11

// OE

CAD1

// D4

CAD5

// D6

CAD8 // D15

CAD10

// CE2

VDD

PLL_33

CAD0

// D3

CAD4 // D12

RSVD

// D14

CAD7

// D7

VR_

PORT

CVS2 //

VS2

CAD20

// A6

CAD15

IOWR

RSVD // A18

CGNT // WE

CIRDY

// A15

CAD18

// A7

MFUNC4MFUNC5MFUNC

MFUNC3MFUNC

MFUNC

CLK_48 RSVD RSVD RSVD VCC GND

RSVD RSVD RSVD NC

RSVD

SPKR

OUT

SCL SDA RSVD VCC GND

XD_CD

/ SM_

PHYS_

RSVD /

VD0 /

VCCD1

SM_ CLE

SD_

CLK /

SM_RE

SUS-

PEND

MFUNC

SD_

CMD /

SM_ ALE

SD_ DAT2 / SM_D6

SD_ DAT1 / SM_D5

VCC VCC

GND

MC_

SD_

DAT3 /

SM_D7

SD_

DAT0 /

SM_D4

MS_

DATA3 /

SD_

DAT3 /

SM_D3

MS_

DATA2 /

SD_

DAT2 /

SM_D2

SD_WP

SM_CE

MS_

DATA1 /

SD_

DAT1 /

SM_D1

MS_

SDIO

(DATA0)

/ SD_

DAT0 /

SM_D0

MS_

CLK /

SD_

CLK /

SM_EL_

PWR_

CTRL_

1 /

SM_R/B

MS_BS

/ SD_

CMD /

SM_WE

MC_

PWR_

CTRL_

SM_CD

MS_CD

VCC GND

SD_CD

LATCH / VD3 / VPPD0

DATA /

VD2 /

VPPD1

CLOCK

/ VD1 /

VCCD0

CAD29

// D1

USB_ENCAD28

// D8

CAD31

CAD27

// D10

// D0

RSVD

CCD2

// D2

// CD2

CCLK

RUN //

CAD30

// D9

(IOIS16

VCC GND VCC

CINT //

CC/

READY

BE3

)

REG

(IREQ

CSERR

CAD25

// WAIT

// A1

CAU-

DIO //

CAD26

// A0

BVD2

)

(SPKR

CSTS

CHG //

CVS1 //

BVD1

VS1

(STSC

)

HG/RI)

CPAR

// A13

CAD21

// A5

CREQ

// IN-

PACK

CAD23

// A3

CAD24

// A2

CAD14

// A9

CBLOC K // A19

CTRDY

// A22

CAD17

// A24

CRST // RE-

SET

CAD22

// A4

VCCCB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CAD13 // IORD

CC/

BE1

CSTOP

// A20

CCLK // A16

CC/

BE2

A12

VCCCB

CAD16

// A17

CPERR

// A14

CDEV-

SEL //

A21

CFRAM

E // A23

CAD19

// A25

Figure 2−5. PCI7412 GHK/ZHK-Package Terminal Diagram

September 2005SCPS110

Introduction

12345678910111213141516171819

AD18 AD17 R0 R1

AD22 AD21 AD19 FRAME PERR AD14 AD8 AD5 AD0 CPS

VCCP C/BE3 AD23 AD20 VCC GND VCC GND VCC AD1 TEST0

AD26 AD25 AD24 IDSEL GND

AD31 AD30 AD29 AD27 AD28 GND

PCLK GNT REQ

VR_

VR_EN PRST GRST GND GND

PORT

AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N TPB1N TPA1N

IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P TPB1P TPA1P

DEV-

C/BE2

RI_OUT

/ PME

PAR AD13 AD9 AD6 AD2 NC AGND AGND

SEL

VCC VCC

TPBIAS

AVDD_

_33

AVDD_

_33

AGND VSSPLL XO XI

AVDD_

VDD

_33

PLL_15

CCD1 // CD1

CAD3

// D5

CAD9 // A10

CAD12

// A11

TPBIAS

PHY_

TEST_

CAD2 // D11

CAD6 // D13

CC/

BE0

CE1

CAD11

// OE

CAD1

// D4

CAD5

// D6

CAD8 // D15

CAD10

// CE2

VDD

PLL_33

CAD0

// D3

CAD4 // D12

RSVD // D14

CAD7

// D7

VR_

PORT

CVS2 //

VS2

CAD20

// A6

CAD15

IOWR

RSVD // A18

CGNT // WE

CIRDY

// A15

CAD18

// A7

MFUNC4MFUNC5MFUNC

MFUNC3MFUNC

MFUNC

CLK_48 SC_OC SC_CD

SC_

DATA

SC_

RFU

SPKR

OUT

SCL SDA

SC_

CLK

FCB

XD_CD

/ SM_

PHYS_

SUS-

RSVD /

VD0 /

VCCD1

SM_

CLE /

SC_

GPIO0

SD_

CLK /

SM_RE

/ SC_ GPIO1

VCC VCC

PEND

MFUNC

GND

SC_

PWR_

VCC_

CTRL

MC_

SD_WP

SM_CE

MS_

DATA1 /

SD_

DAT1 /

SM_D1

MS_

SDIO

(DATA0)

/ SD_

DAT0 /

SM_D0

MS_

CLK /

SD_

CLK /

SM_EL_

PWR_

CTRL_

1 /

SM_R/B MS_BS

/ SD_

CMD /

SM_WE

MC_

PWR_

CTRL_

SM_CD

MS_CD

VCC GND

SD_CD

LATCH

/ VD3 /

VPPD0

DATA /

VD2 /

VPPD1

CLOCK

/ VD1 /

VCCD0

CAD29

// D1

USB_ENCAD28

// D8

CAD31

CAD27

// D10

// D0

RSVD

CCD2

// D2

// CD2

CCLK

RUN //

CAD30

// D9

(IOIS16

)

SC_ RST

SD_

CMD /

SM_

ALE /

SC_

GPIO2

SD_

DAT2 /

SM_D6

/ SC_

GPIO4

SD_

DAT1 /

SM_D5

/ SC_

GPIO5

VCC GND

SD_

DAT3 /

SM_D7

/ SC_

GPIO3

SD_

DAT0 /

SM_D4

/ SC_

GPIO6

MS_

DATA3 /

SD_

DAT3 /

SM_D3

MS_

DATA2 /

SD_

DAT2 /

SM_D2

VCC GND VCC

CINT //

CC/

READY

(IREQ

CSERR // WAIT

CAUDIO // BVD2

(SPKR)

CSTS

CHG //

BVD1

(STSC HG/RI)

BE3

)

REG

CAD25

// A1

CAD26

// A0

CVS1 //

VS1

CPAR // A13

GND

CAD21

// A5

CREQ

// IN-

PACK

CAD23

// A3

CAD24

// A2

CAD14

// A9

CBLOC K // A19

CTRDY

// A22

CAD17

// A24

CRST // RE-

SET

CAD22

// A4

VCCCB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CAD13 // IORD

CC/

BE1

CSTOP

// A20

CCLK // A16

CC/

BE2

A12

VCCCB

CAD16

// A17

CPERR

// A14

CDEV-

SEL //

A21

CFRAM

E // A23

CAD19

// A25

Figure 2−6. PCI7612 GHK/ZHK-Package Terminal Diagram

September 2005 SCPS110

Introduction

12345678910111213141516171819

AD18 AD17 R0 R1

AD22 AD21 AD19 FRAME PERR AD14 AD8 AD5 AD0 CPS

VCCP C/BE3 AD23 AD20 VCC GND VCC GND VCC AD1 TEST0

AD26 AD25 AD24 IDSEL GND RSVD RSVD RSVD RSVD

AD31 AD30 AD29 AD27 AD28 GND RSVD RSVD RSVD RSVD

PCLK GNT REQ

VR_

VR_EN PRST GRST GND GND RSVD RSVD RSVD

PORT

AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N RSVD RSVD RSVD

IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P RSVD RSVD

DEV-

C/BE2

RI_OUT

/ PME

PAR AD13 AD9 AD6 AD2 NC AGND AGND

SEL

TPBIAS

AVDD_

_33

VCC VCC RSVD RSVD RSVD RSVD

AVDD_

_33

AGND VSSPLL XO XI

AVDD_

_33

VDD

PLL_15

PHY_

TEST_

VDD

PLL_33

RSVD

VR_

PORT

MFUNC4MFUNC5MFUNC

MFUNC3MFUNC

MFUNC

CLK_48 RSVD RSVD RSVD VCC GND

RSVD RSVD RSVD NC

RSVD RSVD

SPKR

OUT

SCL SDA RSVD VCC GND RSVD RSVD RSVD RSVD

XD_CD

/ SM_

PHYS_

RSVD /

VD0 /

VCCD1

SM_ CLE

SD_

CLK /

SM_RE

SUS-

VCC VCC RSVD RSVD RSVD RSVD

PEND

MFUNC

GND RSVD RSVD RSVD RSVD RSVD

MC_

PWR_

CTRL_

VCC GND RSVD VCC GND VCC RSVD RSVD RSVD RSVD

1 /

SM_R/B

SD_WP

SM_CE

MS_

DATA1 /

SD_

DAT1 /

SM_D1

MS_

SDIO

(DATA0)

/ SD_

DAT0 /

SM_D0

MS_

CLK /

SD_

CLK /

SM_EL_

MS_BS

/ SD_

SD_CD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

CMD /

SM_WE

MC_

LATCH

PWR_

/ VD3 /

CTRL_

SM_CD

MS_CD

RSVD RSVD RSVD RSVD RSVD RSVD

VPPD0

DATA /

VD2 /

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VPPD1

CLOCK

/ VD1 /

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCD0

SD_

CMD /

SM_ ALE

SD_ DAT2 / SM_D6

SD_ DAT1 / SM_D5

SD_

DAT3 /

SM_D7

SD_

DAT0 /

SM_D4

MS_

DATA3 /

SD_

DAT3 /

SM_D3

MS_

DATA2 /

SD_

DAT2 /

SM_D2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Figure 2−7. PCI8402 GHK/ZHK-Package Terminal Diagram

September 2005SCPS110

Introduction

12345678910111213141516171819

AD18 AD17 R0 R1

AD22 AD21 AD19 FRAME PERR AD14 AD8 AD5 AD0 CPS

VCCP C/BE3 AD23 AD20 VCC GND VCC GND VCC AD1 TEST0

AD26 AD25 AD24 IDSEL GND

AD31 AD30 AD29 AD27 AD28 GND

PCLK GNT REQ

VR_

VR_EN PRST GRST GND GND

PORT

AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 NC TPB0N TPA0N RSVD RSVD RSVD

IRDY STOP C/BE1 AD12 AD10 AD7 AD3 NC TPB0P TPA0P RSVD RSVD

DEV-

C/BE2

RI_OUT

/ PME

PAR AD13 AD9 AD6 AD2 NC AGND AGND

SEL

VCC VCC

TPBIAS

AVDD_

_33

AVDD_

_33

AGND VSSPLL XO XI

AVDD_

_33

VDD

PLL_15

CCD1 // CD1

CAD3

// D5

CAD9 // A10

CAD12

// A11

PHY_

TEST_

CAD2 // D11

CAD6 // D13

CC/

BE0

CE1

CAD11

// OE

CAD1

// D4

CAD5

// D6

CAD8 // D15

CAD10

// CE2

VDD

PLL_33

CAD0

// D3

CAD4 // D12

RSVD // D14

CAD7

// D7

VR_

PORT

CVS2 //

VS2

CAD20

// A6

CAD15

IOWR

RSVD // A18

CGNT // WE

CIRDY

// A15

CAD18

// A7

MFUNC4MFUNC5MFUNC

MFUNC3MFUNC

MFUNC

CLK_48 RSVD RSVD RSVD VCC GND

RSVD RSVD RSVD NC

RSVD

SPKR

OUT

SCL SDA RSVD VCC GND

XD_CD

/ SM_

PHYS_

RSVD /

VD0 /

VCCD1

SM_ CLE

SD_

CLK /

SM_RE

SUS-

PEND

MFUNC

SD_

CMD /

SM_ ALE

SD_

DAT2 /

SM_D6

SD_

DAT1 /

SM_D5

VCC VCC

GND

MC_

SD_

DAT3 /

SM_D7

SD_

DAT0 /

SM_D4

MS_

DATA3 /

SD_

DAT3 /

SM_D3

MS_

DATA2 /

SD_

DAT2 /

SM_D2

SD_WP

SM_CE

MS_

DATA1 /

SD_

DAT1 /

SM_D1

MS_

SDIO

(DATA0)

/ SD_

DAT0 /

SM_D0

MS_

CLK /

SD_

CLK /

SM_EL_

PWR_

CTRL_

1 /

SM_R/B MS_BS

/ SD_

CMD /

SM_WE

MC_

PWR_

CTRL_

SM_CD

MS_CD

VCC GND

SD_CD

LATCH

/ VD3 /

VPPD0

DATA /

VD2 /

VPPD1

CLOCK

/ VD1 /

VCCD0

CAD29

// D1

USB_ENCAD28

// D8

CAD31

CAD27

// D10

// D0

RSVD

CCD2

// D2

// CD2

CCLK

RUN //

CAD30

// D9

(IOIS16

VCC GND VCC

CINT //

CC/

READY

BE3

)

REG

(IREQ

CSERR

CAD25

// WAIT

// A1

CAU-

DIO //

CAD26

// A0

BVD2

)

(SPKR

CSTS

CHG //

CVS1 //

BVD1

VS1

(STSC

)

HG/RI)

CAD21

CAD23

CAD24

CPAR // A13

// A5

CREQ

// IN-

PACK

// A3

// A2

CAD14

// A9

CBLOC K // A19

CTRDY

// A22

CAD17

// A24

CRST // RE-

SET

CAD22

// A4

VCCCB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CAD13 // IORD

CC/

BE1

CSTOP

// A20

CCLK // A16

CC/

BE2

A12

VCCCB

CAD16

// A17

CPERR

// A14

CDEV-

SEL //

A21

CFRAM

E // A23

CAD19

// A25

Figure 2−8. PCI8412 GHK/ZHK-Package Terminal Diagram

September 2005 SCPS110

Introduction

Table 2−3 lists the terminal assignments arranged in terminal-number order, with corresponding signal names for both CardBus and 16-bit PC Cards for the PCIxx12 GHK packages. Table 2−4 and Table 2−5 list the terminal assignments arranged in alphanumerical order by signal name, with corresponding terminal numbers for the GHK package; Table 2−4 is for CardBus signal names and Table 2−5 is for 16-bit PC Card signal names.

Terminal E5 on the GHK package is an identification ball used for device orientation.

September 2005SCPS110

Introduction

TERMINAL

Table 2−3. Signal Names by GHK Terminal Number

SIGNAL NAME

NUMBER

A03 XD_CD /

A04 SD_CLK / SM_RE /

A05 SD_DAT1 / SM_D5 /

A06 MS_DATA2 / SD_DAT2

A07 MS_CLK / SD_CLK /

A08 MS_CD MS_CD D01 SC_RFU SC_RFU A09 CLOCK / VD1 / VCCD0 CLOCK / VD1 / VCCD0 D19 CAD19 A25 A10 CAD30 D9 E01 SC_DATA SC_DATA A11 CCLKRUN WP(IOIS16) E02 SC_CLK SC_CLK A12 CSTSCHG BVD1(STSCHG/RI) E03 SC_FCB SC_FCB A13 CVS1 VS1 E05 NC NC A14 CAD24 A2 E06 SD_DAT3 / SM_D7 /

A15 VCCCB VCCCB E07 SD_WP / SM_CE SD_WP / SM_CE A16 CAD20 A6 E08 MS_BS / SD_CMD /

B04 SM_CLE / SC_GPIO0 SM_CLE / SC_GPIO0 E09 SD_CD SD_CD B05 SD_DAT2 / SM_D6 /

B06 MS_DATA3 / SD_DAT3

B07 MS_SDIO(DATA0) /

B08 SM_CD SM_CD E13 CC/BE3 REG B09 DATA / VD2 / VPPD1 DATA / VD2 / VPPD1 E14 CAD21 A5 B10 RSVD D2 E17 CAD18 A7 B11 CCD2 CD2 E18 CC/BE2 A12 B12 CAUDIO BVD2(SPKR) E19 CFRAME A23 B13 CAD26 A0 F01 CLK_48 CLK_48 B14 CAD23 A3 F02 SC_OC SC_OC B15 CAD22 A4 F03 SC_CD SC_CD B16 CVS2 VS2 F05 SC_RST SC_RST C04 RSVD / VD0 / VCCD1 RSVD / VD0 / VCCD1 F06 VCC VCC C05 SD_CMD / SM_ALE /

C06 SD_DAT0 / SM_D4 /

C07 MS_DATA1 / SD_DAT1

C08 MC_PWR_CTRL_0 MC_PWR_CTRL_0 F10 GND GND C09 LATCH / VD3 / VPPD0 LATCH / VD3 / VPPD0 F11 CAD29 D1 C10 CAD31 D10 F12 VCC VCC

CardBus PC Card 16-Bit PC Card

SM_PHYS_WP

SC_GPIO1

SC_GPIO5

/ SM_D2

SM_EL_WP

SC_GPIO4

/ SM_D3

SD_DAT0 / SM_D0

SC_GPIO2

SC_GPIO6

/ SM_D1

XD_CD /

SM_PHYS_WP

SD_CLK / SM_RE /

SC_GPIO1

SD_DAT1 / SM_D5 /

SC_GPIO5

MS_DATA2 / SD_DAT2

/ SM_D2

MS_CLK / SD_CLK /

SM_EL_WP

SD_DAT2 / SM_D6 /

SC_GPIO4

MS_DATA3 / SD_DAT3

/ SM_D3

MS_SDIO(DATA0) /

SD_DAT0 / SM_D0

SD_CMD / SM_ALE /

SC_GPIO2

SD_DAT0 / SM_D4 /

SC_GPIO6

MS_DATA1 / SD_DAT1

/ SM_D1

NUMBER

C11 CAD27 D0

C12 CSERR WAIT

C13 CAD25 A1

C14 CREQ INPACK

C15 CRST RESET

E10 USB_EN USB_EN

E11 CAD28 D8

E12 CINT READY(IREQ)

F07 GND GND

F08 MC_PWR_CTRL_1 /

F09 VCC VCC

CardBus PC Card 16-Bit PC Card

SC_GPIO3

SM_WE

SM_R/B

SIGNAL NAME

SD_DAT3 / SM_D7 /

SC_GPIO3

MS_BS / SD_CMD /

SM_WE

MC_PWR_CTRL_1 /

SM_R/B

September 2005 SCPS110

Introduction

TERMINAL

Table 2−3. Signal Names by GHK Terminal Number (Continued)

SIGNAL NAME

NUMBER

F13 GND GND K17 CAD11 OE F14 VCC VCC K18 CAD10 CE2 F15 CAD17 A24 K19 VR_PORT VR_PORT F17 CIRDY A15 L01 PCLK PCLK F18 CCLK A16 L02 GNT GNT F19 CDEVSEL A21 L03 REQ REQ G01 MFUNC0 MFUNC0 L05 RI_OUT/PME RI_OUT/PME G02 SCL SCL L06 VCC VCC G03 SDA SDA L14 VCC VCC G05 SC_PWR_CTRL SC_PWR_CTRL L15 CAD9 A10 G06 SC_VCC_5V SC_VCC_5V L17 CC/BE0 CE1 G14 GND GND L18 CAD8 D15 G15 CTRDY A22 L19 CAD7 D7 G17 CGNT WE M01 AD31 AD31 G18 CSTOP A20 M02 AD30 AD30 G19 CPERR A14 M03 AD29 AD29 H01 MFUNC3 MFUNC3 M05 AD27 AD27 H02 MFUNC2 MFUNC2 M06 AD28 AD28 H03 SPKROUT SPKROUT M14 GND GND H05 MFUNC1 MFUNC1 M15 CAD3 D5 H06 GND GND M17 CAD6 D13 H14 CPAR A13 M18 CAD5 D6 H15 CBLOCK A19 M19 RSVD D14 H17 RSVD A18 N01 AD26 AD26 H18 CC/BE1 A8 N02 AD25 AD25 H19 CAD16 A17 N03 AD24 AD24

J01 MFUNC4 MFUNC4 N05 IDSEL IDSEL J02 MFUNC5 MFUNC5 N06 GND GND J03 MFUNC6 MFUNC6 N15 CCD1 CD1 J05 SUSPEND SUSPEND N17 CAD2 D11 J06 VCC VCC N18 CAD1 D4 J14 VCC VCC N19 CAD4 D12 J15 CAD14 A9 P01 VCCP VCCP J17 CAD15 IOWR P02 C/BE3 C/BE3 J18 CAD13 IORD P03 AD23 AD23

J19 VCCCB VCCCB P05 AD20 AD20 K01 VR_PORT VR_PORT P06 VCC VCC K02 VR_EN VR_EN P07 GND GND K03 PRST PRST P08 VCC VCC K05 GRST GRST P09 GND GND K06 GND GND P10 VCC VCC K14 GND GND P11 AD1 AD1 K15 CAD12 A11 P12 TEST0 TEST0

CardBus PC Card 16-Bit PC Card

NUMBER

CardBus PC Card 16-Bit PC Card

SIGNAL NAME

September 2005SCPS110

Table 2−3. Signal Names by GHK Terminal Number (Continued)

TERMINAL

SIGNAL NAME

NUMBER

P13 AVDD_33 AVDD_33 U12 NC NC P14 AVDD_33 AVDD_33 U13 AGND AGND P15 VDDPLL_15 VDDPLL_15 U14 AGND AGND P17 PHY_TEST_MA PHY_TEST_MA U15 AVDD_33 AVDD_33 P19 CAD0 D3 U19 VDDPLL_33 VDDPLL_33 R01 AD22 AD22 V05 IRDY IRDY R02 AD21 AD21 V06 STOP STOP R03 AD19 AD19 V07 C/BE1 C/BE1 R06 FRAME FRAME V08 AD12 AD12 R07 PERR PERR V09 AD10 AD10 R08 AD14 AD14 V10 AD7 AD7 R09 AD8 AD8 V11 AD3 AD3 R10 AD5 AD5 V12 NC NC R11 AD0 AD0 V13 TPB0P TPB0P R12 CPS CPS V14 TPA0P TPA0P R13 TPBIAS0 TPBIAS0 V15 TPB1P TPB1P R14 AGND AGND V16 TPA1P TPA1P R17 VSSPLL VSSPLL W04 AD16 AD16 R18 XO XO W05 TRDY TRDY R19 XI XI W06 SERR SERR T01 AD18 AD18 W07 AD15 AD15 T02 AD17 AD17 W08 VCCP VCCP T18 R0 R0 W09 AD11 AD11 T19 R1 R1 W10 C/BE0 C/BE0 U05 C/BE2 C/BE2 W11 AD4 AD4 U06 DEVSEL DEVSEL W12 NC NC U07 PAR PAR W13 TPB0N TPB0N U08 AD13 AD13 W14 TPA0N TPA0N U09 AD9 AD9 W15 TPB1N TPB1N U10 AD6 AD6 W16 TPA1N TPA1N U11 AD2 AD2 W17 TPBIAS1 TPBIAS1

CardBus PC Card 16-Bit PC Card

NUMBER

CardBus PC Card 16-Bit PC Card

SIGNAL NAME

Introduction

September 2005 SCPS110

Introduction

Table 2−4. CardBus PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

AD0 R11 CAD5 M18 CGNT G17 AD1 P11 CAD6 M17 CINT E12 AD2 U11 CAD7 L19 CIRDY F17 AD3 V11 CAD8 L18 CLK_48 F01 AD4 W11 CAD9 L15 CLOCK / VD1 / VCCD0 A09 AD5 R10 CAD10 K18 CPAR H14 AD6 U10 CAD11 K17 CPERR G19 AD7 V10 CAD12 K15 CPS R12 AD8 R09 CAD13 J18 CREQ C14

AD9 U09 CAD14 J15 CRST C15 AD10 V09 CAD15 J17 CSERR C12 AD11 W09 CAD16 H19 CSTOP G18 AD12 V08 CAD17 F15 CSTSCHG A12 AD13 U08 CAD18 E17 CTRDY G15 AD14 R08 CAD19 D19 CVS1 A13 AD15 W07 CAD20 A16 CVS2 B16 AD16 W04 CAD21 E14 DATA / VD2 / VPPD1 B09 AD17 T02 CAD22 B15 DEVSEL U06 AD18 T01 CAD23 B14 FRAME R06 AD19 R03 CAD24 A14 GND F07 AD20 P05 CAD25 C13 GND F10 AD21 R02 CAD26 B13 GND F13 AD22 R01 CAD27 C11 GND G14 AD23 P03 CAD28 E11 GND H06 AD24 N03 CAD29 F11 GND K06 AD25 N02 CAD30 A10 GND K14 AD26 N01 CAD31 C10 GND M14 AD27 M05 CAUDIO B12 GND N06 AD28 M06 C/BE0 W10 GND P07 AD29 M03 C/BE1 V07 GND P09 AD30 M02 C/BE2 U05 GNT L02 AD31 M01 C/BE3 P02 GRST K05

AGND R14 CBLOCK H15 IDSEL N05 AGND U13 CC/BE0 L17 IRDY V05

AGND U14 CC/BE1 H18 LATCH / VD3 / VPPD0 C09 AVDD_33 P13 CC/BE2 E18 MC_PWR_CTRL_0 C08 AVDD_33 P14 CC/BE3 E13 MC_PWR_CTRL_1 /

AVDD_33 U15 CCD1 N15 MFUNC0 G01

CAD0 P19 CCD2 B11 MFUNC1 H05 CAD1 N18 CCLK F18 MFUNC2 H02 CAD2 N17 CCLKRUN A11 MFUNC3 H01 CAD3 M15 CDEVSEL F19 MFUNC4 J01 CAD4 N19 CFRAME E19 MFUNC5 J02

TERMINAL

NUMBER

SIGNAL NAME

TERMINAL

NUMBER

SIGNAL NAME

SM_R/B

TERMINAL

NUMBER

F08

September 2005SCPS110

Introduction

Table 2−4. CardBus PC Card Signal Names Sorted Alphabetically (Continued)

SIGNAL NAME

MFUNC6 J03 SCL G02 TPB0P V13

MS_BS / SD_CMD /

SM_WE MS_CD A08 SC_PWR_CTRL G05 TPB1P V15

MS_CLK / SD_CLK /

SM_EL_WP

MS_DATA1 / SD_DAT1

/ SM_D1

MS_DATA2 / SD_DAT2

/ SM_D2

MS_DATA3 / SD_DAT3

/ SM_D3

MS_SDIO(DATA0) /

SD_DAT0 / SM_D0

NC E05 SD_CLK / SM_RE /

NC U12 SD_CMD / SM_ALE /

NC V12 SD_DAT0 / SM_D4 /

NC W12 SD_DAT1 / SM_D5 /

PAR U07 SD_DAT2 / SM_D6 /

PCLK L01 SD_DAT3 / SM_D7 /

PERR R07 SD_WP / SM_CE E07 VCC P08

PHY_TEST_MA P17 SERR W06 VCC P10

PRST K03 SM_CD B08 VCCCB A15

REQ L03 SM_CLE / SC_GPIO0 B04 VCCCB J19

RI_OUT/PME L05 SPKROUT H03 VCCP P01

RSVD B10 STOP V06 VCCP W08 RSVD H17 SUSPEND J05 VDDPLL_15 P15 RSVD M19 TEST0 P12 VDDPLL_33 U19

RSVD / VD0 / VCCD1 C04 TPA0N W14 VR_EN K02

R0 T18 TPA0P V14 VR_PORT K01 R1 T19 TPA1N W16 VR_PORT K19

SC_CD F03 TPA1P V16 VSSPLL R17

SC_CLK E02 TPBIAS0 R13 XD_CD /

SC_DATA E01 TPBIAS1 W17 XI R19

SC_FCB E03 TPB0N W13 XO R18

TERMINAL

NUMBER

E08 SC_OC F02 TPB1N W15

A07 SC_RFU D01 TRDY W05

C07 SC_RST F05 USB_EN E10

A06 SC_VCC_5V G06 VCC F06

B06 SDA G03 VCC F09

B07 SD_CD E09 VCC F12

SIGNAL NAME

SC_GPIO1

SC_GPIO2

SC_GPIO6

SC_GPIO5

SC_GPIO4

SC_GPIO3

TERMINAL

NUMBER

A04 VCC F14

C05 VCC J06

C06 VCC J14

A05 VCC L06

B05 VCC L14

E06 VCC P06

SIGNAL NAME

SM_PHYS_WP

TERMINAL

NUMBER

A03

September 2005 SCPS110

Introduction

Table 2−5. 16-Bit PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

AD0 R11 A4 B15 D5 M15 AD1 P11 A5 E14 D6 M18 AD2 U11 A6 A16 D7 L19 AD3 V11 A7 E17 D8 E11 AD4 W11 A8 H18 D9 A10 AD5 R10 A9 J15 D10 C10 AD6 U10 A10 L15 D11 N17 AD7 V10 A11 K15 D12 N19 AD8 R09 A12 E18 D13 M17

AD9 U09 A13 H14 D14 M19 AD10 V09 A14 G19 D15 L18 AD11 W09 A15 F17 FRAME R06 AD12 V08 A16 F18 GND F07 AD13 U08 A17 H19 GND F10 AD14 R08 A18 H17 GND F13 AD15 W07 A19 H15 GND G14 AD16 W04 A20 G18 GND H06 AD17 T02 A21 F19 GND K06 AD18 T01 A22 G15 GND K14 AD19 R03 A23 E19 GND M14 AD20 P05 A24 F15 GND N06 AD21 R02 A25 D19 GND P07 AD22 R01 BVD1(STSCHG/RI) A12 GND P09 AD23 P03 BVD2(SPKR) B12 GNT L02 AD24 N03 C/BE0 W10 GRST K05 AD25 N02 C/BE1 V07 IDSEL N05 AD26 N01 C/BE2 U05 INPACK C14 AD27 M05 C/BE3 P02 IORD J18 AD28 M06 CD1 N15 IOWR J17 AD29 M03 CD2 B11 IRDY V05 AD30 M02 CE1 L17 LATCH / VD3 / VPPD0 C09 AD31 M01 CE2 K18 MC_PWR_CTRL_0 C08

AGND R14 CLK_48 F01 MC_PWR_CTRL_1 /

AGND U13 CLOCK / VD1 / VCCD0 A09 MFUNC0 G01

AGND U14 CPS R12 MFUNC1 H05 AVDD_33 P13 DATA / VD2 / VPPD1 B09 MFUNC2 H02 AVDD_33 P14 DEVSEL U06 MFUNC3 H01 AVDD_33 U15 D0 C11 MFUNC4 J01

A0 B13 D1 F11 MFUNC5 J02 A1 C13 D2 B10 MFUNC6 J03 A2 A14 D3 P19 MS_CD A08 A3 B14 D4 N18 MS_BS / SD_CMD /

TERMINAL

NUMBER

SIGNAL NAME

TERMINAL

NUMBER

SIGNAL NAME

SM_R/B

SM_WE

TERMINAL

NUMBER

F08

E08

September 2005SCPS110

Introduction

Table 2−5. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)

SIGNAL NAME

MS_CLK / SD_CLK /

SM_EL_WP

MS_DATA1 / SD_DAT1

/ SM_D1

MS_DATA2 / SD_DAT2

/ SM_D2

MS_DATA3 / SD_DAT3

/ SM_D3

MS_SDIO(DATA0) /

SD_DAT0 / SM_D0

NC E05 SD_CLK / SM_RE /

NC U12 SD_CMD / SM_ALE /

NC V12 SD_DAT0 / SM_D4 /

NC W12 SD_DAT1 / SM_D5 /

OE K17 SD_DAT2 / SM_D6 /

PAR U07 SD_DAT3 / SM_D7 /

PCLK L01 SD_WP / SM_CE E07 VCC P10

PERR R07 SERR W06 VCCCB A15

PHY_TEST_MA P17 SM_CD B08 VCCCB J19

PRST K03 SM_CLE / SC_GPIO0 B04 VCCP P01

READY(IREQ) E12 SPKROUT H03 VCCP W08

REG E13 STOP V06 VDDPLL_15 P15 REQ L03 SUSPEND J05 VDDPLL_33 U19

RI_OUT/PME L05 TEST0 P12 VR_EN K02

RESET C15 TPA0N W14 VR_PORT K01

RSVD / VD0 / VCCD1 C04 TPA0P V14 VR_PORT K19

R0 T18 TPA1N W16 VSSPLL R17 R1 T19 TPA1P V16 VS1 A13

SC_CD F03 TPBIAS0 R13 VS2 B16

SC_CLK E02 TPBIAS1 W17 WAIT C12

SC_DATA E01 TPB0N W13 WE G17

SC_FCB E03 TPB0P V13 WP(IOIS16) A11

SCL G02 TPB1N W15 XD_CD /

SC_OC F02 TPB1P V15 XI R19

SC_PWR_CTRL G05 TRDY W05 XO R18

TERMINAL

NUMBER

A07 SC_RFU D01 USB_EN E10

C07 SC_RST F05 VCC F06

A06 SC_VCC_5V G06 VCC F09

B06 SDA G03 VCC F12

B07 SD_CD E09 VCC F14

SIGNAL NAME

SC_GPIO1

SC_GPIO2

SC_GPIO6

SC_GPIO5

SC_GPIO4

SC_GPIO3

TERMINAL

NUMBER

A04 VCC J06

C05 VCC J14

C06 VCC L06

A05 VCC L14

B05 VCC P06

E06 VCC P08

SIGNAL NAME

SM_PHYS_WP

TERMINAL

NUMBER

A03

September 2005 SCPS110

Introduction

2.9 Detailed Terminal Descriptions

Please see Table 2−6 through Table 2−24 for more detailed terminal descriptions. The following list defines the column headings and the abbreviations used in the detailed terminal description tables.

• I/O Type:

− I = Digital input

− O = Digital output

− I/O = Digital input/output

− AI = Analog input

− PWR = Power

− GND = Ground

• Input/Output Description:

− AF = Analog feedthrough

− TTLI1 = 5-V tolerant TTL input buffer

− TTLI2 = 5-V tolerant TTL input buffer with hysteresis

− TTLO1 = 5-V tolerant low−noise 4−mA TTL output buffer

− PCII1 = 3.3-V PCI input buffer

− PCII3 = Universal 5-V tolerant PCI input buffer

− PCII4 = 5-V tolerant PCMCIA input buffer

− PCII5 = 5-V Smart Card input buffer

− PCII6 = 5-V tolerant PCMCIA input buffer, failsafe

− PCII7 = 5-V tolerant PCIMCIA input buffer

− PCIO1 = 3.3-V PCI output buffer

− PCIO3 = Universal 5-V tolerant PCI output buffer

− PCIO4 = 5-V tolerant PCMCIA output buffer

− PCIO5 = 5-V Smart Card output buffer

− PCIO6 = 5-V Smart Card output buffer

− PCIO7 = 5-V tolerant PCMCIA output buffer

− PCIO8 = 5-V Smart Card output buffer

− LVCI1 = LVCMOS input buffer

− LVCI2 = LVCMOS input buffer with hysteresis, failsafe

− LVCI3 = LVCMOS input buffer with hysteresis

− LVCO1 = Low-noise 4-mA LVCMOS output buffer

− LVCO2 = Low-noise 4-mA LVCMOS open drain output buffer

− LVCO3 = Low-noise 8-mA LVCMOS output buffer

− TP = 1394a transceiver

• PU/PD signifies whether the terminal has an internal pullup or pulldown resistor. These pullups are disabled and enabled by design when appropriate to preserve power.

− PD1 = 20-µA pulldown

− PD2 = 100-µA pulldown

− PU2 = 100-µA pullup

− PU4 = 5-V tolerant 100-µA pullup

− PU5 = 100-µA pullup

September 2005SCPS110

Introduction

I/O

EXTERNAL

PIN STRAPPING

I/O

EXTERNAL

PIN STRAPPING

− SW1 = Switchable 50-µA pullup/200-µA pulldown implemented depending on situation

− SW2 = Switchable 100-µA pullup/100-µA pulldown implemented depending on situation

− SW3 = Switchable 200-µA pullup/200-µA pulldown implemented depending on situation

• Power Rail signifies which rail the terminal is clamped to for protection.

• External Components signifies any external components needed for normal operation.

• Pin Strapping (If Unused) signifies how the terminal must be implemented if its function is not needed.

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference.

Table 2−6. Power Supply Terminals

Output description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the power supply terminals.

TERMINAL

NAME NUMBER

AGND R14, U13, U14 Analog circuit ground terminals GND NA

Analog circuit power terminals. A parallel combination of high frequency decoupling capacitors near each terminal is

AVDD_33 P13, P14, U15

F07, F10, F13,

GND

VCCCB A15, J19

CCP

VDDPLL_15 P15

VDDPLL_33 U19

VR_EN K02 Internal voltage regulator enable. Active low AF

VSSPLL R17

VR_PORT K01, K19 1.5-V output from the internal voltage regulator PWR

G14, H06, K06, K14, M14, N06,

P07, P09

F06, F09, F12,

F14, J06, J14,

L06, L14, P06,

P08, P10

P01, W08 Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V PWR NA

suggested, such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from VDDPLL_33 internal to the controller to provide noise isolation. They must be tied to a low-impedance point on the circuit board.

Digital ground terminal GND NA

Power supply terminal for I/O and internal voltage regulator PWR

Clamp voltage for PC Card interface. Matches card signaling environment, 5 V or 3.3 V

1.5-V PLL circuit power terminal. An external capacitor (0.1 µF recommended) must be placed between terminals T18 and R17 (VSSPLL) when the internal voltage regulator is enabled (VR_EN

= 0 V). When the internal voltage regulator is disabled,

1.5-V must be supplied to this terminal and a parallel combination of high frequency decoupling capacitors near the terminal is suggested, such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended.

3.3-V PLL circuit power terminal. A parallel combination of high frequency decoupling capacitors near the terminal is suggested, such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. This supply terminal is separated from AVDD internal to the controller to provide noise isolation. It must be tied to a low-impedance point on the circuit board. When the internal voltage regulator is disabled (VR_EN supplied to this terminal.

PLL circuit ground terminal. This terminal must be tied to the low-impedance circuit board ground plane.

DESCRIPTION

= 3.3 V), no voltage is required to be

INPUT

TYPE

GND

PWR

GND NA

COMPONENTS

0.1-µF, 0.001-µF, and 10-µF capacitors tied to AGND

0.1-µF and

0.001-µF decoupling capacitors

0.1-µF capacitor tied to GND

0.1-µF, 0.001-µF, and 10-µF capacitors tied to VSSPLL

Pulled directly to GND

0.1-µF capacitor tied to GND

(IF UNUSED)

Float

September 2005 SCPS110

Introduction

I/O

EXTERNAL

I/O

EXTERNAL

I/O

DESCRIPTION

INPUT

OUTPUT

I/O

POWER

EXTERNAL

I/O

POWER

EXTERNAL

Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch terminals.

TERMINAL

NAME NO.

CLOCK A09

DATA B09

LATCH C09

Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch terminals.

TERMINAL

NAME NO.

VD1/VCCD0 VD0/VCCD1

VD3/VPPD0 VD2/VPPD1

Table 2−7. Serial PC Card Power Switch Terminals

DESCRIPTION

Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to an output by using bit 27 (P2CCLK) in the system control register (offset 80h, see Section 4.29).

Power switch data. DATA is used to communicate socket power control information serially to the power switch.

Power switch latch. LATCH is asserted by the controller to indicate to the power switch that the data on the DATA line is valid.

Table 2−8. Parallel PC Card Power Switch Terminals

Logic controls to the TPS2211A PC Card power interface switch to control V

A09 C04

C09 B09

RSVD/VD0/VCCD1

I/O

pulled up, the power switch interface uses the 3-pin serial power interface. If it is pulled down, the power switch interface uses the 4-pin parallel power switch interface.

Logic controls to the TPS2211A PC Card power interface switch to control VPP

(terminal C04) controls the power switch interface mode. If it is

INPUT OUTPUT

TYPE

I/O TTLI1 TTLO1

O LVCO1

CCCB

TTLI1 LVCI1

COMPONENTS

PCMCIA power switch

TTLO1 LVCO1

LVCO1 LVCO1

Table 2−9. PCI System Terminals

Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI terminals.

TERMINAL

NAME NO.

GRST K05

PCLK L01

PRST

K03

Global reset. When the global reset is asserted, the GRST signal causes the controller to place all output buffers in a high-impedance state and reset all internal registers. When GRST systems that require wake-up from D3, GRST boot. PRST when transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST protected from the GRST placed in a high-impedance state, but the contents of the registers are preserved.

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK.

PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to place all output buffers in a high-impedance state and reset some internal registers. When PRST deasserted, the controller is in a default state. When SUSPEND clearing the internal registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

must be asserted following initial boot so that PME context is retained

must be tied to PRST. When the SUSPEND mode is enabled, the controller is

is asserted, the controller is completely nonfunctional. After PRST is

is asserted, the controller is completely in its default state. For

, and the internal registers are preserved. All outputs are

and PRST are asserted, the controller is protected from PRST

DESCRIPTION

is normally asserted only during initial

TYPE

I LVCI2

I PCII3 V

INPUT

RAIL

CCP

COMPONENTS

Power-on reset or tied to PRST

September 2005SCPS110

Table 2−10. PCI Address and Data Terminals

I/O

POWER

I/O

POWER

Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI address and data terminals.

TERMINAL

NAME NO.

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00

C/BE3 C/BE2 C/BE1 C/BE0

PAR U07

M01 M02 M03 M06 M05 N01 N02 N03

P03 R01 R02

P05 R03

T01

T02

W04 W07

R08 U08

V08

W09

V09 U09 R09

V10 U10 R10 W11

V11

U11

P11

R11

P02 U05

V07

W10

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary-bus PCI cycle, AD31−AD0 contain a 32-bit address or other destination information. During the data phase, AD31−AD0 contain data.

PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary-bus PCI cycle, C/BE3 command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable determines which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 byte 0 (AD7−AD0), C/BE1 (AD23−AD16), and C/BE3

PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across the AD31−AD0 and C/BE3 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the controller compares its calculated parity to the parity indicator of the initiator. A compare error results in the assertion of a parity error (PERR

applies to byte 1 (AD15−AD8), C/BE2 applies to byte 2 applies to byte 3 (AD31−AD24).

−C/BE0 buses. As an initiator during PCI cycles, the controller

DESCRIPTION

−C/BE0 define the bus

applies to

INPUT OUTPUT

TYPE

I/O PCII3 PCIO3 V

Introduction

RAIL

CCP

September 2005 SCPS110

Introduction

I/O

POWER

EXTERNAL

I/O

POWER

EXTERNAL

Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI interface control terminals.

TERMINAL

NAME NO.

DEVSEL

FRAME

GNT

IDSEL N05

IRDY

PERR

REQ

SERR

STOP

TRDY

Table 2−11. PCI Interface Control Terminals

DESCRIPTION

PCI device select. The controller asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the controller monitors

U06

DEVSEL

until a target responds. If no target responds before timeout

occurs, then the controller terminates the cycle with an initiator abort. PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME

is asserted to indicate that a bus transaction is beginning, and data

R06

transfers continue while this signal is asserted. When FRAME deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the controller access to the PCI bus after the current data transaction has

L02

completed. GNT the PCI bus parking algorithm.

Initialization device select. IDSEL selects the controller during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY

V05

asserted. Until IRDY are inserted.

PCI parity error indicator. PERR is driven by a PCI controller to indicate that calculated parity does not match PAR when PERR

R07

through bit 6 of the command register (PCI offset 04h, see Section 4.4). PCI bus request. REQ is asserted by the controller to request access to

L03

the PCI bus as an initiator. PCI system error. SERR is an output that is pulsed from the controller

when enabled through bit 8 of the command register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The controller need

W06

not be the target of the PCI cycle to assert this signal. When SERR enabled in the command register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP

V06

disconnects and is commonly asserted by target devices that do not support burst data transfers.

PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY

W05

asserted. Until both IRDY inserted.

may or may not follow a PCI bus request, depending on

and TRDY are

and TRDY are both sampled asserted, wait states

is used for target

and TRDY are

and TRDY are asserted, wait states are

is enabled

INPUT OUTPUT

TYPE

I/O PCII3 PCIO3 V

I PCII3 V

I/O PCII3 PCIO3 V

O PCIO3 V

I/O PCII3 PCIO3 V

RAIL

CCP

COMPONENTS

Pullup resistor per PCI specification

September 2005SCPS110

Table 2−12. Multifunction and Miscellaneous Terminals

I/O

PU/

EXTERNAL

PIN STRAPPING

I/O

PU/PDEXTERNAL

PIN STRAPPING

configuration details.

The power rail designation is not applicable for the multifunction and miscellaneous terminals.

TERMINAL

NAME NO.

CLK_48 F01

MFUNC0 G01 I/O PCII3 PCIO3

MFUNC1 H05 I/O PCII3 PCIO3

MFUNC2 H02

MFUNC3 H01

MFUNC4 J01

MFUNC5 J02 I/O PCII3 PCIO3

MFUNC6 J03 I/O PCII3 PCIO3

PHY_TEST_MA P17

RI_OUT / PME L05

SCL G02

SDA G03

SPKROUT

SUSPEND J05

TEST0 P12

USB_EN

A 48-MHz clock must be connected to this terminal.

Multifunction terminals 0−6. See Section 4.35, Multifunction Routing Status Register, for

PHY test pin. Not for customer use. It must be pulled high with a 4.7-kΩ resistor.

Ring indicate out and power management event output. This terminal provides an output for ring-indicate or PME

Serial clock. At PRST, the SCL signal is sampled to determine if a two-wire serial ROM is present. If the serial ROM is detected, then this terminal provides the serial clock signaling and is implemented as open-drain. For normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM VDD with a 2.7-kΩ resistor. Otherwise, it must be pulled low to ground with a 220-Ω resistor.

Serial data. This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM VDD with a 2.7-kΩ resistor. Otherwise, it must be pulled low to ground with a 220-Ω resistor.

Speaker output. SPKROUT is the output to the host system that can carry SPKR through the controller from the PC Card interface.

H03

SPKROUT is driven as the exclusive-OR combination of card SPKR

Suspend. SUSPEND protects the internal registers from clearing when the GRST asserted. See Section 3.8.6, Suspend Mode, for details.

Terminal TEST0 is used for factory test of the controller and must be connected to ground for normal operation.

USB enable. ThIs output terminal controlS an external CBT switch for the socket when an USB

E10

card is inserted into the socket.

DESCRIPTION

signals.

//CAUDIO inputs.

or PRST signal is

or CAUDIO

INPUT OUTPUT

TYPE

I LVCI1

I/O PCII3 PCIO3

I LCVI1 PU2 NA

O LVCO2

I/O TTLI1 TTLO2

O TTLO1

I LVCI2

I/O LVCI1 PD1 Tie to GND

O LVCO1 CBT switch Float

COMPONENTS

48 MHz clock source

Pullup resistor per PCI specification

Pullup resistor per I2C specification (value depends on EEPROM, typically 2.7 kΩ)

10-kΩ to 47-kΩ pulldown resistor

10-kΩ to 47-kΩ pullup resistor

Introduction

(IF UNUSED)

10-kΩ to 47-kΩ pullup resistor

Tie to GND if not using EEPROM

10-kΩ to 47-kΩ pullup resistor

September 2005 SCPS110

Introduction

I/O

POWER

I/O

POWER

Table 2−13. 16-Bit PC Card Address and Data Terminals

External components are not applicable for the 16-bit PC Card address and data terminals. If any 16-bit PC Card address and data terminal is unused, then the terminal may be left floating. For input, output, pullup, and pulldown information refer to information by terminal number in Table 2−15, Table 2−16, and Table 2−17.

TERMINAL

NAME NO.

A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D15 D14 D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

†

These terminals are reserved for the PCI7402 and PCI8402 controllers.

D19

F15 E19 G15

F19 G18 H15 H17 H19

F18

F17 G19 H14 E18 K15

L15

J15 H18 E17 A16 E14 B15 B14 A14 C13 B13

L18 M19 M17 N19 N17 C10 A10

E11

L19 M18 M15 N18 P19 B10

F11 C11

PC Card address. 16-bit PC Card address lines. A25 is the most significant bit. O V

PC Card data. 16-bit PC Card data lines. D15 is the most significant bit. I/O V

DESCRIPTION

†

TYPE

RAIL

CCCB

September 2005SCPS110

Introduction

I/O

POWER

I/O

POWER

Table 2−14. 16-Bit PC Card Interface Control Terminals

External components are not applicable for the 16-bit PC Card interface control terminals. If any 16-bit PC Card interface control terminal is unused, then the terminal may be left floating. For input, output, pullup, and pulldown information refer to information by terminal number in Table 2−15, Table 2−16, and Table 2−17.

TERMINAL

NAME NO.

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and must be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See

BVD1

(STSCHG

†

These terminals are reserved for the PCI7402 and PCI8402 controllers.

/RI)

BVD2

(SPKR

)

CD1 CD2

CE1 CE2

INPACK C14

IORD

IOWR

Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5,

A12

ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for this signal.

Status change. STSCHG condition of a 16-bit I/O PC Card.

Ring indicate. RI Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used

with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and must be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for

B12

this signal. Speaker. SPKR

configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the controller and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.

Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC

N15

Card is inserted into a socket, CD1

B11

Status Register.

L17

Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables

K18

even-numbered address bytes, and CE2 Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current

address. DMA request. INPACK that supports DMA. If it is used as a strobe, then the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read. IORD is asserted by the controller to enable 16-bit I/O PC Card data output during host I/O read cycles.

J18

DMA write. IORD DMA. The controller asserts IORD

I/O write. IOWR is driven low by the controller to strobe write data into 16-bit I/O PC Cards during host I/O write cycles.

J17

DMA read. IOWR DMA. The controller asserts IOWR

alerts the system to a change in the READY, write protect, or battery voltage dead

is used by 16-bit modem cards to indicate a ring detection.

is an optional binary audio signal available only when the card and socket have been

and CD2 are pulled low. For signal status, see Section 5.2, ExCA Interface

can be used as the DMA request signal during DMA operations from a 16-bit PC Card

is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports

during DMA transfers from the PC Card to host memory.

is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports

during transfers from host memory to the PC Card.

DESCRIPTION

enables odd-numbered address bytes.

†

TYPE

I V

O V

I V

O V

RAIL

CCCB

September 2005 SCPS110

Introduction

I/O

POWER

I/O

POWER

I/O

PU/

POWER

I/O

PU/PDPOWER

Table 2−14. 16-Bit PC Card Interface Control Terminals (Continued)

TERMINAL

NAME NO.

Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data output during host

OE K17

READY

(IREQ

)

REG

RESET C15 PC Card reset. RESET forces a hard reset to a 16-bit PC Card. O V

VS1 VS2

WAIT

WE G17

WP (IOIS16) A11

†

These terminals are reserved for the PCI7402 and PCI8402 controllers.

memory read cycles. DMA terminal count. OE DMA. The controller asserts OE

Ready. The ready function is provided when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready

E12

to accept a new data transfer command. Interrupt request. IREQ

I/O PC Card requires service by the host software. IREQ Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is

limited to attribute memory (OE separately accessed section of card memory and is generally used to record card capacity and other

E13

configuration and attribute information. DMA acknowledge. REG that supports DMA. The controller asserts REG DMA read (IOWR

A13

Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the

B16

operating voltage of the PC Card. Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle in

C12

progress. Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory

PC Cards that employ programmable memory technologies. DMA terminal count. WE controller asserts WE

Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16

I/O is 16 bits. IOIS16 on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses.

DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a request for a DMA operation.

is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports

to indicate TC for a DMA write operation.

is asserted by a 16-bit I/O PC Card to indicate to the host that a controller on the 16-bit

or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a

is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card

) or DMA write (IORD) strobes to transfer data.

is used as a TC during DMA operations to a 16-bit PC Card that supports DMA. The

to indicate the TC for a DMA read operation.

applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address

DESCRIPTION

is high (deasserted) when no interrupt is requested.

to indicate a DMA operation. REG is used in conjunction with the

) function.

Table 2−15. CardBus PC Card Interface System Terminals

†

TYPE

O V

I V

O V

I/O V

I V

O V

I V

RAIL

CCCB

A 33-Ω to 47-Ω series damping resistor (per PC Card specification) is the only external component needed for terminal C16 (CCLK). If any CardBus PC Card interface system terminal is unused, then the terminal may be left floating.

TERMINAL

NAME NO.

CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST

CCLK F18

CCLKRUN

CRST

†

These terminals are reserved for the PCI7402 and PCI8402 controllers.

CAUDIO, CCD2 CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings.

CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an

A11

increase in the CCLK frequency, and by the controller to indicate that the CCLK frequency is going to be decreased.

CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST

C15

signals are placed in a high-impedance state, and the controller drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

, CCD1, CVS2, and CVS1 are sampled on the rising edge of

DESCRIPTION

, CCLKRUN, CINT, CSTSCHG,

is asserted, all CardBus PC Card

INPUT OUTPUT

TYPE

O PCIO3 V

I/O PCII4 PCIO4 PU3 V

O PCII4 PCIO4 PU3 V

September 2005SCPS110

RAIL

CCCB

Introduction

I/O

POWER

I/O

POWER

Table 2−16. CardBus PC Card Address and Data Terminals

†

External components are not applicable for the 16-bit PC Card address and data terminals. If any CardBus PC Card address and data terminal is unused, then the terminal may be left floating.

TERMINAL

NAME NO.

CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10

CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

C10 A10

F11 E11 C11 B13 C13 A14 B14 B15 E14 A16 D19 E17 F15 H19

J17

J15

J18 K15 K17 K18 L15 L18 L19

M17 M18

N19

M15

N17 N18 P19

CardBus address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31−CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31−CAD0 contain data. CAD31 is the most significant bit.

DESCRIPTION

INPUT OUTPUT

TYPE

I/O PCII7 PCIO7 V

RAIL

CCCB

CardBus bus commands and byte enables. CC/BE3−CC/BE0 are multiplexed on the same

CC/BE3 CC/BE2 CC/BE1 CC/BE0

CPAR H14

†

These terminals are reserved for the PCI7402 and PCI8402 controllers.

E13

CardBus terminals. During the address phase of a CardBus cycle, CC/BE3

E18

the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0

H18

applies to byte 0 (CAD7−CAD0), CC/BE1 applies to byte 1 (CAD15−CAD8), CC/BE2 applies

L17

to byte 2 (CAD23−CAD16), and CC/BE3

CardBus parity. In all CardBus read and write cycles, the controller calculates even parity across the CAD and CC/BE CPAR with a one-CCLK delay. As a target during CardBus cycles, the controller compares its calculated parity to the parity indicator of the initiator; a compare error results in a parity error assertion.

buses. As an initiator during CardBus cycles, the controller outputs

applies to byte 3 (CAD31−CAD24).

−CC/BE0 define I/O PCII7 PCIO7 V

I/O PCII7 PCIO7 V

September 2005 SCPS110

CCCB

Introduction

I/O

PU/

POWER

I/O

PU/PDPOWER

CCD1

N15

CCD1

N15

CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in

Table 2−17. CardBus PC Card Interface Control Terminals

If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating.

TERMINAL

NAME NO.

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system

CAUDIO B12

CBLOCK

CCD2

CDEVSEL

CFRAME

CGNT

CINT

CIRDY

CPERR

CREQ

CSERR

CSTOP

CSTSCHG

CTRDY

CVS1 CVS2

†

These terminals are reserved for the PCI7402 and PCI8402 controllers.

speaker. The controller supports the binary audio mode and outputs a binary signal from the card to SPKROUT.

H15

CardBus lock. CBLOCK is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in

conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards

B11

to determine the operating voltage and card type. CardBus device select. The controller asserts CDEVSEL to claim a CardBus

cycle as the target device. As a CardBus initiator on the bus, the controller

F19

monitors CDEVSEL occurs, then the controller terminates the cycle with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME

E19

G17

E12

F17

G19

C14

C12

G18

A12

G15

A13 B16

is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME the CardBus bus transaction is in the final data phase.

CardBus bus grant. CGNT is driven by the controller to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed.

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host.

CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are both sampled asserted, wait states are inserted.

CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following the data cycle during which a parity error is detected.

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator.

CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR synchronous to CCLK, but deasserted by a weak pullup; deassertion may take several CCLK periods. The controller can report CSERR assertion of SERR

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is commonly asserted by target devices that do not support burst data transfers.

CardBus status change. CSTSCHG alerts the system to a change in the card status, and is used as a wake-up mechanism.

CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY time, wait states are inserted.

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1 interrogate cards to determine the operating voltage and card type.

until a target responds. If no target responds before timeout

on the PCI interface.

DESCRIPTION

and CTRDY are asserted. Until CIRDY

is used for target disconnects, and

and CTRDY are asserted; until this

and CCD2 to identify card insertion and

is deasserted,

is driven by the card

to the system by

†

INPUT OUTPUT

TYPE

I/O PCII4 PCIO4 PU3 V

I TTLI2 PU4

I/O PCII4 PCIO4 PU3 V

I/O PCII7 PCIO7 V

I/O PCII4 PCIO4 PU3 V

I PCII6 SW1 V

I/O PCII1 PCIO1 PU5 V

I/O TTLI2 TTLO1 PU4 V

RAIL

CCCB

TERMINAL

NAME NUMBER

RSVD B10, H17, M19 Reserved (CardBus reserved) Float

Table 2−18. Reserved Terminals

DESCRIPTION PIN STRAPPING

September 2005SCPS110

Introduction

I/O

EXTERNAL

PIN STRAPPING

I/O

EXTERNAL

PIN STRAPPING

signal pins must be matched and as short as possible to the

Table 2−19. IEEE 1394 Physical Layer Terminals

Table 2−19 is only applicable to the PCI4512, PCI7402, PCI7412, PCI7612, PCI8402, and PCI8412 controllers.

TERMINAL

NAME NO.

Cable power status input. This terminal is normally connected to cable power through a 400-kΩ resistor. This

CPS R12

R0 R1

TPA0P TPA0N

TPA1P TPA1N

TPBIAS0 TPBIAS1

TPB0P TPB0N

TPB1P TPB1N

XI XO

†

These terminals are reserved for the PCI6412 and PCI6612 controllers.

circuit drives an internal comparator that is used to detect the presence of cable power. If CPS is not used to detect cable power, then this terminal must be pulled to GND.

Current-setting resistor terminals. These terminals are connected to an external resistance to set the internal

T18

operating currents and cable driver output currents. A

T19

resistance of 6.34 kΩ ±1% is required to meet the IEEE Std 1394-1995 output voltage limits.

V14

Twisted-pair cable A differential signal terminals. Board trace

W14

lengths from each pair of positive and negative differential

external load resistors and to the cable connector. For an

V16

unused port, TPA+ and TPA− can be left open.

W16

Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair

R13

cable drivers and receivers and for signaling to the remote

W17

nodes that there is an active cable connection. Each of these pins must be decoupled with a 1.0-µF capacitor to ground.

V13

Twisted-pair cable B differential signal terminals. Board trace

W13

lengths from each pair of positive and negative differential

external load resistors and to the cable connector. For an

V15

unused port, TPB+ and TPB− must be pulled to ground.

W15

Crystal oscillator inputs. These pins connect to a

24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see

R19

Section 3.9.2, Crystal Selection). An external clock input can

R18

be connected to the XI terminal. When using an external clock input, the XO terminal must be left unconnected, and the clock must be supplied before the controller is taken out of reset. Refer to Section 3.9.2 for the operating characteristics of the XI terminal.

DESCRIPTION

INPUT OUTPUT

TYPE

I/O TP TP

I//O TP TP

I/O TP TP

†

COMPONENTS

390-kΩ series resistor to BUSPOWER if providing power through the 1394 port

6.34-kΩ ±1% resistor between R0 and R1 per 1394 specification

1394 termination (see reference schematics)

24.576-MHz oscillator (see implementation guide)

(IF UNUSED)

Tie to GND

Float

TERMINAL

NAME NUMBER

NC U12, V12, W12 No connect. These terminals do not have a connection anywhere on this device. Float NC E05 No connect. This terminal is an identification ball used for device orientation. Float

September 2005 SCPS110

Table 2−20. No Connect Terminals

DESCRIPTION PIN STRAPPING

Introduction

I/O

PU/

POWER

EXTERNAL

I/O

PU/PDPOWER

EXTERNAL

I/O

PU/

POWER

EXTERNAL

I/O

PU/PDPOWER

EXTERNAL

Table 2−21. SD/MMC Terminals

If any SD/MMC terminal is unused, then the terminal may be left floating.

TERMINAL

NAME NO.

MC_PWR_CTRL_0 MC_PWR_CTRL_1

SD_CD E09

SD_CLK

SD_CMD C05, E08

SD_DAT3 SD_DAT2 SD_DAT1 SD_DAT0

SD_WP E07

†

These terminals are reserved for the PCI4512 controller.

C08 F08

A04 A07

E06, B06 B05, A06 A05, C07 C06, B07

Media card power control for flash media sockets

SD/MMC card detect. This input is asserted when SD/MMC cards are inserted.

SD flash clock. This output provides the SD/MMC clock, which operates at 16 MHz.

SD flash command. This signal provides the SD command per the SD Memory Card Specifications.

SD flash data [3:0]. These signals provide the SD data path per the SD Memory Card Specifications.

SD write protect data. This signal indicates that the media inserted in the socket is write protected.

DESCRIPTION

Table 2−22. Memory Stick/PRO Terminals

If any Memory Stick/PRO terminal is unused, then the terminal may be left floating.

TERMINAL

NAME NO.

MC_PWR_CTRL_0 MC_PWR_CTRL_1

MS_BS E08

MS_CD A08

MS_CLK A07

MS_DATA3 MS_DATA2 MS_DATA1

MS_SDIO (DATA0) B07

†

These terminals are reserved for the PCI4512 controller.

C08

Media card power control for flash media sockets

F08

Memory Stick bus state. This signal provides Memory Stick bus state information.

Media Card detect. This input is asserted when a Memory Stick or Memory Stick Pro media is inserted.

Memory Stick clock. This output provides the MS clock, which operates at 16 MHz.

B06

Memory Stick data [3:1]. These signals provide the

A06

Memory Stick data path.

C07

Memory Stick serial data I/O. This signal provides Memory Stick data input/output. Memory Stick data 0.

DESCRIPTION

†

INPUT OUTPUT

TYPE

LVCI1

I/O

I LVCI1 LVCO1 PU2 V

LVCI3

I/O

LVCI3

I/O LVCI1 LVCO1 SW2 V

I/O LVCI1 LVCO1 PU2 V

LVCO1 LVCO1

LVCO3 LVCO3

PU2

PU2 V

†

INPUT OUTPUT

TYPE

LVCI1

I/O

I/O LVCI1 LVCO1 SW2 V

I LVCI1 PU2 V

I/O LVCI3 LVCO3 V

I/O LVCI1 LVCO1 SW2 V

LVCO1 LVCO1

PU2

V V

RAIL

CC CC

COMPONENTS

Power switch or FET to turn power on to FM socket

COMPONENTS

Power switch or FET to turn power on to FM socket

September 2005SCPS110

Introduction

I/O

PU/

POWER

EXTERNAL

I/O

PU/PDPOWER

EXTERNAL

Table 2−23. Smart Media/XD Terminals

†

If any Smart Media/XD terminal is unused, then the terminal may be left floating.

TERMINAL

NAME NO.

MC_PWR_CTRL_0 C08 Media card power control for flash media sockets O LVCO1 V

SmartMedia address latch enable. This signal

SM_ALE C05

SM_CD B08

SM_CE E07

SM_CLE B04

SM_D7 SM_D6 SM_D5 SM_D4 SM_D3 SM_D2 SM_D1 SM_D0 SM_EL_WP A07 SmartMedia electrical write protect I/O LVCI3 LVCO3 V

SM_PHYS_WP A03

SM_RE A04

SM_R/B F08

SM_WE E08

XD_CD A03 I LVCI1 PU2 V

†

These terminals are reserved for the PCI4512 controller.

functions as specified in the SmartMedia specification, and is used to latch addresses passed over SM_D7−SM_D0.

SmartMedia card detect. This input is asserted when SmartMedia cards are inserted.

SmartMedia card enable. This signal functions as specified in the SmartMedia specification, and is used to enable the media for a pending transaction.

SmartMedia command latch enable. This signal functions as specified in the SmartMedia specification, and is used to latch commands

passed over SM_D7−SM_D0. E06 B05 A05

SmartMedia data terminals. These signals pass

C06

data to and from the SmartMedia, and functions B06

as specified in the SmartMedia specifications. A06

C07 B07

SmartMedia physical write protect. This input

comes from the write protect tab of the

SmartMedia card.

SmartMedia read enable. This signal functions as

specified in the SmartMedia specification, and is

used to latch a read transfer from the card.

SmartMedia read/busy. This signal functions as

specified in the SmartMedia specification, and is

used to pace data transfers to the card.

SmartMedia write enable. This signal functions as

specified in the SmartMedia specification, and is

used to latch a write transfer to the card.

DESCRIPTION

INPUT OUTPUT

TYPE

I/O LVCI1 LVCO1 SW2 V

I LVCI1 PU2 V

I/O LVCI1 LVCO1 PU2 V

I/O LVCI1 LVCO1 PD2 V

I/O LVCI1 LVCO1 SW2 V

I LVCI1 PU2

I/O LVCI1 LVCO1 PU2 V

I/O LVCI1 LVCO1 SW2 V

RAIL

PARTS

Power switch or FET to turn power on to FM socket

100-kΩ pullup resistor to VCC for xD compliance

10-kΩ to 47-kΩ pullup resistor to VCC for xD compliance

100-kΩ pullup resistor to VCC for xD compliance

September 2005 SCPS110

Introduction

I/O

PU/

POWER

EXTERNAL

I/O

PU/PDPOWER

EXTERNAL

Table 2−24. Smart Card Terminals

†

If any Smart Card terminal is unused, then the terminal may be left floating, except for SC_VCC_5V which must be connected to 5 V. Smart Card terminals are only functional in the PCI6612 and PCI7612 controllers.

TERMINAL

NAME NO.

SC_CD F03

SC_CLK E02

SC_DATA E01 Smart Card data input/output I/O PCII5 PCIO5 SW3 SC_VCC_5V

SC_FCB E03

SC_GPIO6 SC_GPIO5 SC_GPIO4 SC_GPIO3 SC_GPIO2 SC_GPIO1 SC_GPIO0

SC_OC F02

SC_PWR_CTRL G05 Smart Card power control for the Smart Card socket O LVCO1 VCC

SC_RFU D01

SC_RST F05

SC_VCC_5V G06 Smart Card power terminal PWR

†

These terminals are reserved for the PCI4512, PCI6412, PCI7402, PCI7412, PCI8402, and PCI8412 controllers.

Smart Card card detect. This input is asserted when Smart Cards are inserted.

Smart Card clock. The controller drives a 3-MHz clock to the Smart Card interface when enabled.

Smart Card function code. The controller does not support synchronous Smart Cards as specified in ISO/IEC 7816-10, and this terminal is in a

high-impedance state. C06 A05

Smart Card general-purpose I/O terminals. These

B05

signals can be controlled by firmware and are used as E06

control signals for an external Smart Card interface chip C05

or level shifter. A04

B04

Smart Card overcurrent. This input comes from the

Smart Card power switch.

Smart Card reserved. This terminal is in a

high-impedance state.

Smart Card This signal starts and stops the Smart Card

reset sequence. The controller asserts this reset when

requested by the host.

DESCRIPTION

INPUT OUTPUT

TYPE

I/O LVCI1 LVCO1 PU2 VCC

O PCIO8 SC_VCC_5V

I/O PCII5 PCIO5 SW3 SC_VCC_5V

LVCI1 LVCI1 LVCI1 LVCI1

I/O

LVCI1 LVCI3 LVCI3

I LVCI1 PU2 VCC

I/O PCII5 PCIO5 SW3 SC_VCC_5V

O PCIO6 SC_VCC_5V

LVCO1 LVCO1 LVCO1 LVCO1 LVCO1 LVCO3 LVCO3

SW2 SW2 SW2 SW2 SW2

PU2 PU2

RAIL

VCC VCC VCC VCC VCC VCC VCC

PARTS

Series resistor or 22 kΩ resistor to GND 68 pF capacitor to GND

Power switch or FET to turn on power to FM socket

September 2005SCPS110

3 Principles of Operation

The following sections give an overview of the PCIxx12 controller. Figure 3−1 shows the connections to the controller. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.

EEPROM

PCI Bus

PCIxx12

SD/MMC

MS/MSPRO

SM/xD

Principles of Operation

Power Switch

1394a

Socket

Power Switch

Smart

Card

Figure 3−1. PCIxx12 System Block Diagram

3.1 Power Supply Sequencing

The PCIxx12 controller contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp voltages. The core power supply is always 1.5 V. The clamp voltages can be either 3.3 V or 5 V, depending on the interface. The following power-up and power-down sequences are recommended.

The power-up sequence is:

1. Power core 1.5 V.

2. Apply the I/O voltage.

3. Apply the analog voltage.

Card

SD/MMC

Power Switch

4. Apply the clamp voltage. The power-down sequence is:

1. Remove the clamp voltage.

2. Remove the analog voltage.

3. Remove the I/O voltage.

4. Remove power from the core.

NOTE: If the voltage regulator is enabled, then steps 2, 3, and 4 of the power-up sequence and steps 1, 2, and 3 of the power-down sequence all occur simultaneously.

September 2005 SCPS110

Principles of Operation

3.2 I/O Characteristics

The PCIxx12 controller meets the ac specifications of the PC Card Standard (release 8.1) and the PCI Local Bus Specification. Figure 3−2 shows a 3-state bidirectional buffer. Section 14.2, Recommended Operating Conditions, provides the electrical characteristics of the inputs and outputs.

3.3 Clamping Voltages

The clamping voltages are set to match whatever external environment the PCIxx12 controller is interfaced with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals. The core power supply is 1.5 V and is independent of the clamping voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the controller must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a 5-V PCI bus, then V supply.

Tied for Open Drain

CCP

Pad

Figure 3−2. 3-State Bidirectional Buffer

can be connected to a 5-V power

CCP

3.4 Peripheral Component Interconnect (PCI) Interface

The PCIxx12 controller is fully compliant with the PCI Local Bus Specification. The controller provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the V

terminals to the desired voltage level. In addition to the mandatory PCI

CCP

signals, the controller provides the optional interrupt signals INTA

3.4.1 1394 PCI Bus Master

As a bus master, the 1394 function of the PCIxx12 controller supports the memory commands specified in Table 3−1. The PCI master supports the memory read, memory read line, and memory read multiple commands. The read command usage for read transactions of greater than two data phases are determined by the selection in bits 9−8 (MR_ENHANCE field) of the PCI miscellaneous configuration register (refer to Section 7.23 for details). For read transactions of one or two data phases, a memory read command is used.

Table 3−1. PCI Bus Support

PCI

Memory read 0110 DMA read from memory Memory write 0111 DMA write to memory Memory read multiple 1100 DMA read from memory Memory read line 1110 DMA read from memory Memory write and invalidate 1111 DMA write to memory

COMMAND

C/BE3

−C/BE0

OHCI MASTER FUNCTION

, INTB, INTC, and INTD.

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3.4.2 Device Resets

The following are the requirements for proper reset of the PCIxx12 controller:

Principles of Operation

1. GRST

2. GRST

3. PRST

and PRST must both be asserted at power on. must be asserted for at least 2 ms at power on.

must be deasserted either at the same time or after GRST is asserted.

4. PCLK must be stable for 100 µs before PRST

> 2 ms > 0 ns

VCC

GRST

PRST

PCLK

is deasserted.

> 100 ms

Figure 3−3. PCI Reset Requirement

3.4.3 Serial EEPROM I2C Bus

The PCIxx12 controller offers many choices for modes of operation, and these choices are selected by programming several configuration registers. For system board applications, these registers are normally programmed through the BIOS routine. For add-in card and docking-station/port-replicator applications, the controller provides a two-wire inter-integrated circuit (IIC or I EEPROM.

The controller is always the bus master, and the EEPROM is always the slave. Either device can drive the bus low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors on the SCL and SDA signal lines. The controller is always the source of the clock signal, SCL.

System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and SDA terminals. If the controller detects a logic-high level on the SCL terminal at the end of GRST then it initiates incremental reads from the external EEPROM. Any size serial EEPROM up to the I 16 Kbits can be used, but only the first 96 bytes (from offset 00h to offset 5Fh) are required to configure the controller. Figure 3−3 shows a serial EEPROM application.

September 2005 SCPS110

C) serial bus for use with an external serial

C limit of

Principles of Operation

In addition to loading configuration data from an EEPROM, the I2C bus can be used to read and write from

other I

C serial devices. A system designer can control the I2C bus, using the controller as bus master, by reading and writing PCI configuration registers. Setting bit 3 (SBDETECT) in the serial bus control/status

register (PCI offset B3h, see Section 4.49) causes the controller to route the SDA and SCL signals to the SDA and SCL terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by accessing the serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1h, and B2h; see Sections 4.46, 4.47, and 4.48, respectively).

EEPROM interface status information is communicated through the serial bus control and status register (PCI offset B3h, see Section 4.49). Bit 3 (SBDETECT) in this register indicates whether or not the serial ROM circuitry detects the pullup resistor on SCL. Any undefined condition, such as a missing acknowledge, results in bit 0 (ROM_ERR) being set. Bit 4 (ROMBUSY) is set while the subsystem ID register is loading (serial ROM interface is busy).

The subsystem vendor ID for functions 2 and 3 is also loaded through EEPROM. The EEPROM load data goes to all four functions from the serial EEPROM loader.

Serial ROM

A0 A1A2SCL

SDA

Figure 3−4. Serial ROM Application

3.4.4 Function 0 (CardBus) Subsystem Identification

The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset 42h, see Section 4.27) make up a doubleword of PCI configuration space for function 0. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC 99/PC 2001 requirement.

The PCIxx12 controller offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but can be made read/write by clearing bit 5 (SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). Once this bit is cleared, the BIOS can write a subsystem identification value into the registers at PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM).

SCL SDA

PCIxx12

In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM. The controller loads the data from the serial EEPROM after a reset of the primary bus. Note that the SUSPEND

input gates the PCI reset from the entire PCIxx12 core, including the serial-bus state machine (see Section 3.8.6, Suspend Mode, for details on using SUSPEND

September 2005SCPS110

The controller provides a two-line serial-bus host controller that can interface to a serial EEPROM. See Section 3.6, Serial EEPROM Interface,

for details on the two-wire serial-bus controller and applications.

3.4.5 Function 1 (OHCI 1394) Subsystem Identification

The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 7.25, Subsystem Access Register). See Table 7−22 for a complete description of the register contents.

Write access to the subsystem access register updates the subsystem identification registers identically to OHCI-Lynx. The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 1 PCI offsets 2Ch and 2Eh, respectively. The system ID value written to this register may also be read back from this register . See Table 7−22 for a complete description of the register contents.

3.4.6 Function 2 (Flash Media) Subsystem Identification

The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI configuration space (see Section 11.22, Subsystem Access Register). See Table 11−15 for a complete description of the register contents.

The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 2 PCI offsets 2Ch and 2Eh, respectively. See Table 11−15 for a complete description of the register contents.

Principles of Operation

3.4.7 Function 3 (SD Host) Subsystem Identification

The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset 8Ch in the PCI configuration space (see Section 12.23, Subsystem Access Register). See Table 12−16 for a complete description of the register contents.

The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 3 PCI offsets 2Ch and 2Eh, respectively. See Table 12−16 for a complete description of the register contents.

3.4.8 Function 4 (Smart Card) Subsystem Identification

The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI configuration space (see Section 13.23, Subsystem ID Alias Register). See Table 13−14 for a complete description of the register contents.

The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 4 PCI offsets 2Ch and 2Eh, respectively. See Table 13−14 for a complete description of the register contents.

3.5 PC Card Applications

The PCIxx12 controller supports all the PC Card features and applications as described below.

• Card insertion/removal and recognition per the PC Card Standard (release 8.1)

• Speaker and audio applications

• LED socket activity indicators

• PC Card controller programming model

• CardBus socket registers

September 2005 SCPS110

Principles of Operation

3.5.1 PC Card Insertion/Removal and Recognition

The PC Card Standard (release 8.1) addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage requirements and interface (CardBus versus 16-bit) are determined.

The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface.

3.5.2 Low Voltage CardBus Card Detection

The card detection logic of the PCIxx12 controller includes the detection of Cardbus cards with VCC = 3.3 V and V socket present state register as follows based on bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.30):

• If the 12V_SW_SEL bit is 0b (TPS2228 is used), then the 1.8-V CardBus card causes the 3VCARD bit

• If the 12V_SW_SEL bit is 1b (TPS2226 is used), then the 1.8-V CardBus card causes the XVCARD bit

= 1.8 V. The reporting of the 1.8-V CardBus card (VCC = 3.3 V, VPP = 1.8 V) is reported through the

in the socket present state register to be set.

3.5.3 PC Card Detection

The PC Card Standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate upon card insertion into a cold, unpowered socket. Through this interrogation, card voltage requirements and interface type (16-bit vs. CardBus) are determined. The scheme uses the CD1, CD2, VS1, and VS2 signals (CCD1, CCD2, CVS1, CVS2 for CardBus). A PC Card designer connects these four terminals in a certain configuration to indicate the type of card and its supply voltage requirements. The encoding scheme for this, defined in the PC Card Standard, is shown in Table 3−2. In addition, to 16-bit and CardBus cards, the controller supports the detection of USB custom cards via the custom card detection method defined by the PC Card Standard. Other types of custom cards are not supported and if detected the socket registers will report values as if it were empty.

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Principles of Operation

Table 3−2. PC Card—Card Detect and Voltage Sense Connections

CCD2//CD2 CCD1//CD1 CVS2//VS2 CVS1//VS1 Key Interface V

Ground Ground Open Open 5 V 16-bit PC Card 5 V Per CIS (VPP) Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V Per CIS (VPP)

Ground Ground Ground Ground 5 V 16-bit PC Card

Ground Ground Open Ground LV 16-bit PC Card 3.3 V Per CIS (VPP) Ground Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V Per CIS (VPP)

Connect to

CVS2

Connect to

CVS1

Ground Ground Ground Open LV 16-bit PC Card X.X V Per CIS (VPP)

Connect to

CVS2

Ground

Connect to

CVS1

Ground

Connect to

CVS1

Ground

Ground Ground

Ground

Connect to

CVS2

Ground Open

Connect to

CVS1

Connect to

CVS2

Open

Connect to

CCD2

Connect to

CCD2

Connect to

CCD1

Ground

Connect to

CCD1

Connect to

CCD1

Ground LV CardBus PC Card 3.3 V and X.X V Per CIS (VPP)

Connect to

CCD2

Open LV CardBus PC Card 3.3 V 1.8 V (V

Open LV CardBus PC Card X.X V and Y.Y V Per CIS (VPP)

Connect to

CCD2

Connect to

CCD1

Ground Reserved Reserved

LV CardBus PC Card 3.3 V Per CIS (VPP)

LV CardBus PC Card

LV CardBus PC Card Y.Y V Per CIS (VPP)

LV UltraMedia Per query terminals

5 V, 3.3 V, and

X.X V

3.3 V, X.X V, and Y.Y V

VPP/V

CORE

Per CIS (VPP)

CORE

)

3.5.4 Flash Media and Smart Card Detection

The PCIxx12 controller detects flash media card insertions through the SD_CD, MS_CD, SM_CD, and XD_CD The controller debounces these signals such that instability of the signal does not cause false card insertions. The debounce time is approximately 50 ms. The detect signals are not debounced on card removals. The filtered detect signals are used in the flash media card detection and power control logic.

The MMC/SD card detection and power control logic contains three main states:

• Socket empty, power off

• Card inserted, power off

• Card inserted, power on

The controller detects a Smart Card insertion through the SC_CD Card is inserted in the socket. The controller debounces the SC_CD does not cause false card insertions. The debounce time is approximately 50 ms. The SC_CD debounced on card removals. The filtered SC_CD control logic.

The Smart Card detection and power control logic contains three main states:

• Socket empty, power off

• Card inserted, power off

• Card inserted, power on

terminals. When one of these terminals is 0b, a flash media device is inserted in the respective socket.

terminal. When this terminal is 0b, a Smart

signal such that instability of the signal

signal is not

signal is used in the Smart Card detection and power

September 2005 SCPS110

Principles of Operation

OUTPUT

3.5.5 Power Switch Interface

The power switch interface of the PCIxx12 controller supports either the 3-pin serial interface or the 4-pin parallel interface. The RSVD/VD0/VCCD1 interface is used. If the RSVD/VD0/VCCD1 serial interface is used. If the RSVD/VD0/VCCD1 parallel interface is used. The 3-pin interface is implemented such that the controller can connect to both the TPS2226 and TPS2228 power switches. Bit 10 (12V_SW_SEL) in the general control register (PCI offset 86h, see Section 4.30) selects the power switch that is implemented. The controller defaults to use the control logic for the TPS2228 power switch. See Table 3−3 and Table 3−6 below for the power switch control logic.

Table 3−3. TPS2228 Control Logic—xVPP/VCORE

AVPP/VCORE CONTROL SIGNALS

D8(SHDN) D0 D1 D9

1 0 0 X 0 V 1 0 0 X 0 V 1 0 1 0 3.3 V 1 0 1 0 3.3 V 1 0 1 1 5 V 1 0 1 1 5 V 1 1 0 X Hi-Z 1 1 0 X Hi-Z 1 1 1 0 Hi-Z 1 1 1 0 Hi-Z 1 1 1 1 1.8 V 1 1 1 1 1.8 V 0 X X X Hi-Z 0 X X X Hi-Z

pin selects whether the 3-pin serial interface or the 4-pin parallel

pin is sampled high on the rising edge of GRST, then the 3-pin

OUTPUT

V_AVPP/VCORE

pin is sampled low on the rising edge of GRST, then the 4-pin

BVPP/VCORE CONTROL SIGNALS

D8(SHDN) D4 D5 D10

OUTPUT

V_BVPP/VCORE

Table 3−4. TPS2228 Control Logic—xVCC

AVCC CONTROL SIGNALS

D8(SHDN) D3 D2

1 0 0 0 V 1 0 0 0 V 1 0 1 3.3 V 1 0 1 3.3 V 1 1 0 5 V 1 1 0 5 V 1 1 1 0 V 1 1 1 0 V 0 X X Hi-Z 0 X X Hi-Z

OUTPUT V_AVCC

BVCC CONTROL SIGNALS

D8(SHDN) D6 D7

Table 3−5. TPS2226 Control Logic—xVPP

AVPP CONTROL SIGNALS

D8(SHDN) D0 D1 D9

1 0 0 X 0 V 1 0 0 X 0 V 1 0 1 0 3.3 V 1 0 1 0 3.3 V 1 0 1 1 5 V 1 0 1 1 5 V 1 1 0 X 12 V 1 1 0 X 12 V 1 1 1 X Hi-Z 1 1 1 X Hi-Z 0 X X X Hi-Z 0 X X X Hi-Z

OUTPUT

V_AVPP

BVPP CONTROL SIGNALS

D8(SHDN) D4 D5 D10

Table 3−6. TPS2226 Control Logic—xVCC

AVCC CONTROL SIGNALS

D8(SHDN) D3 D2

1 0 0 0 V 1 0 0 0 V 1 0 1 3.3 V 1 0 1 3.3 V 1 1 0 5 V 1 1 0 5 V 1 1 1 0 V 1 1 1 0 V 0 X X Hi-Z 0 X X Hi-Z

OUTPUT V_AVCC

BVCC CONTROL SIGNALS

D8(SHDN) D6 D7

OUTPUT V_BVCC

OUTPUT

V_BVPP

OUTPUT V_BVCC

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3.5.6 Internal Ring Oscillator

The internal ring oscillator provides an internal clock source for the PCIxx12 controller so that neither the PCI clock nor an external clock is required in order for the controller to power down a socket or interrogate a PC Card. This internal oscillator, operating nominally at 16 kHz, is always enabled.

3.5.7 Integrated Pullup Resistors for PC Card Interface

The PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit PC Card configurations. The PCIxx12 controller has integrated all of these pullup resistors and requires no additional external components. The I/O buffer on the CSTSCHG//BVD1(STSCHG capability to switch to an internal pullup resistor when a 16-bit PC Card is inserted, or switch to an internal pulldown resistor when a CardBus card is inserted. This prevents inadvertent CSTSCHG events.

3.5.8 SPKROUT and CAUDPWM Usage

The SPKROUT terminal carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 terminal becomes the SPKR terminal, in CardBus applications, is referred to as CAUDIO. SPKR to the PCIxx12 controller. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform as well as a PWM signal. The binary audio signal from the PC Card socket is enabled by bit 1 (SPKROUTEN) of the card control register (PCI offset 91h, see Section 4.37).

Older controllers support CAUDIO in binary or PWM mode, but use the same output terminal (SPKROUT). Some audio chips may not support both modes on one terminal and may have a separate terminal for binary and PWM. The PCIxx12 implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC terminal. Bit 2 (AUD2MUX), located in the card control register, is programmed to route a CardBus CAUDIO PWM terminal to CAUDPWM. See Section 4.35, Multifunction Routing Register, for details on configuring the MFUNC terminals.

Principles of Operation

) terminal has the

input terminal from the card. This

passes a TTL-level binary audio signal

Figure 3−5 illustrates the SPKROUT connection.

System

Core Logic

SPKROUT

PCIxx12

CAUDPWM

Figure 3−5. SPKROUT Connection to Speaker Driver

3.5.9 LED Socket Activity Indicators

The socket activity LEDs indicate when a PC Card is being accessed. The LEDA1 and LEDSKT signals can be routed to the multifunction terminals. When configured for LED outputs, these terminals output an active high signal to indicate socket activity. See Section 4.35, Multifunction Routing Status Register, configuring the multifunction terminals.

The active-high LED signal is driven for 64 ms. When the LED is not being driven high, it is driven to a low state. Either of the two circuits shown in Figure 3−6 can be implemented to provide LED signaling, and the board designer must implement the circuit that best fits the application.

The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity signals are pulsed when READY(IREQ if CFRAME

, IRDY, or CREQ is active.

BINARY_SPKR

Speaker

Subsystem

PWM_SPKR

for details on

) is low. For CardBus cards, the LED activity signals are pulsed

September 2005 SCPS110

Principles of Operation

MFUNCx

PCIxx12

Figure 3−6. Sample LED Circuit

As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.

If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven.

3.5.10 CardBus Socket Registers

The PCIxx12 controller contains all registers for compatibility with the PCI Local Bus Specification and the PC Card Standard. These registers, which exist as the CardBus socket registers, are listed in Table 3−7.

Table 3−7. CardBus Socket Registers

Socket event 00h Socket mask 04h Socket present state 08h Socket force event 0Ch Socket control 10h Reserved 14h−1Ch Socket power management 20h

Current Limiting

R ≈ 150 Ω

Socket LED

3.5.11 48-MHz Clock Requirements

The PCIxx12 controller is designed to use an external 48-MHz clock connected to the CLK_48 terminal to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for the flash media function (Function 2) of the controller.

The 48-MHz clock is needed as follows in the designated states:

• Power−up Follow the power-up sequence

• D0: Clock must not be stopped

• D1/D2/D3: Clock can be stopped

• D1/D2/D3

• D3

cold

The 48-MHz clock must maintain a frequency of 48 MHz ± 0.8% over normal operating conditions. This clock must maintain a duty cycle of 40% − 60%. The controller requires that the 48-MHz clock be running and stable (a minimum of 10 clock pulses) before a GRST

to D0: Need 10 clocks before D0 state

hot

to D0: Need 10 clocks before PRST de-assert

deassertion.

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The following are typical specifications for crystals used with the controller in order to achieve the required frequency accuracy and stability.

• Crystal mode of operation: Fundamental

• Frequency tolerance @ 25°C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with ±30 ppm frequency tolerance is recommended for adequate margin.

• Frequency stability (overtemperature and age): A crystal with ±30 ppm frequency stability is

recommended for adequate margin.

NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than ±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone. Crystal aging also contributes to the frequency variation.

3.6 Serial EEPROM Interface

The PCIxx12 controller has a dedicated serial bus interface that can be used with an EEPROM to load certain registers in the controller. The EEPROM is detected by a pullup resistor on the SCL terminal. See Table 3−9 for the EEPROM loading map.

3.6.1 Serial-Bus Interface Implementation

The PCIxx12 controller drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency for standard mode I

C. The serial EEPROM must be located at address A0h.

Principles of Operation

Some serial device applications may include PC Card power switches, card ejectors, or other devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed in the sections that follow.

3.6.2 Accessing Serial-Bus Devices Through Software

The PCIxx12 controller provides a programming mechanism to control serial bus devices through software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−8 lists the registers used to program a serial-bus device through software.

Table 3−8. PCIxx12 Registers Used to Program Serial-Bus Devices

PCI OFFSET REGISTER NAME DESCRIPTION

B0h Serial-bus data Contains the data byte to send on write commands or the received data byte on read commands. B1h Serial-bus index

B2h

B3h

Serial-bus slave address

Serial-bus control and status

The content of this register is sent as the word address on byte writes or reads. This register is not used in the quick command protocol.

Write transactions to this register initiate a serial-bus transaction. The slave device address and the R/ W command selector are programmed through this register.

Read data valid, general busy, and general error status are communicated through this register. In addition, the protocol-select bit is programmed through this register.

3.6.3 Serial-Bus Interface Protocol

The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3−4. The PCIxx12 controller, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode I

All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as shown in Figure 3−7. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3−7. Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control signals, that is, a start or a stop condition.

C using 7-bit addressing.

September 2005 SCPS110

Principles of Operation

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 3−7. Serial-Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−8 illustrates the acknowledge protocol.

SCL From

Master

SDA Output

By Transmitter

SDA Output By Receiver

123 789

Figure 3−8. Serial-Bus Protocol Acknowledge

The controller is a serial bus master; all other devices connected to the serial bus external to the controller are slave devices. As the bus master, the controller drives the SCL clock at nearly 100 kHz during bus cycles and places SCL in a high-impedance state (zero frequency) during idle states.

Typically, the controller masters byte reads and byte writes under software control. Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See Section 3.6.4, Serial-Bus EEPROM Application, for details on how the controller automatically loads the subsystem identification and other register defaults through a serial-bus EEPROM.

Figure 3−9 illustrates a byte write. The controller issues a start condition and sends the 7-bit slave device address and the command bit zero. A 0b in the R/W

command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the address. If no acknowledgment is received by the controller, then an appropriate status bit is set in the serial-bus control/status register (PCI offset B3h, see Section 4.49). The word address byte is then sent by the controller, and another slave acknowledgment is expected. Then the controller delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition.

Slave Address Word Address

Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA

R/W

S/P = Start/Stop ConditionA = Slave Acknowledgement

b7 b6 b4b5 b3 b2 b1 b0 A P

Data Byte

Figure 3−9. Serial-Bus Protocol—Byte Write

September 2005SCPS110

Principles of Operation

Figure 3−10 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command bit must be set to 1b to indicate a read-data transfer. In addition, the PCIxx12 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL signal remains driven by the PCIxx12 master.

Slave Address Word Address

Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA

Start

A = Slave Acknowledgement

R/W

Sb6 b4b5 b3 b2 b1 b0 1 A

Restart R/W

b7 b6 b4b5 b3 b2 b1 b0 M P

S/P = Start/Stop ConditionM = Master Acknowledgement

Slave Address

Data Byte

Figure 3−10. Serial-Bus Protocol—Byte Read

Figure 3−11 illustrates EEPROM interface doubleword data collection protocol.

Slave Address Word Address

S1 10 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0AA

Start

Data Byte 3 M

R/W

Data Byte 2 Data Byte 1 Data Byte 0 M PMM

S1 10 00001A

Restart

Slave Address

Stop

R/W

M = Master Acknowledgement S/P = Start/Stop ConditionA = Slave Acknowledgement

Figure 3−11. EEPROM Interface Doubleword Data Collection

3.6.4 Serial-Bus EEPROM Application

When the PCI bus is reset and the serial-bus interface is detected, the PCIxx12 controller attempts to read the subsystem identification and other register defaults from a serial EEPROM.

This format must be followed for the controller to load initializations from a serial EEPROM. All bit fields must be considered when programming the EEPROM.

The serial EEPROM is addressed at slave address 1010 000b by the controller. All hardware address bits for the EEPROM must be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application (Figure 3−11) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.

September 2005 SCPS110

Principles of Operation

Table 3−9. EEPROM Loading Map

SERIAL ROM

OFFSET

00h CardBus function indicator (00h) 01h Number of bytes (22h)

PCI 04h, command register, function 0, bits 8, 6−5, 2−0

02h [7]

Command

register, bit 8 03h Reserved 04h PCI 40h, subsystem vendor ID, byte 0 05h PCI 41h, subsystem vendor ID, byte 1 06h PCI 42h, subsystem ID, byte 0 07h PCI 43h, subsystem ID, byte 1 08h PCI 44h, PC Card 16-bit I/F legacy mode base address register, byte 0, bits 7−1 09h PCI 45h, PC Card 16-bit I/F legacy mode base address register, byte 1

0Ah PCI 46h, PC Card 16-bit I/F legacy mode base address register, byte 2 0Bh PCI 47h, PC Card 16-bit I/F legacy mode base address register, byte 3 0Ch PCI 80h, system control, function 0, byte 0, bits 6−0 0Dh Reserved 0Eh PCI 81h, system control, byte 1, bits 7, 6 0Fh Reserved nonloadable (PCI 82h, system control, byte 2)

10h PCI 83h, system control, byte 3 11h PCI 8Ch, MFUNC routing, byte 0 12h PCI 8Dh, MFUNC routing, byte 1 13h PCI 8Eh, MFUNC routing, byte 2 14h PCI 8Fh, MFUNC routing, byte 3 15h PCI 90h, retry status, bits 7, 6 16h PCI 91h, card control, bit 7 17h PCI 92h, device control, bits 6−1 (bit 0 must be programmed to 0b) 18h PCI 93h, diagnostic, bits 7, 4−0 19h PCI A2h, power-management capabilities, function 0, bit 15 (bit 7 of EEPROM offset 19h corresponds to bit 15)

1Ah Reserved 1Bh Reserved 1Ch Reserved 1Dh ExCA 00h, ExCA identification and revision, bits 7−0 1Eh PCI 86h, general control, byte 0, bits 7−0 1Fh PCI 87h, general control, byte 1, bits 7, 6 (can only be set to 1b if bits 1:0 = 01b), 4−0

20h PCI 89h, GPE enable, bits 7, 6, 4−0 21h PCI 8Bh, general-purpose output, bits 4−0 22h PCI 85h, general control byte 1, bits 2−0 23h Reserved 24h 1394 OHCI function indicator (01h) 25h Number of bytes (17h) 26h PCI 3Fh, maximum latency bits 7−4 PCI 3Eh, minimum grant, bits 3−0 27h PCI 2Ch, subsystem vendor ID, byte 0

[6]

Command

BYTE DESCRIPTION

[5]

[4:3]

RSVD

[2]

Command

[1]

Command

[0]

Command

September 2005SCPS110

Table 3−9. EEPROM Loading Map (Continued)

SERIAL ROM

OFFSET

28h PCI 2Dh, subsystem vendor ID, byte 1

29h PCI 2Eh, subsystem ID, byte 0 2Ah PCI 2Fh, subsystem ID, byte 1 2Bh PCI F4h, Link_Enh, byte 0, bits 7, 2, 1

OHCI 50h, host controller control, bit 23

[7]

Link_Enh.

enab_unfair

2Ch Mini-ROM address, this byte indicates the MINI ROM offset into the EEPROM

2Dh OHCI 24h, GUIDHi, byte 0 2Eh OHCI 25h, GUIDHi, byte 1 2Fh OHCI 26h, GUIDHi, byte 2

30h OHCI 27h, GUIDHi, byte 3

31h OHCI 28h, GUIDLo, byte 0

32h OHCI 29h, GUIDLo, byte 1

33h OHCI 2Ah, GUIDLo, byte 2

34h OHCI 2Bh, GUIDLo, byte 3

35h Checksum (Reserved—no bit loaded)

36h PCI F5h, Link_Enh, byte 1, bits 7, 6, 5, 4

37h PCI F0h, PCI miscellaneous, byte 0, bits 7, 5, 4, 2, 1, 0

38h PCI F1h, PCI miscellaneous, byte 1, bits 7−0

39h Reserved 3Ah Reserved (CardBus CIS pointer) 3Bh Reserved 3Ch PCI ECh, PCI PHY control, bits 7, 3, 1 3Dh Flash media core function indicator (02h) 3Eh Number of bytes (05h) 3Fh PCI 2Ch, subsystem vendor ID, byte 0

40h PCI 2Dh, subsystem vendor ID, byte 1

41h PCI 2Eh, subsystem ID, byte 0

42h PCI 2Fh, subsystem ID, byte 1

43h PCI 4Ch, general control, bits 7−4, 2−0

44h SD host controller function indicator (03h)

45h Number of bytes (0Bh)

46h PCI 2Ch, subsystem vendor ID, byte 0

47h PCI 2Dh, subsystem vendor ID, byte 1

48h PCI 2Eh, subsystem ID, byte 0

49h PCI 2Fh, subsystem ID, byte 1 4Ah PCI 88h, general control bits 7−3, 1, 0 4Bh PCI 94h, slot 0 3.3 V maximum current 4Ch Reserved (PCI 98h, slot 1 3.3 V maximum current) 4Dh Reserved (PCI 9Ch, slot 2 3.3 V maximum current)

HCControl.Program Phy Enable

[6]

BYTE DESCRIPTION

[5:3]

RSVD

00h = No MINI ROM

Other Values = MINI ROM offset

Link_Enh, bit 2

[2]

Principles of Operation

[1]

Link_Enh.

enab_accel

[0]

RSVD

September 2005 SCPS110

Principles of Operation

Table 3−9. EEPROM Loading Map (Continued)

SERIAL ROM

OFFSET

4Eh Reserved (PCI A0h, slot 3 3.3 V maximum current) 4Fh Reserved (PCI A4h, slot 4 3.3 V maximum current)

50h Reserved (PCI A8h, slot 5 3.3 V maximum current) 51h PCI Smart Card function indicator (04h) 52h Number of bytes (0Eh) 53h PCI 09h, class code, byte 0 54h PCI 0Ah, class code, byte 1 55h PCI 0Bh, class code, byte 2 56h PCI 2Ch, subsystem vendor ID, byte 0 57h PCI 2Dh, subsystem vendor ID, byte 1 58h PCI 2Eh, subsystem ID, byte 0

59h PCI 2Fh, subsystem ID, byte 1 5Ah PCI 4Ch, general control bits 7−4 5Bh PCI 58h, Smart Card configuration 1, byte 0, bits 4, 0 5Ch PCI 59h, Smart Card configuration 1, byte 1, bits 4, 0 5Dh PCI 5Ah, Smart Card configuration 1, byte 2, bits 4, 0 5Eh PCI 5Bh, Smart Card configuration 1, byte 3, bits 7−4, 0 5Fh PCI 5Ch, Smart Card configuration 2, byte 0

60h PCI 5Dh, Smart Card configuration 2, byte 1

61h End-of-list indicator (80h)

BYTE DESCRIPTION

3.7 Programmable Interrupt Subsystem

Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the PCIxx12 controller. The controller provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this controller are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The controller is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required.

The controller detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the controller, PC Card interrupts are classified either as card status change (CSC) or as functional interrupts.

The method by which any type of interrupt is communicated to the host interrupt controller varies from system to system. The controller offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All interrupt signaling is provided through the seven multifunction terminals, MFUNC0−MFUNC6.

3.7.1 PC Card Functional and Card Status Change Interrupts

PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards.

September 2005SCPS110

Principles of Operation

CardBus

Battery conditions

memory

Smart Card

Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the PCIxx12 controller and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.

Table 3−10 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The four types of cards that can be inserted into any PC Card socket are:

• 16-bit memory card

• 16-bit I/O card

• CardBus cards

• UltraMedia card

Table 3−10. Interrupt Mask and Flag Registers

CARD TYPE EVENT MASK FLAG

16-bit memory

16-bit I/O Change in card status (STSCHG) ExCA offset 05h/805h bit 0 ExCA offset 04h/804h bit 0 16-bit I/O Interrupt request (IREQ) Always enabled PCI configuration offset 91h bit 0

All 16-bit PC Cards/Smart

Card adaptors

Battery conditions (BVD1, BVD2) ExCA offset 05h/805h bits 1 and 0 ExCA offset 04h/804h bits 1 and 0 Wait states (READY) ExCA offset 05h/805h bit 2 ExCA offset 04h/804h bit 2

Power cycle complete ExCA offset 05h/805h bit 3 ExCA of fset 04h/804h bit 3

Change in card status (CSTSCHG) Socket mask bit 0 Socket event bit 0 Interrupt request (CINT) Always enabled PCI configuration offset 91h bit 0 Power cycle complete Socket mask bit 3 Socket event bit 3 Card insertion or removal Socket mask bits 2 and 1 Socket event bits 2 and 1

Functional interrupt events are valid only for CardBus and 16-bit I/O cards; that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the card type.

Table 3−11. PC Card Interrupt Events and Description

CARD TYPE EVENT TYPE SIGNAL DESCRIPTION

16-bit

memory

16-bit I/O

CardBus

All PC Cards

adaptors

(BVD1, BVD2)

Wait states

(READY)

Change in card

status (STSCHG

Interrupt request

(IREQ

)

Change in card

status (CSTSCHG)

Interrupt request

(CINT

)

Card insertion

or removal

Power cycle

complete

CSTSCHG //

CSC

CSC CINT // READY(IREQ)

CSC

)

Functional CINT // READY(IREQ)

CSC

Functional CINT // READY(IREQ)

CSC

CSC N/A

BVD1(STSCHG

CAUDIO // BVD2(SPKR)

CSTSCHG //

BVD1(STSCHG

CSTSCHG //

BVD1(STSCHG

CCD1 // CD1,

CCD2

// CD2

A transition on BVD1 indicates a change in the PC Card battery conditions.

)

A transition on BVD2 indicates a change in the PC Card battery conditions.

A transition on READY indicates a change in the ability of the memory PC Card to accept or provide data.

The assertion of STSCHG indicates a status change on the PC Card.

)

The assertion of IREQ indicates an interrupt request from the PC Card.

The assertion of CSTSCHG indicates a status change on the PC Card.

)

The assertion of CINT indicates an interrupt request from the PC Card.

A transition on either CD1//CCD1 or CD2//CCD2 indicates an insertion or removal of a 16-bit or CardBus PC Card.

An interrupt is generated when a PC Card power-up cycle has completed.

September 2005 SCPS110

Principles of Operation

The naming convention for PC Card signals describes the function for CardBus, 16-bit memory, and 16-bit I/O cards. For example, CINT cards, and IREQ

for 16-bit I/O cards. The CardBus signal name is first. The 16-bit memory card signal name

//READY(IREQ) includes CINT for CardBus cards, READY for 16-bit memory

follows after a double slash (//) with the 16-bit I/O card signal name second, enclosed in parentheses. The 1997 PC Card Standard describes the power-up sequence that must be followed by the controller when

an insertion event occurs and the host requests that the socket V of this power-up sequence, the PCIxx12 interrupt scheme can be used to notify the host system (see Table 3−11), denoted by the power cycle complete event. This interrupt source is considered a PCIxx12 internal event, because it depends on the completion of applying power to the socket rather than on a signal change at the PC Card interface.

3.7.2 Interrupt Masks and Flags

Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3−11 by setting the appropriate bits in the PCIxx12 controller. By individually masking the interrupt sources listed, software can control those events that cause a PCIxx12 interrupt. Host software has some control over the system interrupt the controller asserts by programming the appropriate routing registers. The controller allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections.

When an interrupt is signaled by the controller, the interrupt service routine must determine which of the events listed in Table 3−10 caused the interrupt. Internal registers in the controller provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken.

and VPP be powered. Upon completion

Table 3−10 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.

Notice that there is not a mask bit to stop the controller from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there must never be a card interrupt that does not require service after proper initialization.

Table 3−10 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1b to the flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20), and defaults to the flag-cleared-on-read method.

The CardBus-related interrupt flags can be cleared by an explicit write of 1b to the interrupt flag in the socket event register (see Section 6.1). Although some of the functionality is shared between the CardBus registers and the ExCA registers, software must not program the chip through both register sets when a CardBus card is functioning.

3.7.3 Using Parallel IRQ Interrupts

The seven multifunction terminals, MFUNC6−MFUNC0, implemented in the PCIxx12 controller can be routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset 92h, see Section 4.38), to select the parallel IRQ signaling scheme. See Section 4.35, Multifunction Routing Status Register, for details on configuring the multifunction terminals.

A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA requirement is dictated by certain card and socket-services software. The INTA the MFUNC0 terminal for INTA to INTA

. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.

signaling. The INTRTIE bit is used, in this case, to route socket interrupt events

, to signal CSC events. This requirement calls for routing

September 2005SCPS110

Principles of Operation

(INT_SEL field) in SD host

media general control

(INT_SEL field) in SD host

Card general control

As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ9, IRQ10, and IRQ15. The multifunction routing status register must be programmed to a value of 0A9F 5432h. This value routes the MFUNC0 terminal to INTA in Figure 3−12. Not shown is that INTA

must also be routed to the programmable interrupt controller (PIC),

signaling and routes the remaining terminals as illustrated

or to some circuitry that provides parallel PCI interrupts to the host.

PCIxx12

MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6

Figure 3−12. IRQ Implementation

Power-on software is responsible for programming the multifunction routing status register to reflect the IRQ configuration of a system implementing the controller. The multifunction routing status register is a global register that is shared between the four PCIxx12 functions. See Section 4.35, Multifunction Routing Status Register,

for details on configuring the multifunction terminals.

The parallel ISA-type IRQ signaling from the MFUNC6−MFUNC0 terminals is compatible with the input signal requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. Design constraints may demand more MFUNC6−MFUNC0 IRQ terminals than the controller makes available.

3.7.4 Using Parallel PCI Interrupts

Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and when only IRQs are serialized with the IRQSER protocol. The INTA to MFUNC terminals (MFUNC0, MFUNC1, MFUNC2, and MFUNC4). If bit 29 (INTRTIE) is set in the system control register (PCI offset 80h, see Section 4.29), then INTA bit is set, all functions return a value of 01h on reads from the interrupt pin register for both parallel and serial PCI interrupts.

PIC IRQ3 IRQ4

IRQ5 IRQ15 IRQ9 IRQ10

, INTB, INTC, and INTD can be routed

and INTB are tied internally . When the TIEALL

INTRTIE

Bit

0 0 0x01 (INTA) 0x02 (INTB)

1 0 0x01 (INTA) 0x01 (INTA)

X 1 0x01 (INTA) 0x01 (INTA) 0x01 (INTA) 0x01 (INTA) 0x01 (INTA)

3.7.5 Using Serialized IRQSER Interrupts

September 2005 SCPS110

The INTRTIE and TIEALL bits affect the read-only value provided through accesses to the interrupt pin register (PCI offset 3Dh, see Section 4.24). Table 3−12 summarizes the interrupt signaling modes.

Table 3−12. Interrupt Pin Register Cross Reference

TIEALL

Bit

INTPIN

Function 0

(CardBus)

INTPIN

Function 1

(1394 OHCI)

INTPIN

Function 2

(Flash Media)

Determined by bits 6−5 (INT_SEL field) in flash

Section 11.21)

INTPIN

Function 3

(SD Host)

Determined by bits 6−5

general control register

(see Section 12.22)

INTPIN

Function 4

(Smart Card)

Determined by bits 6−5

(INT_SEL field) in Smart

Section 13.22)

The serialized interrupt protocol implemented in the PCIxx12 controller uses a single terminal to communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA INTC

, and INTD. For details on the IRQSER protocol, refer to the document Serialized IRQ Support for PCI

, INTB,

Systems.

Principles of Operation

3.7.6 SMI Support in the PCIxx12 Controller

The PCIxx12 controller provides a mechanism for interrupting the system when power changes have been made to the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme. SMI interrupts are generated by the controller , when enabled, after either a write cycle to the socket control register (CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA offset 02h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch interface.

The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29). These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3−13 describes the SMI control bits function.

Table 3−13. SMI Control

BIT NAME FUNCTION

SMIROUTE This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2. SMISTAT This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1b. SMIENB When set, SMI interrupt generation is enabled.

If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per-socket basis. The CSC interrupt can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20).

If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNC3 or MFUNC6 through the multifunction routing status register (PCI offset 8Ch, see Section 4.35).

3.8 Power-Management Overview

In addition to the low-power CMOS technology process used for the PCIxx12 controller, various features are designed into the controller to allow implementation of popular power-saving techniques. These features and techniques are as follows:

• Clock run protocol

• Cardbus PC Card power management

• 16-bit PC Card power management

• Suspend mode

• Ring indicate

• PCI power management

• Cardbus bridge power management

• ACPI support

September 2005SCPS110

EEPROM

PCI Bus

PCIxx12

SD/MMC

MS/MSPRO

SM/xD

Principles of Operation

Power Switch

1394a

Socket

Power Switch

†

The system connection to GRST be asserted for subsequent warm resets.

is implementation-specific. GRST must be asserted on initial power up of the PCIxx12 controller. PRST must

Smart

Card

Figure 3−13. System Diagram Implementing CardBus Device Class Power Management

3.8.1 1394 Power Management (Function 1)

The PCIxx12 controller complies with PCI Bus Power Management Interface Specification. The controller supports the D0 (uninitialized), D0 (active), D1, D2, and D3 power states as defined by the power-management definition in the 1394 Open Host Controller Interface Specification, Appendix A.4 and PCI Bus Power Management Specification. PME A.4.2, the 1394 OHCI sets PMCSR.PME_STS in the D0 state due to unmasked interrupt events. In previous OHCI implementations, unmasked interrupt events were interpreted as (IntEvent.n && IntMask.n && IntMask.masterIntEnable), where n represents a specific interrupt event. Based on feedback from Microsoft this implementation may cause problems with the existing Windows power-management arcitecture a s a PME and an interrupt could be simultaneously signaled on a transition from the D1 to D0 state where interrupts were enabled to generate wake events. If bit 10 (ignore_mstrIntEna_for_pme) in the PCI miscellaneous configuration register (OHCI offset F0h, see Section 7.23) is set, then the controller implements the preferred behavior as (IntEvent.n && IntMask.n). Otherwise, the controller implements the preferred behavior as (IntEvent.n && IntMask.n && IntMask.masterIntEnable). In addition, when the ignore_mstrIntEna_for_pme bit is set, it causes bit 26 of the OHCI vendor ID register (OHCI offset 40h, see Section 8.15) to read 1b, otherwise, bit 26 reads 0b. An open drain buffer is used for PME control/status register (PCI offset A4h, see Section 4.43), then insertion of a PC Card causes the controller to assert PME

, which wakes the system from a low power state (D3, D2, or D1). The OS services PME and

takes the PCIxx12 controller to the D0 state.

is supported to provide notification of wake events. Per Section

SD/MMC

Power Switch

. If PME is enabled in the power-management

3.8.2 Integrated Low-Dropout Voltage Regulator (LDO-VR)

The PCIxx12 controller requires 1.5-V core voltage. The core power can be supplied by the controller itself using the internal the VR_PORT terminal. Table 3−14 lists the requirements for both the internal core power supply and the external core power supply.

September 2005 SCPS110

LDO-VR. The core power can be alternatively supplied by an external power supply through

Principles of Operation

Table 3−14. Requirements for Internal/External 1.5-V Core Power Supply

SUPPLY V

Internal 3.3 V GND 1.5-V output

External 3.3 V V

VR_EN VR_PORT NOTE

1.5-V input

3.8.3 Clock Run Protocol

The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCIxx12 controller. CLKRUN implement CLKRUN are provided. For details on the CLKRUN

The controller does not permit the central resource to stop the PCI clock under any of the following conditions:

• Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.

• The 16-bit PC Card resource manager is busy.

• The PCIxx12 CardBus master state machine is busy. A cycle may be in progress on CardBus.

• The PCIxx12 master is busy. There may be posted data from CardBus, 1394, flash media core, SD host

core, or Smart Card core to PCI in the controller or DMA is active.

signaling is provided through the MFUNC6 terminal. Since some chip sets do not

, this is not always available to the system designer, and alternate power-saving features

Internal 1.5-V LDO-VR is enabled. A 1.0-µF bypass capacitor is required on the VR_PORT terminal for decoupling. This output is not for external use.

Internal 1.5-V LDO-VR is disabled. An external 1.5-V power supply, of minimum 50-mA capacity, is required. A 0.1-µF bypass capacitor on the VR_PORT terminal is required.

protocol see the PCI Mobile Design Guide.

• Interrupts are pending from CardBus, 1394, flash media core, SD host core, or Smart Card core

• The CardBus CCLK for the socket has not been stopped by the PCIxx12 CCLKRUN manager.

• Bit 0 (KEEP_PCLK) in the miscellaneous configuration register (PCI offset F0h, see Section 7.23) is set.

• The 1394 resource manager is busy.

• The PCIxx12 1394 master state machine is busy. A cycle may be in progress on 1394.

• PC Card interrogation is in progress.

• Flash media or Smart Card insertion/removal processing

• The 1394 bus is not idle.

• Smart card DES request or decryption in progress

The controller restarts the PCI clock using the CLKRUN protocol under any of the following conditions:

• A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card.

• A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in the socket.

• A CardBus attempts to start the CCLK using CCLKRUN.

• A CardBus card arbitrates for the CardBus bus using CREQ.

• A 1394 device changes the status of the twisted pair lines from idle to active.

• Bit 1 (KEEPCLK) in the system control register (PCI offset 80h, see Section 4.29) is set.

• Data is in any of the FIFOs (receive or transmit).

• The master state machine is busy.

• There are pending interrupts from CardBus, 1394, flash media core, SD host core, or Smart Card core.

3.8.4 CardBus PC Card Power Management

The PCIxx12 controller implements its own card power-management engine that can turn off the CCLK to a socket when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN

interface to control this clock management.

September 2005SCPS110

3.8.5 16-Bit PC Card Power Management

The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/802h, see Section 5.3) and PWRDWN bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20) are provided for 16-bit PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function when there is no card activity.

NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and PWRDWN modes.

3.8.6 Suspend Mode

The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global reset) signal from the PCIxx12 controller. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the controller in order to minimize power consumption.

It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt stream, then the PCI clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor an external clock is routed to the serial-interrupt state machine. Figure 3−14 is a signal diagram of the suspend function.

Principles of Operation

RESET

GNT

SUSPEND

PCLK

RESETIN

SUSPENDIN

PCLKIN

External Terminals

Internal Signals

Figure 3−14. Signal Diagram of Suspend Function

September 2005 SCPS110

Principles of Operation

3.8.7 Requirements for Suspend Mode

The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) which would require the reconfiguration of the PCIxx12 controller by software. Asserting the SUSPEND places the PCI outputs of the controller in a high-impedance state and gates the PCLK signal internally to the controller unless a PCI transaction is currently in process (GNT not be parked on the controller when SUSPEND state.

signal

is asserted). It is important that the PCI bus

is asserted because the outputs are in a high-impedance

The GPIOs, MFUNC signals, and RI_OUT in the appropriate PCIxx12 registers.

3.8.8 Ring Indicate

The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode and wake-up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform requirements. RI_OUT conditions:

• A 16-bit PC Card modem in a powered socket asserts RI incoming call.

• A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake-up.

• A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery

voltage levels.

Figure 3−15 shows various enable bits for the PCIxx12 RI_OUT masking of CSC events. See Table 3−10 for a detailed description of CSC interrupt masks and flags.

PC Card

Socket A

signal are all active during SUSPEND, unless they are disabled

on the PCIxx12 controller can be asserted under any of the following

to indicate to the system the presence of an

function; however, it does not show the

RI_OUT Function

Card

I/F

CSTSMASK

CSC

RINGEN

CDRESUME

RIENB

RI_OUT

CSC

Figure 3−15. RI_OUT Functional Diagram

from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register (ExCA offset 03h/803h, see Section 5.4). This is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket.

The CBWAKE signaling to RI_OUT

is enabled through the same mask as the CSC event for CSTSCHG. The mask bit (bit 0, CSTSMASK) is programmed through the socket mask register (CB offset 04h, see Section 6.2) in the CardBus socket registers.

RI_OUT

can be routed through any of three different pins, RI_OUT/PME, MFUNC2, or MFUNC4. The RI_OUT function is enabled by setting bit 7 (RIENB) in the card control register (PCI offset 91h, see Section 4.37). The PME

function is enabled by setting bit 8 (PME_ENABLE) in the power-management control/status register (PCI offset A4h, see Section 4.43). When bit 0 (RIMUX) in the system control register (PCI offset 80h, see Section 4.29) is set to 0b, both the RI_OUT

function and the PME function are routed to the RI_OUT/PME terminal. Therefore, in a system using both the RI_OUT function and the PME function, RIMUX must be set to 1b and RI_OUT

must be routed to either MFUNC2 or MFUNC4.

September 2005SCPS110

Principles of Operation

3.8.9 PCI Power Management

3.8.9.1 CardBus (Function 0) Power Management

The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure required to let the operating system control the power of PCI functions. This is accomplished by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of seven power-management states, resulting in varying levels of power savings.

The seven power-management states of PCI functions are:

• D0-uninitialized − Before controller configuration, controller not fully functional

• D0-active − Fully functional state

• D1 − Low-power state

• D2 − Low-power state

• D3

NOTE 1: In the D0-uninitialized state, the PCIxx12 controller does not generate PME and/or interrupts. When bits 0 (IO_EN) and 1 (MEM_EN)

of the command register (PCI offset 04h, see Section 4.4) are both set, the PCIxx12 controller switches the state to D0-active. Transition from D3 D0-uninitialized state immediately.

NOTE 2: The PWR_ST ATE bits (bits 1−0) of the power-management control/status register (PCI offset A4h, see Section 4.43) only code for four

power states, D0, D1, D2, and D3 is not accessible in the D3

Similarly, bus power states of the PCI bus are B0−B3. The bus power states B0−B3 are derived from the device power state of the originating bridge device.

− Low-power state. Transition state before D3

hot

− PME signal-generation capable. Main power is removed and VAUX is available.

cold

− No power and completely nonfunctional

off

to the D0-uninitialized state happens at the deassertion of PRST

cold

. The differences between the three D3 states is invisible to the software because the controller

hot

cold

or D3

off

state.

cold

. The assertion of GRST forces the controller to the

For the operating system (OS) to manage the controller power states on the PCI bus, the PCI function must support four power-management operations. These operations are:

• Capabilities reporting

• Power status reporting

• Setting the power state

• System wake-up

The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of capabilities in addition to the standard PCI capabilities is indicated by a 1b in bit 4 (CAPLIST) of the status register (PCI offset 06h, see Section 4.5).

The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCIxx12 controller, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an of fset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, then the next item pointer must be set to 0. The registers following the next item pointer are specific to the capability of the function. The PCI power-management capability implements the register block outlined in Table 3−15.

Table 3−15. Power-Management Registers

Power-management capabilities Next item pointer Capability ID A0h

Data Power-management control/status register bridge support extensions Power-management control/status (CSR) A4h

The power-management capabilities register (PCI offset A2h, see Section 4.42) provides information on the capabilities of the function related to power management. The power-management control/status register (PCI offset A4h, see Section 4.43) enables control of power-management states and enables/monitors power-management events. The data register is an optional register that can provide dynamic data.

September 2005 SCPS110

Principles of Operation

For more information on PCI power management, see the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges.

3.8.9.2 OHCI 1394 (Function 1) Power Management

The PCIxx12 controller complies with the PCI Bus Power Management Interface Specification. The controller supports the D0 (unitialized), D0 (active), D1, D2, and D3 power states as defined by the power-management definition in the 1394 Open Host Controller Interface Specification, Appendix A4.

Table 3−16. Function 1 Power-Management Registers

Power-management capabilities Next item pointer Capability ID 44h

Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 48h

3.8.9.3 Flash Media (Function 2) Power Management

The PCI Bus Power Management Interface Specification is applicable for the flash media dedicated sockets. This function supports the D0 and D3 power states.

Table 3−17. Function 2 Power-Management Registers

Power-management capabilities Next item pointer Capability ID 44h

Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 48h

3.8.9.4 SD Host (Function 3) Power Management

The PCI Bus Power Management Interface Specification is applicable for the SD host dedicated sockets. This function supports the D0 and D3 power states.

Table 3−18. Function 3 Power-Management Registers

Power-management capabilities Next item pointer Capability ID 80h

Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 84h

3.8.9.5 Smart Card (Function 4) Power Management

The PCI Bus Power Management Interface Specification is applicable for the Smart Card dedicated sockets. This function supports the D0 and D3 power states.

Table 3−19. Function 4 Power-Management Registers

Power-management capabilities Next item pointer Capability ID 44h

Data Power-management control/status register bridge support extensions Power-management control/status (CSR) 48h

3.8.10 CardBus Bridge Power Management

The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3

The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges for D3 wake-up are as follows:

• Preservation of device context. The specification states that a reset must occur during the transition from

D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear the PME

context registers.

hot

or D3

without losing wake-up context (also called PME context).

cold

September 2005SCPS110

Principles of Operation

• Power source in D3 The Texas Instruments PCIxx12 controller addresses these D3 wake-up issues in the following manner:

• Two resets are provided to handle preservation of PME

− Global reset (GRST controller in its default state and requires BIOS to configure the controller before becoming fully functional.

− PCI reset (PRST then PME

context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset.

Please see the master list of PME

• Power source in D3 auxiliary power source must be supplied to the PCIxx12 V

Implementation Guide for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges for further information.

3.8.11 ACPI Support

The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver . The PCIxx12 controller of fers a generic interface that is compliant with ACPI design rules.

Two doublewords of general-purpose ACPI programming bits reside in PCIxx12 PCI configuration space at offset 88h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event status and enable bits reside in the general-purpose event status register (PCI offset 88h, see Section 4.31) and general-purpose event enable register (PCI offset 89h, see Section 4.32). The status and enable bits are implemented as defined by ACPI and illustrated in Figure 3−16.

if wake-up support is required from this state.

cold

context bits:

) is used only on the initial boot up of the system after power up. It places the

) has dual functionality based on whether PME is enabled or not. If PME is enabled,

context bits in Section 3.8.12.

if wake-up support is required from this state. Since VCC is removed in D 3

cold

Event Input

Enable Bit

Status Bit

Event Output

terminals. Consult the PCI14xx

cold

, an

Figure 3−16. Block Diagram of a Status/Enable Cell

The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the pending status bit. The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. A hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events.

For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.

3.8.12 Master List of PME Context Bits and Global Reset-Only Bits

PME context bit means that the bit is cleared only by the assertion of GRST when the PME enable bit, bit 8 of the power-management control/status register (PCI offset A4h, see Section 4.43) is set. If PME enabled, then these bits are cleared when either PRST

The PME

context bits (function 0) are:

• Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6

• System control register (PCI offset 80h, see Section 4.29): bits 10−8

• Power-management control/status register (PCI offset A4h, see Section 4.43): bit 15

• ExCA power control register (ExCA 802h, see Section 5.3): bits 7, 5 (82365SL mode only), 7, 4, 3, 1, 0

• ExCA interrupt and general control (ExCA 803h, see Section 5.4): bits 6, 5

September 2005 SCPS110

or GRST is asserted.

is not

Principles of Operation

• ExCA card status-change register (ExCA 804h, see Section 5.5): bits 3−0

• ExCA card status-change interrupt configuration register (ExCA 805h, see Section 5.6): bits 3−0

• ExCA card detect and general control register (ExCA 816h, see Section 5.19): bits 7, 6

• Socket event register (CardBus offset 00h, see Section 6.1): bits 3−0

• Socket mask register (CardBus offset 04h, see Section 6.2): bits 3−0

• Socket present state register (CardBus offset 08h, see Section 6.3): bits 13−7, 5−1

• Socket control register (CardBus offset 10h, see Section 6.5): bits 6−4, 2−0

Global reset-only bits, as the name implies, are cleared only by GRST

. These bits are never cleared by PRST, regardless of the setting of the PME enable bit. The GRST signal is gated only by the SUSPEND signal. This means that assertion of SUSPEND Figure 3−13 is a diagram showing the application of GRST

blocks the GRST signal internally, thus preserving all register contents.

and PRST.

The global reset-only bits (function 0) are:

• Status register (PCI offset 06h, see Section 4.5): bits 15−11, 8

• Secondary status register (PCI offset 16h, see Section 4.14): bits 15−11, 8

• Subsystem vendor ID register (PCI offset 40h, see Section 4.26): bits 15–0

• Subsystem ID register (PCI offset 42h, see Section 4.27): bits 15–0

• PC Card 16-bit I/F legacy-mode base-address register (PCI offset 44h, see Section 4.28): bits 31−0

• System control register (PCI offset 80h, see Section 4.29): bits 31−24, 22−13, 11, 6−0

• General control register (PCI offset 84h, see Section 4.30): bits 31−16, 10−0

• General-purpose event status register (PCI offset 88h, see Section 4.31): bits 7, 6, 4−0

• General-purpose event enable register (PCI offset 89h, see Section 4.32): bits 7, 6, 4−0

• General-purpose output register (PCI offset 8Bh, see Section 4.34): bits 4−0

• Multifunction routing register (PCI offset 8Ch, see Section 4.35): bits 31−0

• Retry status register (PCI offset 90h, see Section 4.36): bits 7−5, 3, 1

• Card control register (PCI offset 91h, see Section 4.37): bits 7, 2−0

• Device control register (PCI offset 92h, see Section 4.38): bits 7−5, 3−0

• Diagnostic register (PCI offset 93h, see Section 4.39): bits 7−0

• Power-management capabilities register (PCI offset A2h, see Section 4.42): bit 15

• Power-management CSR register (PCI offset A4h, see Section 4.43): bits 15, 8

• Serial bus data register (PCI offset B0h, see Section 4.46): bits 7−0

• Serial bus index register (PCI offset B1h, see Section 4.47): bits 7−0

• Serial bus slave address register (PCI offset B2h, see Section 4.48): bits 7−0

• Serial bus control/status register (PCI offset B3h, see Section 4.49): bits 7, 3−0

• ExCA identification and revision register (ExCA 800h, see Section 5.1): bits 7−0

• ExCA global control register (ExCA 81Eh, see Section 5.20): bits 2−0

• CardBus socket power-management register (CardBus 20h, see Section 6.6): bits 25, 24

The global reset-only bit (function 1) is:

• Subsystem vendor ID register (PCI offset 2Ch, see Section 7.12): bits 15−0

• Subsystem ID register (PCI offset 2Eh, see Section 7.12): bits 15−0

• Minimum grant and maximum latency register (PCI offset 3Eh, see Section 7.16): bits 15−0

• Power-management control and status register (PCI offset 48h, see Section 7.20): bits 15, 8, 1, 0

• PHY control register (PCI offset ECh, see Section 7.22): bits 7, 4−0

• Miscellaneous configuration register (PCI offset F0h, see Section 7.23): bits 15−7, 5−0

• Link enhancement control register (PCI offset F4h, see Section 7.24): bits 15−12, 10, 8, 7, 2, 1

• Subsystem access register (PCI offset F8h, see Section 7.25): bits 31−0

• OHCI version register (OHCI offset 00h, see Section 8.1): bits 24

• Bus options register (OHCI offset 20h, see Section 8.9): bits 15−12

• GUID high register (OHCI offset 24h, see Section 8.10): bits 31−0

• GUID low register (OHCI offset 28h, see Section 8.11): bits 31−0

• Host controller control register (OHCI offset 50h/54h, see Section 8.16): bit 23

September 2005SCPS110

Principles of Operation

• Link control register (OHCI offset E0h/E4h, see Section 8.31): bit 6

• Link enhancement control set/clear register (TI Extension offset A88/A8Ch, see Section 9.4): bits 15−12,

10, 8, 7, 2, 1

The global reset-only (function 2) register bits:

• Subsystem vendor ID register (PCI offset 2Ch, see Section 11.9): bits 15–0

• Subsystem ID register (PCI offset 2Eh, see Section 11.10): bits 15–0

• Power-management control and status register (PCI offset 48h, see Section 11.18): bits 15, 8, 1, 0

• General control register (PCI offset 4Ch, see Section 11.21): bits 7−4, 2–0

• Subsystem access register (PCI offset 50h, see Section 11.22): bits 31−0

• Diagnostic register (PCI offset 54h, see Section 11.23): bits 31–0

The global reset-only (function 3) register bits:

• Subsystem vendor ID register (PCI offset 2Ch, see Section 12.9): bits 15–0

• Subsystem ID register (PCI offset 2Eh, see Section 12.10): bits 15–0

• Power-management control and status register (PCI offset 84h, see Section 12.19): bits 15, 8, 1, 0

• General control register (PCI offset 88h, see Section 12.22): bits 6−3, 0

• Subsystem access register (PCI offset 8Ch, see Section 12.23): bits 31−0

• Diagnostic register (PCI offset 90h, see Section 12.24): bits 31–0

• Slot 0 max current register (PCI offset 94h, see Section 12.25): bits 7−0

The global reset-only (function 4) register bits:

• Subsystem vendor ID register (PCI offset 2Ch, see Section 13.10): bits 15–0

• Subsystem ID register (PCI offset 2Eh, see Section 13.11): bits 15–0

• Power-management control and status register (PCI offset 48h, see Section 13.19): bits 15, 8, 1, 0

• General control register (PCI offset 4Ch, see Section 13.22): bits 7−4, 0

• Subsystem ID alias register (PCI offset 50h, see Section 13.23): bits 31−0

• Class code alias register (PCI offset 54h, see Section 13.24): bits 31−0

• Smart card configuration 1 register (PCI offset 58h, see Section 13.25): bits 31−0

• Smart card configuration 2 register (PCI offset 5Ch, see Section 13.26): bits 31−0

September 2005 SCPS110

Principles of Operation

3.9 IEEE 1394 Application Information

3.9.1 PHY Port Cable Connection

PCIxx12

Cable Port

CPS

TPBIAS

TPA+ TPA−

TPB+ TPB−

220 pF

(see Note A)

400 kΩ

1 µF

56 Ω56 Ω

5 kΩ

Cable

Power

Pair

Cable

Pair

Cable

Pair

Outer Shield

Termination

NOTE A: IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended.

Figure 3−17. TP Cable Connections

Outer Cable Shield

1 MΩ

Chassis Ground

0.01 µF

0.001 µF

Figure 3−18. Typical Compliant DC Isolated Outer Shield Termination

September 2005SCPS110

Figure 3−19. Non-DC Isolated Outer Shield Termination

3.9.2 Crystal Selection

The PCIxx12 controller is designed to use an external 24.576-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates.

A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394-1995. Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHY devices must be able to compensate for this difference over the maximum packet length. Large clock variations may cause resynchronization overflows or underflows, resulting in corrupted packet data.

The following are some typical specifications for crystals used with the PHYs from TI in order to achieve the required frequency accuracy and stability:

Principles of Operation

Outer Cable Shield

Chassis Ground

• Crystal mode of operation: Fundamental

• Frequency tolerance @ 25°C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with ±30 ppm frequency tolerance is recommended for adequate margin.

• Frequency stability (over temperature and age): A crystal with ±30 ppm frequency stability is

recommended for adequate margin.

• Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent upon the load capacitance specified for the crystal. Total load capacitance (C

) is a function of not only

the discrete load capacitors, but also board layout and circuit. It is recommended that load capacitors with a maximum of ±5% tolerance be used.

For example, load capacitors (C9 and C10 in Figure 3−20) of 16 pF each were appropriate for the layout of the PCIxx12 evaluation module (EVM), which uses a crystal specified for 12-pF loading. The load specified for the crystal includes the load capacitors (C9 and C10), the loading of the PHY pins (C of the board itself (C

). The value of C

is typically about 1 pF, and CBD is typically 0.8 pF per centimeter

PHY

), and the loading

PHY

of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is:

C9 C10 C9 ) C10

) C

PHY

) C

September 2005 SCPS110

Principles of Operation

C10

24.576 MHz

PHY

+ C

Figure 3−20. Load Capacitance for the PCIxx12 PHY

The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise introduced into the PHY phase-lock loop, and minimizing any emissions from the circuit. The crystal and two load capacitors must be considered as a unit during layout. The crystal and the load capacitors must be placed as close as possible to one another while minimizing the loop area created by the combination of the three components. Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant current (Is) that flows in this resonant circuit. This layout unit (crystal and load capacitors) must then be placed as close as possible to the PHY X1 and X0 terminals to minimize etch lengths, as shown in Figure 3−21.

C9 C10

For more details on crystal selection, see application report SLLA051 available from the TI website: http://www.ti.com/sc/1394.

3.9.3 Bus Reset

In the PCIxx12 controller, the initiate bus reset (IBR) bit may be set to 1b in order to initiate a bus reset and initialization sequence. The IBR bit is located in PHY register 1, along with the root-holdoff bit (RHB) and Gap_Count field, as required by IEEE Std 1394a-2000. Therefore, whenever the IBR bit is written, the RHB and Gap_Count are also written.

The RHB and Gap_Count may also be updated by PHY-config packets. The PCIxx12 controller is IEEE 1394a-2000 compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and Gap_Count to be loaded, unlike older IEEE 1394-1995 compliant PHY devices which decode only received PHY-config packets.

The gap-count is set to the maximum value of 63 after 2 consecutive bus resets without an intervening write to the Gap_Count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a PHY-config packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have updated their RHBs and Gap_Count values, without having the Gap_Count set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the Gap_Count of each node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, all other nodes on the bus have their Gap_Count values set to 63, while this node Gap_Count remains set to the value just loaded by the write to PHY register 1.

Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the IBR bit, RHB, and Gap_Count in PHY register 1:

Figure 3−21. Recommended Crystal and Capacitor Layout

September 2005SCPS110

Principles of Operation

• Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHBs and Gap_Count values and to ensure that a subsequent new connection to the bus causes the Gap_Count to be set to 63 on all nodes in the bus. If this bus reset is initiated by setting the IBR bit to 1b, then the RHB and Gap_Count field must also be loaded with the correct values consistent with the just transmitted PHY-config packet. In the PCIxx12 controller, the RHB and Gap_Count are updated to their correct values upon the transmission of the PHY-config packet, so these values may first be read from register 1 and then rewritten.

• Other than to initiate the bus reset, which must follow the transmission of a PHY-config packet, whenever the IBR bit is set to 1b in order to initiate a bus reset, the Gap_Count value must also be set to 63 so as to be consistent with other nodes on the bus, and the RHB must be maintained with its current value.

• The PHY register 1 must not be written to except to set the IBR bit. The RHB and Gap_Count must not be written without also setting the IBR bit to 1b.

An alternative and preferred method is for software to use the initiate short bus reset (ISBR) in PHY register 5 since it does not have any side effects on the gap count.

September 2005 SCPS110

PC Card Controller Programming Model

4 PC Card Controller Programming Model

This chapter describes the PCIxx12 PCI configuration registers that make up the 256-byte PCI configuration header for each PCIxx12 function. There are some bits which affect more than function 0, but which, in order to work properly, must be accessed only through function 0. These are called global bits. Registers containing one or more global bits are denoted by § in Table 4−2.

Any bit followed by a † is not cleared by the assertion of PRST Section 3.8.10, for more details) if PME only by GRST

. If PME is not enabled, then these bits are cleared by GRST or PRST. These bits are sometimes

is enabled (PCI offset A4h, bit 8). In this case, these bits are cleared

referred to as PME context bits and are implemented to allow PME transition from D3

hot

or D3

cold

to D0.

If a bit is followed by a ‡, then this bit is cleared only by GRST enabled). These bits are intended to maintain device context such as interrupt routing and MFUNC programming during warm resets.

A bit description table, typically included when the register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1 describes the field access tags.

Table 4−1. Bit Field Access Tag Descriptions

ACCESS TAG NAME MEANING

R Read Field can be read by software.

W Write Field can be written by software to any value.

S Set Field can be set by a write of 1b. Writes of 0b have no effect. C Clear Field can be cleared by a write of 1b. Writes of 0b have no effect. U Update Field can be autonomously updated by the PCIxx12 controller.

4.1 PCI Configuration Register Map (Function 0)

(see CardBus Bridge Power Management,

context to be preserved during the

in all cases (not conditional on PME being

The PCIxx12 controller is a multifunction PCI device, and the PC Card controller is integrated as PCI function

0. The configuration header, compliant with the PCI Local Bus Specification as a CardBus bridge header, is PC99/PC2001 compliant as well. Table 4−2 illustrates the PCI configuration register map, which includes both the predefined portion of the configuration space and the user-definable registers.

Table 4−2. Function 0 PCI Configuration Register Map

Device ID Vendor ID 00h

Status ‡ Command 04h

Class code Revision ID 08h

BIST Header type Latency timer Cache line size 0Ch

CardBus socket registers/ExCA base address register 10h

Secondary status ‡ Reserved Capability pointer 14h

CardBus latency timer Subordinate bus number CardBus bus number PCI bus number 18h

CardBus memory base register 0 1Ch

CardBus memory limit register 0 20h

CardBus memory base register 1 24h

CardBus memory limit register 1 28h

‡

One or more bits in this register are cleared only by the assertion of GRST

September 2005SCPS110

PC Card Controller Programming Model

Table 4−2. Function 0 PCI Configuration Register Map (Continued)

CardBus I/O base register 0 2Ch

CardBus I/O limit register 0 30h

CardBus I/O base register 1 34h

CardBus I/O limit register 1 38h

Bridge control † Interrupt pin Interrupt line 3Ch

Subsystem ID ‡ Subsystem vendor ID ‡ 40h

PC Card 16-bit I/F legacy-mode base-address ‡ 44h

Reserved 48h−7Ch

System control †‡§ 80h

General control ‡§ Reserved MC_CD debounce ‡ 84h

General-purpose output ‡ General-purpose input

Multifunction routing status ‡ 8Ch

Diagnostic ‡§ Device control ‡§ Card control ‡§ Retry status ‡§ 90h

Reserved 94h−9Ch

Power management capabilities ‡ Next item pointer Capability ID A0h

Power management data

(Reserved)

Serial bus control/status ‡ Serial bus slave address ‡ Serial bus index ‡ Serial bus data ‡ B0h

†

One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST enabled, then this bit is cleared by the assertion of PRST

‡

One or more bits in this register are cleared only by the assertion of GRST

One or more bits in this register are global in nature and must be accessed only through function 0.

Power management

control/status bridge support

extensions

Reserved A8h−ACh

Reserved B4h−FCh

or GRST.

General-purpose event

enable ‡

Power management control/status †‡

General-purpose event

status ‡

when PME is enabled. If PME is not

88h

A4h

4.2 Vendor ID Register

The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device. The vendor ID assigned to Texas Instruments is 104Ch.

PCI register offset: 00h (Function 0) Register type: Read-only Default value: 104Ch

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0

4.3 Device ID Register Function 0

This read-only register contains the device ID assigned by TI to the PCIxx12 CardBus controller functions.

PCI register offset: 02h (Function 0) Register type: Read-only Default value: 8039h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1

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PC Card Controller Programming Model

4.4 Command Register

The PCI command register provides control over the PCIxx12 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification (see Table 4−3). None of the bit functions in this register are shared among the PCIxx12 PCI functions. Five command registers exist in the controller, one for each function. Software manipulates the functions as separate entities when enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are internally-wired OR between the five functions, and these control bits appear to software to be separate for each function.

PCI register offset: 04h Register type: Read-only, Read/Write Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4−3. Command Register Description

BIT SIGNAL TYPE FUNCTION

15−11 RSVD R Reserved. Bits 15−11 return 00000b when read.

INTx disable. When set to 1b, this bit disables the function from asserting interrupts on the INTx signals.

0 = INTx

10 INT_DISABLE RW

9 FBB_EN R

8 SERR_EN RW

7 RSVD R Reserved. Bit 7 returns 0b when read.

6 PERR_EN RW

5 VGA_EN RW

4 MWI_EN R

3 SPECIAL R

2 MAST_EN RW

1 MEM_EN RW

0 IO_EN RW

Fast back-to-back enable. The controller does not generate fast back-to-back transactions; therefore, this bit is read-only. This bit returns a 0b when read.

System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set for the controller to report address parity errors.

Parity error response enable. This bit controls the PCIxx12 response to parity errors through the PERR signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by asserting SERR

VGA palette snoop. When set to 1b, palette snooping is enabled (i.e., the controller does not respond to palette register writes and snoops the data). When the bit is 0b, the controller treats all palette accesses like all other accesses.

Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory write-and-invalidate commands. The controller does not support memory write-and-invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0b. This bit returns 0b when read. Writes to this bit have no effect.

Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The controller does not respond to special cycle operations; therefore, this bit is hardwired to 0b. This bit returns 0b when read. Writes to this bit have no effect.

Bus master control. This bit controls whether or not the controller can act as a PCI bus initiator (master). The controller can take control of the PCI bus only when this bit is set.

Memory space enable. This bit controls whether or not the controller can claim cycles in PCI memory space.

I/O space control. This bit controls whether or not the controller can claim cycles in PCI I/O space.

assertion is enabled (default) assertion is disabled

1 = INTx

0 = Disables the SERR output driver (default) 1 = Enables the SERR

. 0 = Controller ignores detected parity errors (default) 1 = Controller responds to detected parity errors

0 = Disables the PCIxx12 ability to generate PCI bus accesses (default) 1 = Enables the PCIxx12 ability to generate PCI bus accesses

0 = Disables the PCIxx12 response to memory space accesses (default) 1 = Enables the PCIxx12 response to memory space accesses

0 = Disables the controller from responding to I/O space accesses (default) 1 = Enables the controller to respond to I/O space accesses

output driver

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PC Card Controller Programming Model

4.5 Status Register

The status register provides device information to the host system. Bits in this register can be read normally. A bit in the status register is reset when a 1b is written to that bit location; a 0b written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Bus Specification, as seen in the bit descriptions. PCI bus status is shown through each function. See Table 4−4 for a complete description of the register contents.

PCI register offset: 06h (Function 0) Register type: Read-only, Read/Write Default value: 0210h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0

Table 4−4. Status Register Description

BIT SIGNAL TYPE FUNCTION

15 ‡ PAR_ERR RW

14 ‡ SYS_ERR RW

13 ‡ MABORT RW

12 ‡ TABT_REC RW

11 ‡ TABT_SIG RW

10−9 PCI_SPEED R

8 ‡ DATAPAR RW

7 FBB_CAP R

6 UDF R

5 66MHZ R

4 CAPLIST R

3 INT_STATUS RU

2−0 RSVD R Reserved. These bits return 000b when read.

‡

This bit is cleared only by the assertion of GRST

Detected parity error. This bit is set when a parity error is detected, either an address or data parity error. Write a 1b to clear this bit.

Signaled system error. This bit is set when SERR is enabled and the controller signaled a system error to the host. Write a 1b to clear this bit.

Received master abort. This bit is set when a cycle initiated by the controller on the PCI bus has been terminated by a master abort. Write a 1b to clear this bit.

Received target abort. This bit is set when a cycle initiated by the controller on the PCI bus was terminated by a target abort. Write a 1b to clear this bit.

Signaled target abort. This bit is set by the controller when it terminates a transaction on the PCI bus with a target abort. Write a 1b to clear this bit.

DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the controller asserts this signal at a medium speed on nonconfiguration cycle accesses.

Data parity error detected. Write a 1b to clear this bit.

0 = The conditions for setting this bit have not been met 1 = A data parity error occurred and the following conditions were met:

a. PERR b. The controller was the bus master during the data parity error c. Bit 6 (PERR_EN) in the command register (offset 04h, see Section 4.4) is set

Fast back-to-back capable. The controller cannot accept fast back-to-back transactions; thus, this bit is hardwired to 0b.

UDF supported. The controller does not support user-definable features; therefore, this bit is hardwired to 0b.

66-MHz capable. The controller operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is hardwired to 0b.

Capabilities list. This bit returns 1b when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this function.

Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the command register (PCI offset 04h, see Section 4.4) is a 0b and this bit is a 1b, is the function’s INTx asserted. Setting the INT_DISABLE bit to a 1b has no effect on the state of this bit.

was asserted by any PCI device including the controller

signal

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PC Card Controller Programming Model

4.6 Revision ID Register

The revision ID register indicates the silicon revision of the controller.

PCI register offset: 08h (Function 0) Register type: Read-only Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.7 Class Code Register

The class code register recognizes PCIxx12 function 0 as a bridge device (06h) and a CardBus bridge device (07h), with a 00h programming interface.

PCI register offset: 09h (Function 0) Register type: Read-only Default value: 06 0700h

BIT NUMBER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME Base class Subclass Programming interface

RESET STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0

4.8 Cache Line Size Register

The cache line size register is programmed by host software to indicate the system cache line size.

PCI register offset: 0Ch (Function 0) Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.9 Latency Timer Register

The latency timer register specifies the latency timer for the controller, in units of PCI clock cycles. When the controller is a PCI bus initiator and asserts FRAME timer expires before the PCIxx12 transaction has terminated, then the controller terminates the transaction when its GNT

is deasserted.

PCI register offset: 0Dh Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

, the latency timer begins counting from zero. If the latency

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PC Card Controller Programming Model

4.10 Header Type Register

The header type register returns 82h when read, indicating that the function 0 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI registers 00h−7Fh, and 80h−FFh is user-definable extension registers.

PCI register offset: 0Eh (Function 0) Register type: Read-only Default value: 82h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 1 0 0 0 0 0 1 0

4.11 BIST Register

Because the controller does not support a built-in self-test (BIST), this register returns the value of 00h when read.

PCI register offset: 0Fh (Function 0) Register type: Read-only Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.12 CardBus Socket Registers/ExCA Base Address Register

This register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31−12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 1 1−0 are read-only, returning 000h when read. When software writes FFFF FFFFh to this register, the value read back is FFFF F000h, indicating that at least 4K bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h.

PCI register offset: 10h Register type: Read-only, Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4.13 Capability Pointer Register

The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. This register is read-only and returns A0h when read.

PCI register offset: 14h Register type: Read-only Default value: A0h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 1 0 1 0 0 0 0 0

September 2005 SCPS110

PC Card Controller Programming Model

4.14 Secondary Status Register

The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI offset 06h, see Section 4.5), and status bits are cleared by a writing a 1b. See Table 4−5 for a complete description of the register contents.

PCI register offset: 16h Register type: Read-only, Read/Clear Default value: 0200h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

Table 4−5. Secondary Status Register Description

BIT SIGNAL TYPE FUNCTION

15 ‡ CBPARITY RC

14 ‡ CBSERR RC

13 ‡ CBMABORT RC

12 ‡ REC_CBTA RC

11 ‡ SIG_CBTA RC

10−9 CB_SPEED R

8 ‡ CB_DPAR RC

7 CBFBB_CAP R

6 CB_UDF R

5 CB66MHZ R

4−0 RSVD R These bits return 00000b when read.

‡

This bit is cleared only by the assertion of GRST

Detected parity error . This bit is set when a CardBus parity error is detected, either an address or data parity error. Write a 1b to clear this bit.

Signaled system error . This bit is set when CSERR is signaled by a CardBus card. The controller does not assert the CSERR

Received master abort. This bit is set when a cycle initiated by the controller on the CardBus bus is terminated by a master abort. Write a 1b to clear this bit.

Received target abort. This bit is set when a cycle initiated by the controller on the CardBus bus is terminated by a target abort. Write a 1b to clear this bit.

Signaled target abort. This bit is set by the controller when it terminates a transaction on the CardBus bus with a target abort. Write a 1b to clear this bit.

CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the controller asserts this signal at a medium speed.

CardBus data parity error detected. Write a 1b to clear this bit.

0 = The conditions for setting this bit have not been met 1 = A data parity error occurred and the following conditions were met:

a. CPERR b. The controller was the bus master during the data parity error c. Bit 0 (CPERREN) in the bridge control register (PCI offset 3Eh, see Section 4.25) is set

Fast back-to-back capable. The controller cannot accept fast back-to-back transactions; therefore, this bit is hardwired to 0b.

User-definable feature support. The controller does not support user-definable features; therefore, this bit is hardwired to 0b.

66-MHz capable. The PCIxx12 CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, this bit is hardwired to 0b.

signal. Write a 1b to clear this bit.

was asserted on the CardBus interface

4.15 PCI Bus Number Register

The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which the controller is connected. The controller uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses.

PCI register offset: 18h (Function 0) Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

September 2005SCPS110

PC Card Controller Programming Model

4.16 CardBus Bus Number Register

The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus to which the controller is connected. The controller uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each controller function.

PCI register offset: 19h Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.17 Subordinate Bus Number Register

The subordinate bus number register is programmed by the host system to indicate the highest numbered bus below the CardBus bus. The controller uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses.

PCI register offset: 1Ah Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.18 CardBus Latency Timer Register

The CardBus latency timer register is programmed by the host system to specify the latency timer for the CardBus interface, in units of CCLK cycles. When the controller is a CardBus initiator and asserts CFRAME the CardBus latency timer begins counting. If the latency timer expires before the PCIxx12 transaction has terminated, then the controller terminates the transaction at the end of the next data phase. A recommended minimum value for this register of 20h allows most transactions to be completed.

PCI register offset: 1Bh (Function 0) Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

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PC Card Controller Programming Model

4.19 CardBus Memory Base Registers 0, 1

These registers indicate the lower address of a PCI memory address range. They are used by the controller to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 000h. W rites to these bits have no effect. Bits 8 and 9 of the bridge control register (PCI offset 3Eh, see Section

4.25) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero in order for the controller to claim any memory transactions through CardBus memory windows (i.e., these windows by default are not enabled to pass the first 4 Kbytes of memory to CardBus).

PCI register offset: 1Ch, 24h Register type: Read-only, Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4.20 CardBus Memory Limit Registers 0, 1

These registers indicate the upper address of a PCI memory address range. They are used by the controller to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31−12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11−0 are read-only and always return 000h. W rites to these bits have no effect. Bits 8 and 9 of the bridge control register (PCI offset 3Eh, see Section

PCI register offset: 20h, 28h Register type: Read-only, Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Texas Instruments PCI7412 (PC Card, FireWire, Memory Ctrl.) PCIxx12 Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual