DAC7800
DAC7801
DAC7802
SBAS005A – DECEMBER 2001
Dual Monolithic CMOS 12-Bit Multiplying
DIGITAL-TO-ANALOG CONVERTERS
FEATURES
●TWO DACs IN A 0.3" WIDE PACKAGE
●SINGLE +5V SUPPLY
●HIGH SPEED DIGITAL INTERFACE: Serial—DAC7800
8 + 4-Bit Parallel—DAC7801
12-Bit Parallel—DAC7802
●MONOTONIC OVER TEMPERATURE
●LOW CROSSTALK: –94dB min
●FULLY SPECIFIED OVER –40OC TO +85OC
DESCRIPTION
The DAC7800, DAC7801 and DAC7802 are members of a new family of monolithic dual 12-bit CMOS multiplying Digi- tal-to-Analog Converters (DACs). The digital interface speed and the AC multiplying performance are achieved by using an advanced CMOS process optimized for data conversion circuits. High stability on-chip resistors provide true 12-bit integral and differential linearity over the wide industrial temperature range of –40° C to +85° C.
DAC7800 features a serial interface capable of clocking-in data at a rate of at least 10MHz. Serial data is clocked (edge triggered) MSB first into a 24-bit shift register and then latched into each DAC separately or simultaneously as required by the application. An asynchronous CLEAR control is provided for power-on reset or system calibration functions. It is packaged in a 16-pin 0.3" wide plastic DIP.
DAC7801 has a 2-byte (8 + 4) double-buffered interface. Data is first loaded (level transferred) into the input registers in two steps for each DAC. Then both DACs are updated simultaneously. DAC7801 features an asynchronous CLEAR control. DAC7801 is packaged in a 24-pin 0.3" wide plastic DIP.
APPLICATIONS
●PROCESS CONTROL OUTPUTS
●ATE PIN ELECTRONICS LEVEL SETTING
●PROGRAMMABLE FILTERS
●PROGRAMMABLE GAIN CIRCUITS
●AUTO-CALIBRATION CIRCUITS
DAC7802 has a single-buffered 12-bit data word interface. Parallel data is loaded (edge triggered) into the single DAC register for each DAC. DAC7802 is packaged in a 24-pin 0.3" wide plastic DIP.
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DAC7802 |
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VREF A |
RFB A |
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12-Bit Interface |
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IOUT A |
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WR |
CSA |
CSB |
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12-Bit MDAC |
AGND A |
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DAC A |
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DAC7801 |
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VREF B |
RFB B |
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8-Bit Interface |
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8 Bits + 4 Bits |
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IOUT B |
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CS |
CLR WR UPD A0 |
A1 |
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12-Bit MDAC |
AGND B |
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DAC B |
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Serial DAC7800
Serial Interface
CLK |
UPD A |
UPD B |
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CLR |
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CS |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. |
Copyright © 1990, Texas Instruments Incorporated |
Products conform to specifications per the terms of Texas Instruments |
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standard warranty. Production processing does not necessarily include |
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testing of all parameters. |
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www.ti.com
ABSOLUTE MAXIMUM RATINGS
At TA = +25° C, unless otherwise noted.
..................................................................................VDD to AGND |
0V, +7V |
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VDD to DGND .................................................................................. |
0V, +7V |
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AGND to DGND .......................................................................... |
–0.3, VDD |
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Digital Input to DGND ........................................................ |
–0.3, VDD + 0.3 |
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VREF A, VREF B to AGND ..................................................................... |
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16V |
VREF A, VREF B to DGND ..................................................................... |
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16V |
IOUT A, IOUT B to AGND ................................................................. |
–0.3, VDD |
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Storage Temperature Range ........................................... |
–55° C to +125° C |
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Operating Temperature Range ......................................... |
–40° C to +85° C |
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Lead Temperature (soldering, 10s) ................................................. |
+300° C |
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Junction Temperature ...................................................................... |
+175° C |
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PACKAGE/ORDERING INFORMATION
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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SPECIFIED |
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RELATIVE |
GAIN |
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PACKAGE |
TEMPERATURE |
PACKAGE |
ORDERING |
TRANSPORT |
PRODUCT |
ACCURACY |
ERROR |
PACKAGE-LEAD |
DESIGNATOR(1) |
RANGE |
MARKING |
NUMBER |
MEDIA, QUANTITY |
DAC7800KP |
± 1LSB |
± 3LSB |
DIP-16 |
N |
–40° C to +85°C |
DAC7800KP |
DAC7800KP |
Rails, 25 |
DAC7800LP |
± 1/2 LSB |
± 1LSB |
DIP-16 |
N |
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DAC7800LP |
DAC7800LP |
Rails, 25 |
DAC7800KU |
— |
— |
SO-16 |
DW |
–40° C to +85°C |
DAC7800KU |
DAC7800KU/1K |
Tape and Reel, 1000 |
DAC7800LU |
— |
— |
SO-16 |
DW |
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DAC7800LU |
DAC7800LU/1K |
Tape and Reel, 1000 |
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DAC7801KP |
± 1LSB |
± 3LSB |
DIP-24 |
NT |
–40° C to +85°C |
DAC7801KP |
DAC7801KP |
Rails, 15 |
DAC7801LP |
± 1/2 LSB |
± 1LSB |
DIP-24 |
NT |
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DAC7801LP |
DAC7801LP |
Rails, 15 |
DAC7801KU |
— |
— |
SO-24 |
DW |
–40° C to +85°C |
DAC7801KU |
DAC7801KU/1K |
Tape and Reel, 1000 |
DAC7801LU |
— |
— |
SO-24 |
DW |
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DAC7801LU |
DAC7801LU/1K |
Tape and Reel, 1000 |
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DAC7802KP |
± 1LSB |
± 3LSB |
DIP-24 |
NTG |
–40° C to +85°C |
DAC7802KP |
DAC7802KP |
Rails, 15 |
DAC7802LP |
± 1/2 LSB |
± 1LSB |
DIP-24 |
NTG |
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DAC7802LP |
DAC7802LP |
Rails, 15 |
DAC7802KU |
— |
— |
SO-24 |
DW |
–40° C to +85°C |
DAC7802KU |
DAC7802KU/1K |
Tape and Reel, 1000 |
DAC7802LU |
— |
— |
SO-24 |
DW |
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DAC7802LU |
DAC7802LU/1K |
Tape and Reel, 1000 |
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NOTE: (1 ) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
At VDD = +5VDC, VREF A = VREF B = +10V, TA = –40° C to +85° C, unless otherwise noted.
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DAC7800, 7801, 7802K |
DAC7800, 7801, 7802L |
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PARAMETER |
CONDITIONS |
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TYP |
MAX |
MIN |
TYP |
MAX |
UNITS |
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ACCURACY |
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Resolution |
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Bits |
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Relative Accuracy |
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± 1 |
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± 1/2 |
LSB |
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Differential Nonlinearity |
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± 1 |
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LSB |
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Gain Error |
Measured Using RFB A and RFB B. |
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± 3 |
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± 1 |
LSB |
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All Registers Loaded with All 1s. |
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Gain Temperature Coefficient(1) |
TA = +25° C |
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2 |
5 |
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ppm/° C |
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Output Leakage Current |
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0.005 |
10 |
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nA |
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TA = –40° C to +85° C |
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3 |
150 |
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nA |
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REFERENCE INPUT |
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Input Resistance |
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10 |
14 |
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kΩ |
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Input Resistance Match |
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0.5 |
3 |
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2 |
% |
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DIGITAL INPUTS |
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VIH (Input HIGH Voltage) |
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2 |
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V |
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VIL (Input LOW Voltage) |
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0.8 |
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V |
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IIN |
(Input Current) |
TA = +25° C |
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± 1 |
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µ A |
CIN (Input Capacitance) |
TA = –40° C to +85° C |
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± 10 |
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µ A |
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0.8 |
10 |
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pF |
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POWER SUPPLY |
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VDD |
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4.5 |
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5.5 |
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IDD |
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0.2 |
2 |
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mA |
Power-Supply Rejection |
VDD from 4.5V to 5.5V |
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0.002 |
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%/% |
Same specification as for DAC7800, 7801, 7802K.
2 |
DAC7800, 7801, 7802 |
www.ti.com |
SBAS005A |
AC PERFORMANCE
OUTPUT OP AMP IS OPA602.
At VDD = +5VDC, VREF A = VREF B = +10V, TA = +25° C, unless otherwise noted. These specifications are fully characterized but not subject to test.
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DAC7800, 7801, 7802K |
DAC7800, 7801, 7802L |
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PARAMETER |
CONDITIONS |
MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
UNITS |
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OUTPUT CURRENT SETTLING TIME |
To 0.01% of Full-Scale |
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0.4 |
0.8 |
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µ s |
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RL = 100Ω , CL = 13pF |
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DIGITAL-TO-ANALOG GLITCH IMPULSE |
VREF A = VREF B = 0V |
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0.9 |
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nV-s |
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RL = 100Ω , CL = 13pF |
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AC FEEDTHROUGH |
fVREF = 10kHz |
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–75 |
–72 |
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dB |
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OUTPUT CAPACITANCE |
DAC Loaded with All 0s |
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30 |
50 |
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pF |
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DAC Loaded with All 1s |
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70 |
100 |
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pF |
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CHANNEL-TO-CHANNEL ISOLATION |
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VREF A to IOUT B |
fVREF A = 10kHz |
–90 |
–94 |
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dB |
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VREF B = 0V, |
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Both DACs Loaded with 1s |
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VREF B to IOUT A |
fVREF B = 10kHz |
–90 |
–101 |
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dB |
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VREF A = 0V, |
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Both DACs Loaded with 1s |
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DIGITAL CROSSTALK |
Full-Scale Transition |
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0.9 |
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nV-s |
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RL = 100Ω , CL = 13pF |
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Same specification as for DAC7800, 7801, and 7802K. NOTE: (1) Ensured but not tested.
DAC7800
BLOCK DIAGRAM |
PIN CONFIGURATION |
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VDD |
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Top View |
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DIP |
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12 |
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DAC7800 |
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12 |
10 |
UPD B |
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Register |
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DAC B Register |
15 |
I OUT B |
IOUT A |
2 |
15 |
IOUT B |
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DAC B |
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16 |
AGND B |
AGND A |
1 |
16 |
AGND B |
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Shift |
Bit 0 |
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14 |
RFB B |
RFB A |
3 |
14 |
RFB B |
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Bit 11 |
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13 |
V REF B |
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and |
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Bit 12 |
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4 |
VREF A |
VREF A |
4 |
13 |
VREF B |
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Logic |
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DAC7800 |
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Bit 23 |
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3 |
R FB A |
CLK |
5 |
12 |
VDD |
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Control |
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DAC A |
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UPD A |
6 |
11 |
CLR |
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2 |
I OUT A |
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12 |
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Data In |
7 |
10 |
UPD B |
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DAC A Register |
1 |
AGND A |
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12 |
6 |
UPD A |
CS |
8 |
9 |
DGND |
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5 |
8 |
7 |
11 |
9 |
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CLK CS |
Data |
CLR |
DGND |
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In |
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LOGIC TRUTH TABLE
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CLK |
UPD A |
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UPD B |
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CS |
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CLR |
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FUNCTION |
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X |
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X |
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X |
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X |
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0 |
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All register contents set to 0’s (asynchronous). |
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X |
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X |
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X |
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1 |
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X |
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No data transfer. |
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X |
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X |
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0 |
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1 |
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Input data is clocked into input register (location Bit 23) and previous data shifts. |
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X |
0 |
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1 |
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0 |
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1 |
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Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A. |
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X |
1 |
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0 |
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0 |
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1 |
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Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B. |
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X |
0 |
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0 |
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0 |
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1 |
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Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB) |
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are loaded into DAC B. |
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X = Don’t care. means falling edge triggered.
DAC7800, 7801, 7802 |
3 |
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SBAS005A |
www.ti.com |
DAC7800 (Cont.)
DATA INPUT FORMAT
DAC7800 Digital Interface Block Diagram
UPD B |
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UPD A |
DAC A Register |
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DAC B Register |
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LSB |
MSB |
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LSB |
MSB |
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CLK |
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Bit |
Bit |
24-Bit |
Bit |
Bit |
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Data In |
23 |
12 |
11 |
0 |
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Shift Register |
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DAC7800 Data Input Sequence |
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CLK |
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Data In |
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Bit 0 Bit 1 Bit 2 Bit 3 |
Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 |
Bit 9 Bit 10 |
Bit 11 |
Bit 12 |
Bit 13 Bit 14 |
Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 |
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MSB |
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LSB |
MSB |
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LSB |
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DAC B |
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DAC B |
DAC A |
DAC A |
TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40° C to +85° C.
PARAMETER |
MINIMUM |
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t1 — Data Setup Time |
15ns |
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t2 — Data Hold Time |
15ns |
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t3 — Chip Select to CLK, |
15ns |
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Update, Data Setup Time |
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t4 — Chip Select to CLK, |
40ns |
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Update, Data Hold Time |
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t5 |
— CLK Pulse Width |
40ns |
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t6 |
— Clear Pulse Width |
40ns |
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t7 |
— Update Pulse Width |
40ns |
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t8 |
— CLK Edge to |
UPD A |
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15ns |
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or |
UPD B |
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t5 |
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CLK |
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0V |
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t1 |
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5V |
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DATA |
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0V |
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t3 |
t2 |
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5V |
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CS |
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t8 |
t7 t4 |
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UPD A |
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5V |
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UPD B |
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t6 |
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CLR |
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5V |
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NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. tR = tF = 5ns. |
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(2) Timing measurement reference level is VIH + VIL . |
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2 |
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4 |
DAC7800, 7801, 7802 |
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SBAS005A |
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www.ti.com |
DAC7801
BLOCK DIAGRAM |
PIN CONFIGURATION |
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VDD |
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Top View |
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DIP |
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20 |
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DAC7801 |
DAC A |
DAC A |
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MS |
LS |
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Input |
Input |
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AGND A |
1 |
24 |
AGND B |
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Reg |
Reg |
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IOUT A |
2 |
23 |
IOUT B |
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4 |
8 |
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DAC A Register |
2 |
IOUT A |
RFB A |
3 |
22 |
RFB B |
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UPD |
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12 |
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1 |
AGND A |
VREF A |
4 |
21 |
VREF B |
19 |
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DAC A |
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A1 |
16 |
Logic |
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3 |
RFB A |
CS |
5 |
20 |
VDD |
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A0 |
15 |
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4 |
VREF A |
DB0 |
6 |
19 |
UPD |
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Control |
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DAC7801 |
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CS |
5 |
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21 |
VREF B |
DB1 |
7 |
18 |
WR |
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WR |
18 |
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22 |
RFB B |
DB2 |
8 |
17 |
CLR |
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CLR |
17 |
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DAC B |
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23 |
IOUT B |
DB3 |
9 |
16 |
A1 |
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12 |
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24 |
AGND B |
DB4 |
10 |
15 |
A0 |
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DAC B Register |
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4 |
8 |
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DB5 |
11 |
14 |
DB7 |
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DAC B |
DAC B |
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DGND |
12 |
13 |
DB6 |
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MS |
LS |
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Input |
Input |
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Reg |
Reg |
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14 |
6 |
12 |
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DB7–DB0 |
DGND |
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LOGIC TRUTH TABLE
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CLR |
UPD |
CS |
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WR |
A1 |
A0 |
FUNCTION |
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1 |
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1 |
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1 |
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X |
X |
X |
No Data Transfer |
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1 |
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1 |
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X |
1 |
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X |
X |
No Data Transfer |
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0 |
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X |
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X |
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X |
X |
X |
All Registers Cleared |
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1 |
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1 |
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0 |
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0 |
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0 |
0 |
DAC A LS Input Register Loaded with DB7 - DB0 (LSB) |
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1 |
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1 |
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0 |
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0 |
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0 |
1 |
DAC A MS Input Register Loaded with DB3 (MSB) - DB0 |
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1 |
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1 |
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0 |
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0 |
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1 |
0 |
DAC B LS Input Register Loaded with DB7 - DB0 (LSB) |
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1 |
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1 |
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0 |
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0 |
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1 |
1 |
DAC B MS Input Register Loaded with DB3 (MSB) - DB0 |
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1 |
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0 |
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1 |
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0 |
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X |
X |
DAC A, DAC B Registers Updated Simultaneously from Input Registers |
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1 |
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0 |
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0 |
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0 |
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X |
X |
DAC A, DAC B Registers are Transparent |
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X = Don’t care.
TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40° C to +85° C.
PARAMETER |
MINIMUM |
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t1 — Address Valid to Write Setup Time |
10ns |
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t2 — Address Valid to Write Hold Time |
10ns |
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t3 — Data Setup Time |
30ns |
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t4 — Data Hold Time |
10ns |
|
t5 |
— Chip Select or Update to Write Setup Time |
0ns |
t6 |
— Chip Select or Update to Write Hold Time |
0ns |
t7 |
— Write Pulse Width |
40ns |
t8 |
— Clear Pulse Width |
40ns |
t1 |
t2 |
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A0–A1 |
5V |
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0V |
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t3 |
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t4 |
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DATA |
5V |
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0V |
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t5 |
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t6 |
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CS, UPD |
5V |
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0V |
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t7 |
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5V |
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WR |
||
0V |
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t8 |
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CLR |
5V |
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0V |
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NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t R = t F = 5ns. (2) Timing measurement reference level is VIH + VIL .
2
DAC7800, 7801, 7802 |
5 |
|
SBAS005A |
www.ti.com |
DAC7802
BLOCK DIAGRAM |
PIN CONFIGURATION |
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VDD |
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Top View |
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DIP |
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21 |
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12 |
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AGND |
1 |
24 |
IOUT B |
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DAC7802 |
|
CK |
DAC A Register |
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IOUT A |
2 |
23 |
RFB B |
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12 |
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RFB A |
3 |
22 |
V REF B |
CS A |
5 |
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DAC A |
2 |
IOUT A |
VREF A |
4 |
21 |
V DD |
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3 |
RFB A |
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CS A |
5 |
20 |
CS B |
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4 |
VREF A |
(LSB) DB0 |
6 |
19 |
WR |
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22 |
VREF B |
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DAC7802 |
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DB1 |
7 |
18 |
DB11 (MSB) |
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23 |
RFB B |
DB2 |
8 |
17 |
DB10 |
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CS B |
20 |
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DAC B |
24 |
IOUT B |
DB3 |
9 |
16 |
DB9 |
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12 |
1 |
AGND |
DB4 |
10 |
15 |
DB8 |
WR |
19 |
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CK |
DAC B Register |
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11 |
14 |
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12 |
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DB5 |
DB7 |
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DGND |
12 |
13 |
DB6 |
|
12 |
18 |
6 |
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DGND |
DB11–DB0 |
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TIMING CHARACTERISTICS
At VDD = +5V, and TA = –40oC to +85oC.
|
PARAMETER |
MINIMUM |
|
|
|
t1 - Data Setup Time |
20ns |
|
t2 |
- Data Hold Time |
15ns |
t3 |
- Chip Select to Write Setup Time |
30ns |
t4 |
- Chip Select to Write Hold Time |
0ns |
t5 |
- Write Pulse Width |
30ns |
t1 |
|
t2 |
5V |
DATA |
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|
0V |
|
t3 |
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t4 |
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|
5V |
||
CSA, CSB |
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t5 |
|
5V |
WR |
|
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|
|
|
|
NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. tR = tR = 5ns. (2) Timing measurement reference level VIH + VIL
is |
2 |
. |
|
|
LOGIC TRUTH TABLE
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CSA |
CSB |
|
WR |
FUNCTION |
|||||||||
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|
X |
|
X |
1 |
|
No Data Transfer |
|||||||
1 |
|
1 |
|
|
X |
No Data Transfer |
|||||||
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|||
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0 |
|
A Rising Edge on |
CSA |
or |
CSB |
Loads |
|
|
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|
|
|
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|
|
|
Data to the Respective DAC |
||||
0 |
|
1 |
|
|
|
|
DAC A Register Loaded from Data Bus |
||||||
1 |
|
0 |
|
|
|
|
DAC B Register Loaded from Data Bus |
||||||
0 |
|
0 |
|
|
|
|
DAC A and DAC B Registers Loaded |
||||||
|
|
|
|
|
|
|
|
|
from Data Bus |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
X = Don’t care. means rising edge triggered.
6 |
DAC7800, 7801, 7802 |
www.ti.com |
SBAS005A |