Texas Instruments DAC7802LU-1K, DAC7802LP, DAC7802KU-1K, DAC7802KP, DAC7800KP Datasheet

...
0 (0)

DAC7800

DAC7801

DAC7802

SBAS005A – DECEMBER 2001

Dual Monolithic CMOS 12-Bit Multiplying

DIGITAL-TO-ANALOG CONVERTERS

FEATURES

TWO DACs IN A 0.3" WIDE PACKAGE

SINGLE +5V SUPPLY

HIGH SPEED DIGITAL INTERFACE: Serial—DAC7800

8 + 4-Bit Parallel—DAC7801

12-Bit Parallel—DAC7802

MONOTONIC OVER TEMPERATURE

LOW CROSSTALK: –94dB min

FULLY SPECIFIED OVER –40OC TO +85OC

DESCRIPTION

The DAC7800, DAC7801 and DAC7802 are members of a new family of monolithic dual 12-bit CMOS multiplying Digi- tal-to-Analog Converters (DACs). The digital interface speed and the AC multiplying performance are achieved by using an advanced CMOS process optimized for data conversion circuits. High stability on-chip resistors provide true 12-bit integral and differential linearity over the wide industrial temperature range of –40° C to +85° C.

DAC7800 features a serial interface capable of clocking-in data at a rate of at least 10MHz. Serial data is clocked (edge triggered) MSB first into a 24-bit shift register and then latched into each DAC separately or simultaneously as required by the application. An asynchronous CLEAR control is provided for power-on reset or system calibration functions. It is packaged in a 16-pin 0.3" wide plastic DIP.

DAC7801 has a 2-byte (8 + 4) double-buffered interface. Data is first loaded (level transferred) into the input registers in two steps for each DAC. Then both DACs are updated simultaneously. DAC7801 features an asynchronous CLEAR control. DAC7801 is packaged in a 24-pin 0.3" wide plastic DIP.

APPLICATIONS

PROCESS CONTROL OUTPUTS

ATE PIN ELECTRONICS LEVEL SETTING

PROGRAMMABLE FILTERS

PROGRAMMABLE GAIN CIRCUITS

AUTO-CALIBRATION CIRCUITS

DAC7802 has a single-buffered 12-bit data word interface. Parallel data is loaded (edge triggered) into the single DAC register for each DAC. DAC7802 is packaged in a 24-pin 0.3" wide plastic DIP.

12

 

DAC7802

 

 

VREF A

RFB A

 

12-Bit Interface

 

 

 

 

 

 

 

 

 

IOUT A

 

WR

CSA

CSB

12

12-Bit MDAC

AGND A

 

DAC A

 

 

 

 

 

 

DAC7801

 

 

VREF B

RFB B

8

8-Bit Interface

 

 

 

8 Bits + 4 Bits

 

 

 

IOUT B

 

 

 

 

 

CS

CLR WR UPD A0

A1

12

12-Bit MDAC

AGND B

DAC B

 

 

 

 

 

 

 

 

Serial DAC7800

Serial Interface

CLK

UPD A

UPD B

 

CLR

 

CS

 

 

 

 

 

 

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 1990, Texas Instruments Incorporated

Products conform to specifications per the terms of Texas Instruments

 

standard warranty. Production processing does not necessarily include

 

testing of all parameters.

 

www.ti.com

ABSOLUTE MAXIMUM RATINGS

At TA = +25° C, unless otherwise noted.

..................................................................................VDD to AGND

0V, +7V

VDD to DGND ..................................................................................

0V, +7V

AGND to DGND ..........................................................................

–0.3, VDD

Digital Input to DGND ........................................................

–0.3, VDD + 0.3

VREF A, VREF B to AGND .....................................................................

±

16V

VREF A, VREF B to DGND .....................................................................

±

16V

IOUT A, IOUT B to AGND .................................................................

–0.3, VDD

Storage Temperature Range ...........................................

–55° C to +125° C

Operating Temperature Range .........................................

–40° C to +85° C

Lead Temperature (soldering, 10s) .................................................

+300° C

Junction Temperature ......................................................................

+175° C

 

 

 

PACKAGE/ORDERING INFORMATION

ELECTROSTATIC DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

 

 

 

 

 

SPECIFIED

 

 

 

 

RELATIVE

GAIN

 

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

ACCURACY

ERROR

PACKAGE-LEAD

DESIGNATOR(1)

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

DAC7800KP

± 1LSB

± 3LSB

DIP-16

N

–40° C to +85°C

DAC7800KP

DAC7800KP

Rails, 25

DAC7800LP

± 1/2 LSB

± 1LSB

DIP-16

N

 

DAC7800LP

DAC7800LP

Rails, 25

DAC7800KU

SO-16

DW

–40° C to +85°C

DAC7800KU

DAC7800KU/1K

Tape and Reel, 1000

DAC7800LU

SO-16

DW

 

DAC7800LU

DAC7800LU/1K

Tape and Reel, 1000

 

 

 

 

 

 

 

 

 

DAC7801KP

± 1LSB

± 3LSB

DIP-24

NT

–40° C to +85°C

DAC7801KP

DAC7801KP

Rails, 15

DAC7801LP

± 1/2 LSB

± 1LSB

DIP-24

NT

 

DAC7801LP

DAC7801LP

Rails, 15

DAC7801KU

SO-24

DW

–40° C to +85°C

DAC7801KU

DAC7801KU/1K

Tape and Reel, 1000

DAC7801LU

SO-24

DW

 

DAC7801LU

DAC7801LU/1K

Tape and Reel, 1000

 

 

 

 

 

 

 

 

 

DAC7802KP

± 1LSB

± 3LSB

DIP-24

NTG

–40° C to +85°C

DAC7802KP

DAC7802KP

Rails, 15

DAC7802LP

± 1/2 LSB

± 1LSB

DIP-24

NTG

 

DAC7802LP

DAC7802LP

Rails, 15

DAC7802KU

SO-24

DW

–40° C to +85°C

DAC7802KU

DAC7802KU/1K

Tape and Reel, 1000

DAC7802LU

SO-24

DW

 

DAC7802LU

DAC7802LU/1K

Tape and Reel, 1000

 

 

 

 

 

 

 

 

 

NOTE: (1 ) For the most current specifications and package information, refer to our web site at www.ti.com.

ELECTRICAL CHARACTERISTICS

At VDD = +5VDC, VREF A = VREF B = +10V, TA = –40° C to +85° C, unless otherwise noted.

 

 

 

DAC7800, 7801, 7802K

DAC7800, 7801, 7802L

 

 

 

 

 

 

 

 

 

 

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

 

 

ACCURACY

 

 

 

 

 

 

 

 

Resolution

 

12

 

 

 

 

 

Bits

Relative Accuracy

 

 

 

± 1

 

 

± 1/2

LSB

Differential Nonlinearity

 

 

 

± 1

 

 

 

LSB

Gain Error

Measured Using RFB A and RFB B.

 

 

± 3

 

 

± 1

LSB

 

 

All Registers Loaded with All 1s.

 

 

 

 

 

 

 

Gain Temperature Coefficient(1)

TA = +25° C

 

2

5

 

 

 

ppm/° C

Output Leakage Current

 

0.005

10

 

 

 

nA

 

 

TA = –40° C to +85° C

 

3

150

 

 

 

nA

 

 

 

 

 

 

 

 

 

REFERENCE INPUT

 

 

 

 

 

 

 

 

Input Resistance

 

6

10

14

 

 

 

kΩ

Input Resistance Match

 

 

0.5

3

 

 

2

%

 

 

 

 

 

 

 

 

 

DIGITAL INPUTS

 

 

 

 

 

 

 

 

VIH (Input HIGH Voltage)

 

2

 

 

 

 

 

V

VIL (Input LOW Voltage)

 

 

 

0.8

 

 

 

V

IIN

(Input Current)

TA = +25° C

 

 

± 1

 

 

 

µ A

CIN (Input Capacitance)

TA = –40° C to +85° C

 

 

± 10

 

 

 

µ A

 

 

0.8

10

 

 

 

pF

 

 

 

 

 

 

 

 

 

POWER SUPPLY

 

 

 

 

 

 

 

 

VDD

 

 

4.5

 

5.5

 

 

 

V

IDD

 

 

 

0.2

2

 

 

 

mA

Power-Supply Rejection

VDD from 4.5V to 5.5V

 

 

0.002

 

 

 

%/%

Same specification as for DAC7800, 7801, 7802K.

2

DAC7800, 7801, 7802

www.ti.com

SBAS005A

AC PERFORMANCE

OUTPUT OP AMP IS OPA602.

At VDD = +5VDC, VREF A = VREF B = +10V, TA = +25° C, unless otherwise noted. These specifications are fully characterized but not subject to test.

 

 

DAC7800, 7801, 7802K

DAC7800, 7801, 7802L

 

 

 

 

 

 

 

 

 

 

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

 

 

 

 

 

 

 

 

 

OUTPUT CURRENT SETTLING TIME

To 0.01% of Full-Scale

 

0.4

0.8

 

 

 

µ s

 

RL = 100Ω , CL = 13pF

 

 

 

 

 

 

 

DIGITAL-TO-ANALOG GLITCH IMPULSE

VREF A = VREF B = 0V

 

0.9

 

 

 

 

nV-s

 

RL = 100Ω , CL = 13pF

 

 

 

 

 

 

 

AC FEEDTHROUGH

fVREF = 10kHz

 

–75

–72

 

 

 

dB

 

 

 

 

 

 

 

 

 

OUTPUT CAPACITANCE

DAC Loaded with All 0s

 

30

50

 

 

 

pF

 

DAC Loaded with All 1s

 

70

100

 

 

 

pF

 

 

 

 

 

 

 

 

 

CHANNEL-TO-CHANNEL ISOLATION

 

 

 

 

 

 

 

 

VREF A to IOUT B

fVREF A = 10kHz

–90

–94

 

 

 

 

dB

 

VREF B = 0V,

 

 

 

 

 

 

 

 

Both DACs Loaded with 1s

 

 

 

 

 

 

 

VREF B to IOUT A

fVREF B = 10kHz

–90

–101

 

 

 

 

dB

 

VREF A = 0V,

 

 

 

 

 

 

 

 

Both DACs Loaded with 1s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIGITAL CROSSTALK

Full-Scale Transition

 

0.9

 

 

 

 

nV-s

 

RL = 100Ω , CL = 13pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Same specification as for DAC7800, 7801, and 7802K. NOTE: (1) Ensured but not tested.

DAC7800

BLOCK DIAGRAM

PIN CONFIGURATION

 

VDD

 

 

 

 

 

Top View

 

 

DIP

 

12

 

 

 

 

 

 

 

 

 

DAC7800

 

 

12

10

UPD B

 

 

 

 

 

 

 

 

 

 

 

 

Register

 

 

 

DAC B Register

15

I OUT B

IOUT A

2

15

IOUT B

 

 

 

DAC B

 

 

 

 

 

 

12

16

AGND B

AGND A

1

16

AGND B

 

 

 

 

 

 

 

 

 

Shift

Bit 0

 

 

14

RFB B

RFB A

3

14

RFB B

Bit 11

 

 

13

V REF B

and

 

 

 

 

 

 

Bit 12

 

 

4

VREF A

VREF A

4

13

VREF B

Logic

 

 

 

 

DAC7800

 

Bit 23

 

 

3

R FB A

CLK

5

12

VDD

Control

 

 

 

DAC A

 

 

 

 

 

 

 

 

 

UPD A

6

11

CLR

 

 

 

 

 

 

 

 

 

 

 

2

I OUT A

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

Data In

7

10

UPD B

 

 

 

 

DAC A Register

1

AGND A

 

 

 

 

 

 

 

 

 

 

 

 

12

6

UPD A

CS

8

9

DGND

 

 

 

 

 

 

 

 

 

5

8

7

11

9

 

 

 

 

 

 

CLK CS

Data

CLR

DGND

 

 

 

 

 

 

 

 

In

 

 

 

 

 

 

 

 

LOGIC TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

UPD A

 

UPD B

 

CS

 

CLR

 

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

X

 

 

X

 

X

 

0

 

All register contents set to 0’s (asynchronous).

X

 

X

 

 

X

 

1

 

 

X

 

No data transfer.

 

 

X

 

 

X

 

0

 

 

1

 

Input data is clocked into input register (location Bit 23) and previous data shifts.

X

0

 

1

 

 

0

 

 

1

 

Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A.

X

1

 

0

 

 

0

 

 

1

 

Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B.

X

0

 

0

 

 

0

 

 

1

 

Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB)

 

 

 

 

 

 

 

 

 

 

 

 

 

are loaded into DAC B.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X = Don’t care. means falling edge triggered.

DAC7800, 7801, 7802

3

 

SBAS005A

www.ti.com

DAC7800 (Cont.)

DATA INPUT FORMAT

DAC7800 Digital Interface Block Diagram

UPD B

 

 

 

 

 

 

UPD A

DAC A Register

 

 

 

 

DAC B Register

 

 

 

 

 

 

LSB

MSB

 

 

LSB

MSB

CLK

 

 

 

 

 

 

 

Bit

Bit

24-Bit

Bit

Bit

Data In

23

12

11

0

Shift Register

 

 

DAC7800 Data Input Sequence

 

CLK

 

 

 

 

 

 

Data In

 

 

 

 

 

 

Bit 0 Bit 1 Bit 2 Bit 3

Bit 4 Bit 5 Bit 6 Bit 7 Bit 8

Bit 9 Bit 10

Bit 11

Bit 12

Bit 13 Bit 14

Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23

MSB

 

 

LSB

MSB

 

LSB

DAC B

 

DAC B

DAC A

DAC A

TIMING CHARACTERISTICS

VDD = +5V, VREF A = VREF B = +10V, TA = –40° C to +85° C.

PARAMETER

MINIMUM

 

 

 

 

 

 

t1 — Data Setup Time

15ns

t2 — Data Hold Time

15ns

t3 — Chip Select to CLK,

15ns

 

Update, Data Setup Time

 

t4 — Chip Select to CLK,

40ns

 

Update, Data Hold Time

 

t5

— CLK Pulse Width

40ns

t6

— Clear Pulse Width

40ns

t7

— Update Pulse Width

40ns

t8

— CLK Edge to

UPD A

 

15ns

 

or

UPD B

 

 

 

 

 

 

 

 

 

 

 

 

t5

 

CLK

 

0V

 

t1

 

5V

DATA

 

 

0V

t3

t2

5V

CS

 

 

 

 

t8

t7 t4

UPD A

 

5V

UPD B

 

t6

CLR

 

5V

 

 

NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. tR = tF = 5ns.

(2) Timing measurement reference level is VIH + VIL .

 

 

2

 

4

DAC7800, 7801, 7802

SBAS005A

www.ti.com

Texas Instruments DAC7802LU-1K, DAC7802LP, DAC7802KU-1K, DAC7802KP, DAC7800KP Datasheet

DAC7801

BLOCK DIAGRAM

PIN CONFIGURATION

 

 

VDD

 

 

 

 

Top View

 

 

DIP

 

 

20

 

 

 

 

 

 

 

 

 

 

DAC7801

DAC A

DAC A

 

 

 

 

 

 

 

 

 

MS

LS

 

 

 

 

 

 

 

 

 

Input

Input

 

 

AGND A

1

24

AGND B

 

 

 

Reg

Reg

 

 

IOUT A

2

23

IOUT B

 

 

 

4

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DAC A Register

2

IOUT A

RFB A

3

22

RFB B

 

 

 

 

 

UPD

 

 

12

 

1

AGND A

VREF A

4

21

VREF B

19

 

DAC A

 

 

 

 

 

 

 

 

 

 

 

A1

16

Logic

 

 

3

RFB A

CS

5

20

VDD

 

 

 

 

 

 

A0

15

 

 

4

VREF A

DB0

6

19

UPD

 

 

Control

 

 

 

 

 

 

DAC7801

 

CS

5

 

 

21

VREF B

DB1

7

18

WR

 

 

 

 

 

 

 

 

 

 

WR

18

 

 

 

22

RFB B

DB2

8

17

CLR

 

 

 

 

 

 

 

CLR

17

 

DAC B

 

23

IOUT B

DB3

9

16

A1

 

12

 

 

 

 

 

 

 

 

 

24

AGND B

DB4

10

15

A0

 

 

 

DAC B Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

8

 

 

DB5

11

14

DB7

 

 

 

DAC B

DAC B

 

 

DGND

12

13

DB6

 

 

 

MS

LS

 

 

 

 

 

 

 

 

 

Input

Input

 

 

 

 

 

 

 

 

 

Reg

Reg

 

 

 

 

 

 

 

 

14

6

12

 

 

 

 

 

 

 

 

DB7–DB0

DGND

 

 

 

 

 

 

LOGIC TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLR

UPD

CS

 

WR

A1

A0

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

1

 

 

X

X

X

No Data Transfer

1

 

1

 

 

X

1

 

X

X

No Data Transfer

0

 

 

X

 

X

 

X

X

X

All Registers Cleared

1

 

1

 

0

 

0

 

0

0

DAC A LS Input Register Loaded with DB7 - DB0 (LSB)

1

 

1

 

0

 

0

 

0

1

DAC A MS Input Register Loaded with DB3 (MSB) - DB0

1

 

1

 

0

 

0

 

1

0

DAC B LS Input Register Loaded with DB7 - DB0 (LSB)

1

 

1

 

0

 

0

 

1

1

DAC B MS Input Register Loaded with DB3 (MSB) - DB0

1

 

0

 

1

 

0

 

X

X

DAC A, DAC B Registers Updated Simultaneously from Input Registers

1

 

0

 

0

 

0

 

X

X

DAC A, DAC B Registers are Transparent

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X = Don’t care.

TIMING CHARACTERISTICS

VDD = +5V, VREF A = VREF B = +10V, TA = –40° C to +85° C.

PARAMETER

MINIMUM

 

 

t1 — Address Valid to Write Setup Time

10ns

t2 — Address Valid to Write Hold Time

10ns

t3 — Data Setup Time

30ns

t4 — Data Hold Time

10ns

t5

— Chip Select or Update to Write Setup Time

0ns

t6

— Chip Select or Update to Write Hold Time

0ns

t7

— Write Pulse Width

40ns

t8

— Clear Pulse Width

40ns

t1

t2

A0–A1

5V

0V

t3

t4

DATA

5V

0V

t5

t6

CS, UPD

5V

0V

t7

5V

WR

0V

 

t8

CLR

5V

0V

 

NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t R = t F = 5ns. (2) Timing measurement reference level is VIH + VIL .

2

DAC7800, 7801, 7802

5

 

SBAS005A

www.ti.com

DAC7802

BLOCK DIAGRAM

PIN CONFIGURATION

 

VDD

 

 

 

 

 

Top View

 

 

DIP

 

 

 

 

 

 

 

 

 

 

 

21

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

AGND

1

24

IOUT B

 

 

 

 

 

 

 

 

 

 

 

DAC7802

 

CK

DAC A Register

 

 

IOUT A

2

23

RFB B

 

 

 

 

12

 

 

RFB A

3

22

V REF B

CS A

5

 

 

DAC A

2

IOUT A

VREF A

4

21

V DD

 

 

3

RFB A

 

 

 

 

 

CS A

5

20

CS B

 

 

 

 

 

 

 

 

 

 

 

 

4

VREF A

(LSB) DB0

6

19

WR

 

 

 

 

 

22

VREF B

 

 

DAC7802

 

 

 

 

 

 

DB1

7

18

DB11 (MSB)

 

 

 

 

 

 

 

 

 

 

 

 

23

RFB B

DB2

8

17

DB10

 

 

 

 

 

 

 

CS B

20

 

 

DAC B

24

IOUT B

DB3

9

16

DB9

 

 

 

 

 

 

 

 

 

12

1

AGND

DB4

10

15

DB8

WR

19

 

CK

DAC B Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

14

 

 

 

 

 

12

 

 

DB5

DB7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DGND

12

13

DB6

 

12

18

6

 

 

 

 

 

 

 

 

DGND

DB11–DB0

 

 

 

 

 

 

 

TIMING CHARACTERISTICS

At VDD = +5V, and TA = –40oC to +85oC.

 

PARAMETER

MINIMUM

 

 

t1 - Data Setup Time

20ns

t2

- Data Hold Time

15ns

t3

- Chip Select to Write Setup Time

30ns

t4

- Chip Select to Write Hold Time

0ns

t5

- Write Pulse Width

30ns

t1

 

t2

5V

DATA

 

 

 

 

0V

t3

 

t4

 

5V

CSA, CSB

 

 

 

 

 

 

t5

 

5V

WR

 

 

 

 

 

NOTES: (1) All input signal rise and fall times are measured from 10%

to 90% of +5V. tR = tR = 5ns. (2) Timing measurement reference level VIH + VIL

is

2

.

 

 

LOGIC TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CSA

CSB

 

WR

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

X

1

 

No Data Transfer

1

 

1

 

 

X

No Data Transfer

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

A Rising Edge on

CSA

or

CSB

Loads

 

 

 

 

 

 

 

 

 

Data to the Respective DAC

0

 

1

 

 

 

 

DAC A Register Loaded from Data Bus

1

 

0

 

 

 

 

DAC B Register Loaded from Data Bus

0

 

0

 

 

 

 

DAC A and DAC B Registers Loaded

 

 

 

 

 

 

 

 

 

from Data Bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X = Don’t care. means rising edge triggered.

6

DAC7800, 7801, 7802

www.ti.com

SBAS005A

Loading...
+ 11 hidden pages