TEXAS INSTRUMENTS TPS77101, 115, 118, 127, 128 Technical data

TPS77101DGKG4		TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT
		TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT
		150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
		SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

DOpen Drain Power-On Reset With 220-ms Delay (TPS771xx)

DOpen Drain Power-Good (PG) Status Output (TPS772xx)

D150-mA Low-Dropout Voltage Regulator

DAvailable in 1.5-V, 1.8-V, 2.7-V, 2.8-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions

DDropout Voltage Typically 115 mV at 150 mA (TPS77133, TPS77233)

DUltralow 92- A Quiescent Current (Typ)

D8-Pin MSOP (DGK) Package

DLow Noise (55 Vrms) Without External

Filter (Bypass) Capacitor (TPS77118, TPS77218)

D2% Tolerance Over Specified Conditions for Fixed-Output Versions

DFast Transient Response

DThermal Shutdown Protection

description

The TPS771xx and TPS772xx are low-dropout regulators with integrated power-on reset and power good (PG) function respectively. These devices are capable of supplying 150 mA of output current with a dropout of 115 mV (TPS77133, TPS77233). Quiescent current is 92 A at full load dropping down to 1 A when device is disabled. These devices are optimized to be stable with a wide range of output capacitors including low ESR ceramic (10 F) or low capacitance (1 F) tantalum capacitors. These devices have extremely low noise output performance (55 Vrms) without using any added filter capacitors. TPS771xx and TPS772xx are designed to have fast transient response for larger load current changes.

TPS771xx

DGK Package

(TOP VIEW)

FB/SENSE										1			8						OUT
	RESET									2			7						OUT
		EN								3			6						IN
	GND									4			5						IN
													TPS772xx
												DGK Package
												(TOP VIEW)
FB/SENSE																			OUT
											1		8
		PG									2		7						OUT
			EN								3		6						IN
	GND										4		5						IN

TPS77x33

DROPOUT VOLTAGE vs

JUNCTION TEMPERATURE

	300
	250
mV	200
–
				IO = 150 mA
Voltage
	150
Dropout	100
				IO = 10 mA
–	50
DO					IO = 0 A
V
	0
	–50
	–40	0	40	80	120	160
		TJ – Junction Temperature – ° C

The TPS771xx or TPS772xx is offered in 1.5 V,

1.8-V, 2.7-V, 2.8-V, 3.3-V, and 5.0 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The TPS771xx and TPS772xx families are available in 8-pin MSOP (DGK) packages.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 115 mV at an output current of 150 mA for 3.3 volt option) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 92 A over the full range of output current, 0 mA to 150 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

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1

TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

description (continued)

The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 A at TJ = 25° C.

The TPS771xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS) or reset output voltage. The RESET output of the TPS771xx initiates a reset in DSP, microcomputer or microprocessor systems at power up and in the event of an undervoltage condition. An internal comparator in the TPS771xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT reaches 95% of its regulated voltage, RESET will go to a high-impedance state after a 220 ms delay. RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition) of its regulated voltage.

For the TPS772xx, the power good terminal (PG) is an active high output, which can be used to implement a power-on reset or a low-battery indicator. An internal comparator in the TPS772xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82% of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT is above 82% of its regulated voltage.

AVAILABLE OPTIONS

		OUTPUT VOLTAGE		PACKAGED DEVICES
	TJ	(V)		MSOP (DGK)
		TYP		TPS771xx		TPS772xx
				SYMBOL		SYMBOL
		5.0	TPS77150DGK	AFV	TPS77250DGK	AGE
		3.3	TPS77133DGK	AFU	TPS77233DGK	AGD
		2.8	TPS77128DGK	AFS	TPS77228DGK	AGB
	–40° C to 125° C	2.7	TPS77127DGK	AFR	TPS77227DGK	AGA
		1.8	TPS77118DGK	AFP	TPS77218DGK	AFY
		1.5	TPS77115DGK	AFO	TPS77215DGK	AFX
		Adjustable	TPS77101DGK	AFN	TPS77201DGK	AFW
		1.5 V to 5.5 V

NOTE: The TPS77101 and TPS77201 are programmable using an external resistor divider (see application information). The DGK package is available taped and reeled. Add an R suffix to the device type (e.g., TPS77101DGKR).

VI		5		7
		IN	OUT
		6	OUT	8
		IN
			SENSE	1
0.1	F	3	PG or	2
		EN
			RESET
				+
			GND	10
		4

VO

PG or RESET

F

Figure 1. Typical Application Configuration (For Fixed Output Options)

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	TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT
	TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT
	150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING
	SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000
functional block diagrams
adjustable version
IN
EN
	PG or RESET
_
+	OUT

	+	220 ms Delay	R1
	_	(for TPS771xx Option)
	Vref = 1.1834 V		FB/SENSE

	R2
GND	External to the Device

fixed-voltage version

	IN
	EN
			PG or RESET
	_
	+		OUT
	+	220 ms Delay	SENSE
			R1
	_	(for TPS771xx Option)
	Vref = 1.1834 V

R2

GND

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TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

						Terminal Functions
		TERMINAL			I/O	DESCRIPTION
		NAME		NO.
	TPS771XX
	FB/SENSE			1	I	Feedback input voltage for adjustable device (sense input for fixed options)
				2	O	Reset output
	RESET
				3	I	Enable input
	EN
	GND			4		Regulator ground
	IN			5, 6	I	Input voltage
	OUT			7, 8	O	Regulated output voltage
	TPS772XX
	FB/SENSE			1	I	Feedback input voltage for adjustable device (sense input for fixed options)
	PG			2	O	Power good
				3	I	Enable input
	EN
	GND			4		Regulator ground
	IN			5, 6	I	Input voltage
	OUT			7, 8	O	Regulated output voltage

TPS771xx RESET timing diagram

VI
Vres†				Vres†
				t
VO	V	‡	V	‡
		IT +		IT +
Threshold
Voltage
		VIT –‡		VIT –‡
				t
RESET		220 ms		220 ms
Output
		Delay		Delay

Output	Output
Undefined	Undefined
	t

†Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology.

‡VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.

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TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

TPS772xx PG timing diagram

VI
Vres†				Vres†
				t
VO	V	‡	V	‡
		IT +		IT +
Threshold
Voltage
		VIT –‡		VIT –‡
				t
PG
Output

Output	Output
Undefined	Undefined
	t

†Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology.

‡VIT – Trip voltage is typically 18% lower than the output voltage (82%VO) VIT– to VIT+ is the hysteresis voltage.

absolute maximum ratings over operating junction temperature range (unless otherwise noted)

Input voltage range, VI, (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . –0.3 V to 13.5 V
Voltage range at		EN		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . –0.3 V to 16.5 V
Maximum	RESET		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .voltage (TPS771xx)		. . . . . . . . . . . . . . . . . . . 16.5 V
Maximum PG voltage (TPS772xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . 16.5 V
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					See Dissipation Rating Table
Output voltage, VO (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 5.5 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . –40° C to 125° C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . –65° C to 150° C
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . . 2 kV

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network terminal ground.

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TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

DISSIPATION RATING TABLE – FREE-AIR TEMPERATURES

	PACKAGE	AIR FLOW	θ JA	θ JC	TA < 25° C	DERATING FACTOR	TA = 70° C	TA = 85° C
		(CFM)	(° C/W)	(° C/W)	POWER RATING	ABOVE TA = 25° C	POWER RATING	POWER RATING
		0	266.2	3.84	376 mW	3.76 mW/° C	207 mW	150 mW
	DGK	150	255.2	3.92	392 mW	3.92 mW/° C	216 mW	157 mW
		250	242.8	4.21	412 mW	4.12 mW/° C	227 mW	165 mW

recommended operating conditions

	MIN	MAX	UNIT
Input voltage, VI†	2.7	10	V
Output voltage range, VO	1.5	5.5	V
Output current, IO (see Note 2)	0	150	mA
Operating virtual junction temperature, TJ (see Note 2)	–40	125	° C

† To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). NOTE 2: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the

device operate under conditions beyond those specified in this table for extended periods of time.

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TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT

150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

electrical characteristics over recommended operating junction temperature range (–40° C to 125° C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 F (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

Adjustable voltage

1.5 V ≤

VO ≤

5.5 V,

TJ = 25° C

VO

V

1.5 V ≤

VO ≤

5.5 V

0.98VO

1.02VO

1.5-V Output

TJ = 25° C,

2.7 V < VIN < 10 V

1.5

2.7 V < VIN < 10 V

1.470

1.530

1.8-V Output

TJ = 25° C,

2.8 V < VIN < 10 V

1.8

2.8 V < VIN < 10 V

1.764

1.836

Output voltage

2.7-V Output

TJ = 25° C,

3.7 V < VIN < 10 V

2.7

V

(see Notes 3 and 4)

3.7 V < VIN < 10 V

2.646

2.754

2.8-V Output

TJ = 25° C,

3.8 V < VIN < 10 V

2.8

3.8 V < VIN < 10 V

2.744

2.856

3.3-V Output

TJ = 25° C,

4.3 V < VIN < 10 V

3.3

4.3 V < VIN < 10 V

3.234

3.366

5.0-V Output

TJ = 25° C,

6 V < VIN < 10 V

5.0

V

6 V < VIN < 10 V

4.900

5.100

Quiescent current (GND current) (see Notes 3 and 4)

TJ = 25° C

92

A

125

Output voltage line regulation (∆ VO/VO) (see Note 5)

VO + 1 V < VI ≤

10 V,

TJ = 25° C

0.005

%/V

VO + 1 V < VI ≤

10 V

0.05

%/V

Load regulation

TJ = 25° C

1

mV

Output noise voltage

BW = 300 Hz to 100 kHz, TJ = 25° C,

55

Vrms

TPS77118, TPS77218

Output current Limit

VO = 0 V

0.9

1.3

A

Peak output current

2 ms pulse width,

50% duty cycle

400

mA

Thermal shutdown junction temperature

144

° C

= VI,

TJ = 25° C

1

A

Standby current

EN

A

EN = VI

3

FB input current

Adjustable voltage

FB = 1.5 V

1

A

High level enable input voltage

2

V

Low level enable input voltage

0.7

V

Enable input current

–1

1

A

Power supply ripple rejection (TPS77118, TPS77218)

f = 1 KHz,

TJ = 25° C

55

dB

NOTES: 3.	Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 10 V, minimum output
	current 1 mA.
4.	If VO < 1.8 V then VI(max) = 10 V, VI(min) = 2.7 V:
	Line regulation (mV) +	% V	VO VI(max) * 2.7 V	1000
		100

If VO > 2.5 V then VI(max) = 10 V, VI(min) = Vo + 1 V:

	Line regulation (mV) + % V	VO VI(max) * VO ) 1	1000
		100

5. IO = 1 mA to 150 mA

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TPS77101/115/118/127/128/133/150 WITH RESET OUTPUT TPS77201/215/218/227/228/233/250 WITH POWER GOOD OUTPUT 150-mA LDO REGULATORS WITH 8-PIN MSOP PACKAGING

SLVS225D – FEBRUARY 2000 – REVISED OCTOBER 2000

electrical characteristics	over recommended operating junction temperature range (–40° C to
125° C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 10 F (unless otherwise noted) (continued)

	PARAMETER				TEST CONDITIONS			MIN TYP	MAX	UNIT
	Minimum input voltage for valid PG				I(PG) = 300 A		V(PG) ≤ 0.8 V	1.1		V
PG	Trip threshold voltage				VO decreasing			79	85	%VO
	Hysteresis voltage				Measured at VO			0.5		%VO
(TPS772xx)
	Output low voltage				VI = 2.7 V,		I(PG) = 1mA	0.15	0.4	V
	Leakage current				V(PG) = 5 V				1	A
	Minimum input voltage for valid				I(RESET) = 300 A			1.1		V
		RESET
	Trip threshold voltage				VO decreasing			92	98	%VO
Reset	Hysteresis voltage				Measured at VO			0.5		%VO
(TPS771xx)	Output low voltage				VI = 2.7 V,		I(RESET) = 1 mA	0.15	0.4	V
	Leakage current				V(RESET) = 5 V				1	A
	RESET time-out delay							220		ms
			2.8-V Output		IO = 150 mA,		TJ = 25° C	150
					IO = 150 mA,				265
VDO	Dropout voltage (see Note 6)		3.3-V Output		IO = 150 mA,		TJ = 25° C	115		mV
					IO = 150 mA				200
			5.0-V Output		IO = 150 mA,		TJ = 25° C	75
					IO = 150 mA				115

NOTE 6: IN voltage equals VO(typ) – 100 mV; 1.5 V, 1.8 V, and 2.7 V dropout voltage limited by input voltage range limitations (i.e., 3.3 V input voltage needs to drop to 3.2 V for purpose of this test).

TYPICAL CHARACTERISTICS

Table of Graphs

				FIGURE
	VO	Output voltage	vs Output current	2,	3
			vs Junction temperature	4,	5
		Ground current	vs Junction temperature	6
		Power supply rejection ratio	vs Frequency	7
		Output spectral noise density	vs Frequency	8
	Zo	Output impedance	vs Frequency	9
	VDO	Dropout voltage	vs Input voltage	10
			vs Junction temperature	11
		Line transient response		12,	14
		Load transient response		13,	15
		Output voltage and enable pulse	vs Time	16
		Equivalent series resistance (ESR)	vs Output current	18 – 21

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