TMS320x28xx, 28xxx Enhanced Pulse Width
Modulator (ePWM) Module
Reference Guide
Literature Number: SPRU791D
November 2004–Revised October 2007
2 |
SPRU791D–November 2004–Revised October 2007 |
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Contents
Preface ............................................................................................................................... |
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1 |
Introduction |
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13 |
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1.1 |
Introduction......................................................................................................... |
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1.2 |
Submodule Overview ............................................................................................. |
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1.3 |
Register Mapping.................................................................................................. |
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2 |
ePWM Submodules ................................................................................................... |
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2.1 |
Overview............................................................................................................ |
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2.2 |
Time-Base (TB) Submodule ..................................................................................... |
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2.2.1 Purpose of the Time-Base Submodule................................................................ |
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2.2.2 Controlling and Monitoring the Time-base Submodule.............................................. |
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2.2.3 Calculating PWM Period and Frequency.............................................................. |
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2.2.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules................................ |
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30 |
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2.2.5 Time-base Counter Modes and Timing Waveforms ................................................. |
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2.3 |
Counter-Compare (CC) Submodule ............................................................................ |
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32 |
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2.3.1 Purpose of the Counter-Compare Submodule ....................................................... |
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2.3.2 Controlling and Monitoring the Counter-Compare Submodule..................................... |
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2.3.3 Operational Highlights for the Counter-Compare Submodule...................................... |
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2.3.4 Count Mode Timing Waveforms ....................................................................... |
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2.4 |
Action-Qualifier (AQ) Submodule ............................................................................... |
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37 |
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2.4.1 Purpose of the Action-Qualifier Submodule .......................................................... |
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2.4.2 Action-Qualifier Submodule Control and Status Register Definitions ............................. |
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2.4.3 |
Action-Qualifier Event Priority .......................................................................... |
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40 |
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2.4.4 Waveforms for Common Configurations .............................................................. |
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2.5 |
Dead-Band Generator (DB) Submodule ....................................................................... |
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2.5.1 Purpose of the Dead-Band Submodule ............................................................... |
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2.5.2 Controlling and Monitoring the Dead-Band Submodule............................................. |
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2.5.3 Operational Highlights for the Dead-Band Submodule.............................................. |
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51 |
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2.6 |
PWM-Chopper (PC) Submodule ................................................................................ |
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55 |
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2.6.1 Purpose of the PWM-Chopper Submodule ........................................................... |
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2.6.2 Controlling the PWM-Chopper Submodule ........................................................... |
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2.6.3 Operational Highlights for the PWM-Chopper Submodule.......................................... |
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2.6.4 |
Waveforms ................................................................................................ |
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2.7 |
Trip-Zone (TZ) Submodule....................................................................................... |
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2.7.1 Purpose of the Trip-Zone Submodule ................................................................. |
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2.7.2 Controlling and Monitoring the Trip-Zone Submodule............................................... |
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2.7.3 Operational Highlights for the Trip-Zone Submodule................................................ |
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2.7.4 Generating Trip Event Interrupts ....................................................................... |
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2.8 |
Event-Trigger (ET) Submodule .................................................................................. |
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2.8.1 Operational Overview of the Event-Trigger Submodule............................................. |
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Applications to Power Topologies .............................................................................. |
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3.1 |
Overview of Multiple Modules ................................................................................... |
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3.2 |
Key Configuration Capabilities................................................................................... |
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70 |
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3.3 |
Controlling Multiple Buck Converters With Independent Frequencies ..................................... |
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71 |
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SPRU791D–November 2004–Revised October 2007 |
Contents |
3 |
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3.4 |
Controlling Multiple Buck Converters With Same Frequencies ............................................. |
75 |
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3.5 |
Controlling Multiple Half H-Bridge (HHB) Converters ........................................................ |
78 |
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3.6 |
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM) ........................................... |
80 |
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3.7 |
Practical Applications Using Phase Control Between PWM Modules...................................... |
84 |
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3.8 |
Controlling a 3-Phase Interleaved DC/DC Converter......................................................... |
85 |
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3.9 |
Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter ........................................ |
89 |
4 |
Registers ................................................................................................................. |
93 |
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4.1 |
Time-Base Submodule Registers ............................................................................... |
94 |
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4.2 |
Counter-Compare Submodule Registers....................................................................... |
97 |
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4.3 |
Action-Qualifier Submodule Registers.......................................................................... |
99 |
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4.4 |
Dead-Band Submodule Registers ............................................................................. |
103 |
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4.5 |
PWM-Chopper Submodule Control Register................................................................. |
105 |
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4.6 |
Trip-Zone Submodule Control and Status Registers........................................................ |
106 |
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4.7 |
Event-Trigger Submodule Registers .......................................................................... |
110 |
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4.8 |
Proper Interrupt Initialization Procedure ...................................................................... |
115 |
A |
Revision History ..................................................................................................... |
117 |
4 |
Contents |
SPRU791D–November 2004–Revised October 2007 |
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List of Figures
1-1 |
Multiple ePWM Modules................................................................................................... |
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15 |
1-2 |
Submodules and Signal Connections for an ePWM Module ......................................................... |
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16 |
1-3 |
ePWM Submodules and Critical Internal Signal Interconnects ...................................................... |
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17 |
2-1 |
Time-Base Submodule Block Diagram .................................................................................. |
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23 |
2-2 |
Time-Base Submodule Signals and Registers ......................................................................... |
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24 |
2-3 |
Time-Base Frequency and Period ....................................................................................... |
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26 |
2-4 |
Time-Base Counter Synchronization Scheme 1 ....................................................................... |
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27 |
2-5 |
Time-Base Counter Synchronization Scheme 2 ....................................................................... |
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28 |
2-6 |
Time-Base Counter Synchronization Scheme 3 ....................................................................... |
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29 |
2-7 |
Time-Base Up-Count Mode Waveforms ................................................................................ |
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30 |
2-8 |
Time-Base Down-Count Mode Waveforms ............................................................................. |
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31 |
2-9 |
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event...... |
31 |
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2-10 |
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event ......... |
32 |
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2-11 |
Counter-Compare Submodule............................................................................................ |
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32 |
2-12 |
Detailed View of the Counter-Compare Submodule................................................................... |
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33 |
2-13 |
Counter-Compare Event Waveforms in Up-Count Mode ............................................................. |
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35 |
2-14 |
Counter-Compare Events in Down-Count Mode....................................................................... |
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35 |
2-15 |
Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On |
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Synchronization Event .................................................................................................... |
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36 |
2-16 |
Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization |
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Event ........................................................................................................................ |
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36 |
2-17 |
Action-Qualifier Submodule ............................................................................................... |
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37 |
2-18 |
Action-Qualifier Submodule Inputs and Outputs ....................................................................... |
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2-19 |
Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ............................................ |
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2-20 |
Up-Down-Count Mode Symmetrical Waveform ........................................................................ |
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42 |
2-21 |
Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and |
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EPWMxB—Active High.................................................................................................... |
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43 |
2-22 |
Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and |
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EPWMxB—Active Low .................................................................................................... |
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2-23 |
Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA .............. |
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2-24 |
Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and |
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EPWMxB — Active Low................................................................................................... |
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2-25 |
Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and |
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EPWMxB — Complementary ............................................................................................. |
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48 |
2-26 |
Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active |
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Low........................................................................................................................... |
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2-27 |
Dead_Band Submodule ................................................................................................... |
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50 |
2-28 |
Configuration Options for the Dead-Band Submodule ................................................................ |
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51 |
2-29 |
Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)..................................................... |
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53 |
2-30 |
PWM-Chopper Submodule ............................................................................................... |
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55 |
2-31 |
PWM-Chopper Submodule Operational Details........................................................................ |
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56 |
2-32 |
Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only.................................. |
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56 |
2-33 |
PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ......... |
57 |
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2-34 |
PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining |
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Pulses........................................................................................................................ |
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58 |
2-35 |
Trip-Zone Submodule...................................................................................................... |
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2-36 |
Trip-Zone Submodule Mode Control Logic ............................................................................. |
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62 |
2-37 |
Trip-Zone Submodule Interrupt Logic.................................................................................... |
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63 |
2-38 |
Event-Trigger Submodule ................................................................................................. |
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2-39 |
Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion and Interrupt Signals................ |
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2-40 |
Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs.......................................... |
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2-41 |
Event-Trigger Interrupt Generator........................................................................................ |
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2-42 |
Event-Trigger SOCA Pulse Generator .................................................................................. |
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67 |
SPRU791D–November 2004–Revised October 2007 |
List of Figures |
5 |
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2-43 |
Event-Trigger SOCB Pulse Generator .................................................................................. |
67 |
3-1 |
Simplified ePWM Module.................................................................................................. |
70 |
3-2 |
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ........................................ |
71 |
3-3 |
Control of Four Buck Stages. Here FPWM1¹ FPWM2¹ FPWM3¹ FPWM4 .................................................. |
72 |
3-4 |
Buck Waveforms for Figure 3-3 (Note: Only three bucks shown here) ............................................. |
73 |
3-5 |
Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1)............................................................. |
75 |
3-6 |
Buck Waveforms for Figure 3-5 (Note: FPWM2 = FPWM1)) .............................................................. |
76 |
3-7 |
Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1) ........................................................... |
78 |
3-8 |
Half-H Bridge Waveforms for Figure 3-7 (Note: Here FPWM2 = FPWM1 ).............................................. |
79 |
3-9 |
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ................................ |
81 |
3-10 |
3-Phase Inverter Waveforms for Figure 3-9 (Only One Inverter Shown) ........................................... |
82 |
3-11 |
Configuring Two PWM Modules for Phase Control.................................................................... |
84 |
3-12 |
Timing Waveforms Associated With Phase Control Between 2 Modules .......................................... |
85 |
3-13 |
Control of a 3-Phase Interleaved DC/DC Converter................................................................... |
86 |
3-14 |
3-Phase Interleaved DC/DC Converter Waveforms for Figure 3-13 ................................................ |
87 |
3-15 |
Controlling a Full-H Bridge Stage (FPWM2 = FPWM1)..................................................................... |
89 |
3-16 |
ZVS Full-H Bridge Waveforms ........................................................................................... |
90 |
4-1 |
Time-Base Period Register (TBPRD).................................................................................... |
94 |
4-2 |
Time-Base Phase Register (TBPHS).................................................................................... |
94 |
4-3 |
Time-Base Counter Register (TBCTR) .................................................................................. |
94 |
4-4 |
Time-Base Control Register (TBCTL) ................................................................................... |
95 |
4-5 |
Time-Base Status Register (TBSTS) .................................................................................... |
97 |
4-6 |
Counter-Compare A Register (CMPA) .................................................................................. |
97 |
4-7 |
Counter-Compare B Register (CMPB) .................................................................................. |
98 |
4-8 |
Counter-Compare Control Register (CMPCTL) ........................................................................ |
99 |
4-9 |
Action-Qualifier Output A Control Register (AQCTLA)............................................................... |
100 |
4-10 |
Action-Qualifier Output B Control Register (AQCTLB)............................................................... |
101 |
4-11 |
Action-Qualifier Software Force Register (AQSFRC) ................................................................ |
102 |
4-12 |
Action-Qualifier Continuous Software Force Register (AQCSFRC)................................................ |
102 |
4-13 |
Dead-Band Generator Control Register (DBCTL).................................................................... |
103 |
4-14 |
Dead-Band Generator Rising Edge Delay Register (DBRED)...................................................... |
105 |
4-15 |
Dead-Band Generator Falling Edge Delay Register (DBFED) ..................................................... |
105 |
4-16 |
PWM-Chopper Control Register (PCCTL)............................................................................. |
105 |
4-17 |
Trip-Zone Select Register (TZSEL) .................................................................................... |
107 |
4-18 |
Trip-Zone Control Register (TZCTL) ................................................................................... |
108 |
4-19 |
Trip-Zone Enable Interrupt Register (TZEINT)........................................................................ |
108 |
4-20 |
Trip-Zone Flag Register (TZFLG)....................................................................................... |
109 |
4-21 |
Trip-Zone Clear Register (TZCLR) ..................................................................................... |
110 |
4-22 |
Trip-Zone Force Register (TZFRC)..................................................................................... |
110 |
4-23 |
Event-Trigger Selection Register (ETSEL) ............................................................................ |
111 |
4-24 |
Event-Trigger Prescale Register (ETPS) .............................................................................. |
112 |
4-25 |
Event-Trigger Flag Register (ETFLG).................................................................................. |
113 |
4-26 |
Event-Trigger Clear Register (ETCLR) ................................................................................ |
114 |
4-27 |
Event-Trigger Force Register (ETFRC)................................................................................ |
115 |
6 |
List of Figures |
SPRU791D–November 2004–Revised October 2007 |
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List of Tables
1-1 |
ePWM Module Control and Status Register Set Grouped by Submodule.......................................... |
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18 |
2-1 |
Submodule Configuration Parameters................................................................................... |
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20 |
2-2 |
Time-Base Submodule Registers ........................................................................................ |
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24 |
2-3 |
Key Time-Base Signals.................................................................................................... |
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25 |
2-4 |
Counter-Compare Submodule Registers ............................................................................... |
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33 |
2-5 |
Counter-Compare Submodule Key Signals............................................................................. |
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34 |
2-6 |
Action-Qualifier Submodule Registers................................................................................... |
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37 |
2-7 |
Action-Qualifier Submodule Possible Input Events .................................................................... |
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38 |
2-8 |
Action-Qualifier Event Priority for Up-Down-Count Mode............................................................. |
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40 |
2-9 |
Action-Qualifier Event Priority for Up-Count Mode..................................................................... |
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40 |
2-10 |
Action-Qualifier Event Priority for Down-Count Mode ................................................................. |
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40 |
2-11 |
Behavior if CMPA/CMPB is Greater than the Period .................................................................. |
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41 |
2-12 |
Dead-Band Generator Submodule Registers........................................................................... |
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50 |
2-13 |
Classical Dead-Band Operating Modes ................................................................................ |
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52 |
2-14 |
Dead-Band Delay Values in μS as a Function of DBFED and DBRED ............................................ |
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54 |
2-15 |
PWM-Chopper Submodule Registers ................................................................................... |
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55 |
2-16 |
Possible Pulse Width Values for SYSCLKOUT = 100 MHz .......................................................... |
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57 |
2-17 |
Trip-Zone Submodule Registers ......................................................................................... |
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60 |
2-18 |
Possible Actions On a Trip Event ........................................................................................ |
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61 |
2-19 |
Event-Trigger Submodule Registers .................................................................................... |
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65 |
4-1 |
Time-Base Period Register (TBPRD) Field Descriptions ............................................................. |
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94 |
4-2 |
Time-Base Phase Register (TBPHS) Field Descriptions.............................................................. |
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94 |
4-3 |
Time-Base Counter Register (TBCTR) Field Descriptions............................................................ |
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94 |
4-4 |
Time-Base Control Register (TBCTL) Field Descriptions ............................................................. |
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95 |
4-5 |
Time-Base Status Register (TBSTS) Field Descriptions.............................................................. |
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97 |
4-6 |
Counter-Compare A Register (CMPA) Field Descriptions ............................................................ |
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98 |
4-7 |
Counter-Compare B Register (CMPB) Field Descriptions ............................................................ |
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98 |
4-8 |
Counter-Compare Control Register (CMPCTL) Field Descriptions ................................................. |
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99 |
4-9 |
Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions ....................................... |
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100 |
4-10 |
Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions ....................................... |
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101 |
4-11 |
Action-Qualifier Software Force Register (AQSFRC) Field Descriptions.......................................... |
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102 |
4-12 |
Action-qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions.......................... |
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103 |
4-13 |
Dead-Band Generator Control Register (DBCTL) Field Descriptions.............................................. |
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104 |
4-14 |
Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions ............................... |
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105 |
4-15 |
Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions ............................... |
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105 |
4-16 |
PWM-Chopper Control Register (PCCTL) Bit Descriptions ........................................................ |
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105 |
4-17 |
Trip-Zone Submodule Select Register (TZSEL) Field Descriptions ............................................... |
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107 |
4-18 |
Trip-Zone Control Register (TZCTL) Field Descriptions ............................................................. |
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108 |
4-19 |
Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions ................................................. |
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108 |
4-20 |
Trip-Zone Flag Register (TZFLG) Field Descriptions ................................................................ |
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109 |
4-21 |
Trip-Zone Clear Register (TZCLR) Field Descriptions .............................................................. |
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110 |
4-22 |
Trip-Zone Force Register (TZFRC) Field Descriptions .............................................................. |
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110 |
4-23 |
Event-Trigger Selection Register (ETSEL) Field Descriptions ..................................................... |
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111 |
4-24 |
Event-Trigger Prescale Register (ETPS) Field Descriptions ....................................................... |
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112 |
4-25 |
Event-Trigger Flag Register (ETFLG) Field Descriptions ........................................................... |
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114 |
4-26 |
Event-Trigger Clear Register (ETCLR) Field Descriptions .......................................................... |
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114 |
4-27 |
Event-Trigger Force Register (ETFRC) Field Descriptions ......................................................... |
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115 |
A-1 |
Changes for Revision D.................................................................................................. |
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117 |
SPRU791D–November 2004–Revised October 2007 |
List of Tables |
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8 |
List of Tables |
SPRU791D–November 2004–Revised October 2007 |
Submit Documentation Feedback
SPRU791D–November 2004–Revised October 2007
Read This First
This guide describes the Enhanced Pulse Width Modulator (ePWM) Module. It includes an overview of the module and information about each of the sub-modules:
∙Time-Base Module
∙Counter Compare Module
∙Action Qualifier Module
∙Dead-Band Generator Module
∙PWM Chopper (PC) Module
∙Trip Zone Module
∙Event Trigger Module
Related Documentation From Texas Instruments
The following books describe the TMS320x280x and related support tools that are available on the TI website:
Data Manuals—
SPRS230— TMS320F2809, F2808, F2806, F2802, F2801, C2802, C2801, and F2801x DSPs Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the F280x devices.
SPRS357— TMS320F28044 Digital Signal Processor Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the F28044 device.
CPU User's Guides—
SPRU430— TMS320C28x DSP CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs.
SPRU712— TMS320x280x, 2801x, 2804x System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 280x digital signal processors (DSPs).
Peripheral Guides—
SPRU566— TMS320x28xx, 28xxx Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs).
SPRU716— TMS320x280x, 2801x, 2804x Analog-to-Digital Converter (ADC) Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.
SPRU791— TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion
SPRU924— TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) describes the operation of the high-resolution extension to the pulse width modulator (HRPWM)
SPRU807— TMS320x28xx, 28xxx Enhanced Capture (eCAP) Module Reference Guide describes the enhanced capture module. It includes the module description and registers.
SPRU791D–November 2004–Revised October 2007 |
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Related Documentation From Texas Instruments
SPRU790— TMS320x28xx, 28xxx Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction, and speed information from a rotating machine in high performance motion and position control systems. It includes the module description and registers
SPRU074— TMS320x28xx, 28xxx Enhanced Controller Area Network (eCAN) Reference Guide describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments.
SPRU051— TMS320x28xx, 28xxx Serial Communication Interface (SCI) Reference Guide describes the SCI, which is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.
SPRU059— TMS320x28xx, 28xxx Serial Peripheral Interface (SPI) Reference Guide describes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate.
SPRU721— TMS320x28xx, 28xxx Inter-Integrated Circuit (I2C) Reference Guide describes the features and operation of the inter-integrated circuit (I2C) module that is available on the TMS320x280x digital signal processor (DSP).
SPRU722— TMS320x280x, 2801x, 2804x Boot ROM Reference Guide describes the purpose and features of the bootloader (factory-programmed boot-loading software). It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory.
Tools Guides—
SPRU513— TMS320C28x Assembly Language Tools User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device.
SPRU514— TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device.
SPRU608— The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core.
SPRU625— TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide describes development using DSP/BIOS.
Application Reports—
SPRAAM0— Getting Started With TMS320C28x™ Digital Signal Controllers is organized by development flow and functional areas to make your design effort as seamless as possible. Tips on getting started with C28x™ DSP software and hardware development are provided to aid in your initial design and debug efforts. Each section includes pointers to valuable information including technical documentation, software, and tools for use in each phase of design.
SPRAAD5— Power Line Communication for Lighting Apps using BPSK w/ a Single DSP Controller presents a complete implementation of a power line modem following CEA-709 protocol using a single DSP.
SPRAA85— Programming TMS320x28xx and 28xxx Peripherals in C/C++ explores a hardware abstraction layer implementation to make C/C++ coding easier on 28x DSPs. This method is compared to traditional #define macros and topics of code efficiency and special case registers are also addressed.
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Related Documentation From Texas Instruments
SPRA958— Running an Application from Internal Flash Memory on the TMS320F28xx DSP covers the requirements needed to properly configure application software for execution from on-chip flash memory. Requirements for both DSP/BIOS™ and non-DSP/BIOS projects are presented. Example code projects are included.
SPRAA91— TMS320F280x DSC USB Connectivity Using TUSB3410 USB-to-UART Bridge Chip presents hardware connections as well as software preparation and operation of the development system using a simple communication echo program.
SPRAA58— TMS320x281x to TMS320x280x Migration Overview describes differences between the Texas Instruments TMS320x281x and TMS320x280x DSPs to assist in application migration from the 281x to the 280x. While the main focus of this document is migration from 281x to 280x, users considering migrating in the reverse direction (280x to 281x) will also find this document useful.
SPRAAD8— TMS320280x and TMS320F2801x ADC Calibration describes a method for improving the absolute accuracy of the 12-bit ADC found on the TMS320280x and TMS3202801x devices. Inherent gain and offset errors affect the absolute accuracy of the ADC. The methods described in this report can improve the absolute accuracy of the ADC to levels better than 0.5%. This application report has an option to download an example program that executes from RAM on the F2808 EzDSP.
SPRAAI1— Using Enhanced Pulse Width Modulator (ePWM) Module for 0-100% Duty Cycle Control provides a guide for the use of the ePWM module to provide 0% to 100% duty cycle control and is applicable to the TMS320x280x family of processors.
SPRAA88— Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x presents a method for utilizing the on-chip pulse width modulated (PWM) signal generators on the TMS320F280x family of digital signal controllers as a digital-to-analog converter (DAC).
SPRAAH1— Using the Enhanced Quadrature Encoder Pulse (eQEP) Module provides a guide for the use of the eQEP module as a dedicated capture unit and is applicable to the TMS320x280x, 28xxx family of processors.
SPRA820— Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for online stack overflow detection on the TMS320C28x™ DSP. C-source code is provided that contains functions for implementing the overflow detection on both DSP/BIOS™ and non-DSP/BIOS applications.
SPRA806— An Easy Way of Creating a C-callable Assembly Function for the TMS320C28x DSP provides instructions and suggestions to configure the C compiler to assist with understanding of parameter-passing conventions and environments expected by the C compiler.
Trademarks
TMS320C28x, C28x are trademarks of Texas Instruments.
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Chapter 1
SPRU791D–November 2004–Revised October 2007
The enhanced pulse width modulator (ePWM) peripheral is a key element in controlling many of the power-related systems found in both commercial and industrial equipments. These systems include digital motor control, switch mode power supply control, uninterruptible power supplies (UPS), and other forms of power conversion. The ePWM peripheral performs a digital to analog (DAC) function, where the duty cycle is equivalent to a DAC analog value; it is sometimes referred to as a Power DAC.
This reference guide is applicable for the ePWM found on the TMS320x280x, TMS320x2801x and TMS320x2804x processors. This includes all Flash-based, ROM-based, and RAM-based devices.
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1.1 |
Introduction.............................................................................. |
14 |
1.2 |
Submodule Overview................................................................. |
14 |
1.3 |
Register Mapping...................................................................... |
17 |
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1.1Introduction
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand and use. The ePWM unit described here addresses these requirements by allocating all needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided; instead, the ePWM is built up from smaller single channel modules with separate resources and that can operate together as required to form a system. This modular approach results in an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users to understand its operation quickly.
In this document the letter x within a signal or module name is used to indicate a generic ePWM instance on a device. For example output signals EPWMxA and EPWMxB refer to the output signals from the ePWMx instance. Thus, EPWM1A and EPWM1B belong to ePWM1 and likewise EPWM4A and EPWM4B belong to ePWM4.
The ePWM module represents one complete PWM channel composed of two PWM outputs: EPWMxA and EPWMxB. Multiple ePWM modules are instanced within a device as shown in Figure 1-1. Each ePWM instance is identical with one exception. Some instances include a hardware extension that allows more precise control of the PWM outputs. This extension is the high-resolution pulse width modulator (HRPWM) and is described in the TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (SPRU924). See the device-specific data manual to determine which ePWM instances include this feature. Each ePWM module is indicated by a numerical value starting with 1. For example ePWM1 is the first instance and ePWM3 is the 3rd instance in the system and ePWMx indicates any instance.
The ePWM modules are chained together via a clock synchronization scheme that allows them to operate as a single system when required. Additionally, this synchronization scheme can be extended to the capture peripheral modules (eCAP). The number of modules is device-dependent and based on target application needs. Modules can also operate stand-alone.
Each ePWM module supports the following features:
∙Dedicated 16-bit time-base counter with period and frequency control
∙Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations::
–Two independent PWM outputs with single-edge operation
–Two independent PWM outputs with dual-edge symmetric operation
–One independent PWM output with dual-edge asymmetric operation
∙Asynchronous override control of PWM signals through software.
∙Programmable phase-control support for lag or lead operation relative to other ePWM modules.
∙Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.
∙Dead-band generation with independent rising and falling edge delay control.
∙Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions.
∙A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs.
∙All events can trigger both CPU interrupts and ADC start of conversion (SOC)
∙Programmable event prescaling minimizes CPU overhead on interrupts.
∙PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
Each ePWM module is connected to the input/output signals shown in Figure 1-1. The signals are described in detail in subsequent sections.
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Submodule Overview
Figure 1-1. Multiple ePWM Modules
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xSYNCI |
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SYNCI |
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EPWM1INT |
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EPWM1A |
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EPWM1SOC |
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ePWM1 module |
EPWM1B |
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SYNCO |
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To eCAP1 |
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xSYNCO |
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SYNCI |
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EPWM2INT |
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EPWM2A |
PIE |
EPWM2SOC |
ePWM2 module |
GPIO |
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EPWM2B |
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MUX |
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SYNCO |
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SYNCI |
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EPWMxINT |
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EPWMxA |
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EPWMxSOC |
ePWMx module |
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EPWMxB |
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TZ1 to TZ6 |
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SYNCO |
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xSOC |
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Peripheral |
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ADC |
Frame 1 |
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The order in which the ePWM modules are connected may differ from what is shown in Figure 1-1. See Section 2.2.3.2 for the synchronization scheme for a particular device. Each ePWM module consists of seven submodules and is connected within a system via the signals shown in Figure 1-2.
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Submodule Overview
Figure 1-2. Submodules and Signal Connections for an ePWM Module
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EPWMxSYNCI |
ePWM module |
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Time-base (TB) module |
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EPWMxSYNCO |
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Counter-compare (CC) module |
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EPWMxTZINT |
Action-qualifier (AQ) module |
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PIE |
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EPWMxINT |
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TZ1 to TZ6 |
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Dead-band (DB) module |
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ADC |
EPWMxSOCA |
PWM-chopper (PC) module |
EPWMxA |
GPIO |
EPWMxSOCB |
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MUX |
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EPWMxB |
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Event-trigger (ET) module |
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Peripheral bus |
Trip-zone (TZ) module |
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Figure 1-3 shows more internal details of a single ePWM module. The main signals used by the ePWM module are:
∙PWM output signals (EPWMxA and EPWMxB).
The PWM output signals are made available external to the device through the GPIO peripheral described in the system control and interrupts guide for your device.
∙Trip-zone signals (TZ1 to TZ6).
These input signals alert the ePWM module of an external fault condition. Each module on a device can be configured to either use or ignore any of the trip-zone signals. The trip-zone signals can be configured as asynchronous inputs through the GPIO peripheral.
∙Time-base synchronization input (EPWMxSYNCI) and output (EPWMxSYNCO) signals.
The synchronization signals daisy chain the ePWM modules together. Each module can be configured to either use or ignore its synchronization input. The clock synchronization input and output signal are brought out to pins only for ePWM1 (ePWM module #1). The synchronization output for ePWM1 (EPWM1SYNCO) is also connected to the SYNCI of the first enhanced capture module (eCAP1).
∙ADC start-of-conversion signals (EPWMxSOCA and EPWMxSOCB).
Each ePWM module has two ADC start of conversion signals (one for each sequencer). Any ePWM module can trigger a start of conversion for either sequencer. Which event triggers the start of conversion is configured in the Event-Trigger submodule of the ePWM.
∙Peripheral Bus
The peripheral bus is 32-bits wide and allows both 16-bit and 32-bit writes to the ePWM register file.
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Figure 1-3. ePWM Submodules and Critical Internal Signal Interconnects
Time-base (TB) |
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Sync |
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TBPRD shadow (16) |
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in/out |
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EPWMxSYNCO |
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select |
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TBPRD active (16) |
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MUX |
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CTR_PRD |
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S0 |
S1 |
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16 |
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TBCTL[SWFSYNC] |
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EPWMxSYNCI |
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Counter |
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UP/DWN |
TBCTL[PHSEN] |
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(16 bit) |
CTR = ZERO |
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TBCTL[SWFSYNC] (software |
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TBCTR |
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forced sync) |
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active |
CTR_Dir |
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(16) |
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Phase |
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CTR = PRD |
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TBPHS active (16) |
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EPWMxINT |
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control |
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CTR = ZERO |
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Event |
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CTR = CMPA |
trigger and |
EPWMxSOCA |
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CTR = CMPB |
interrupt |
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Counter compare (CC) |
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(ET) |
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EPWMxSOCB |
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CTR_Dir |
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CTR = CMPA |
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16 |
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Action |
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CMPA active (16) |
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qualifier |
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EPWMxA |
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(AQ) |
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PWM |
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CMPA shadow (16) |
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Dead |
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band |
chopper |
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Trip |
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zone |
EPWMxB |
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CTR = CMPB |
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CMPB active (16) |
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EPWMxTZINT |
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TZ1 to TZ6 |
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CMPB shadow (16) |
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Figure 1-3 also shows the key internal submodule interconnect signals. Each submodule is described in detail in its respective section.
1.3Register Mapping
The complete ePWM module control and status register set is grouped by submodule as shown in Table 1-1. Each register set is duplicated for each instance of the ePWM module. The start address for each ePWM register file instance on a device is specified in the appropriate data manual.
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Register Mapping
Table 1-1. ePWM Module Control and Status Register Set Grouped by Submodule
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Offset (1) |
Size |
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Name |
(x16) |
Shadow |
Description |
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Time-Base Submodule Registers |
TBCTL |
0x0000 |
1 |
No |
Time-Base Control Register |
TBSTS |
0x0001 |
1 |
No |
Time-Base Status Register |
TBPHSHR |
0x0002 |
1 |
No |
Extension for HRPWM Phase Register (2) |
TBPHS |
0x0003 |
1 |
No |
Time-Base Phase Register |
TBCTR |
0x0004 |
1 |
No |
Time-Base Counter Register |
TBPRD |
0x0005 |
1 |
Yes |
Time-Base Period Register |
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Counter-Compare Submodule Registers |
CMPCTL |
0x0007 |
1 |
No |
Counter-Compare Control Register |
CMPAHR |
0x0008 |
1 |
No |
Extension for HRPWM Counter-Compare A Register (2) |
CMPA |
0x0009 |
1 |
Yes |
Counter-Compare A Register |
CMPB |
0x000A |
1 |
Yes |
Counter-Compare B Register |
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Action-Qualifier Submodule Registers |
AQCTLA |
0x000B |
1 |
No |
Action-Qualifier Control Register for Output A (EPWMxA) |
AQCTLB |
0x000C |
1 |
No |
Action-Qualifier Control Register for Output B (EPWMxB) |
AQSFRC |
0x000D |
1 |
No |
Action-Qualifier Software Force Register |
AQCSFRC |
0x000E |
1 |
Yes |
Action-Qualifier Continuous S/W Force Register Set |
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Dead-Band Generator Submodule Registers |
DBCTL |
0x000F |
1 |
No |
Dead-Band Generator Control Register |
DBRED |
0x0010 |
1 |
No |
Dead-Band Generator Rising Edge Delay Count Register |
DBFED |
0x0011 |
1 |
No |
Dead-Band Generator Falling Edge Delay Count Register |
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Trip-Zone Submodule Registers |
TZSEL |
0x0012 |
1 |
No |
Trip-Zone Select Register |
TZCTL |
0x0014 |
1 |
No |
Trip-Zone Control Register (3) |
TZEINT |
0x0015 |
1 |
No |
Trip-Zone Enable Interrupt Register (3) |
TZFLG |
0x0016 |
1 |
No |
Trip-Zone Flag Register (3) |
TZCLR |
0x0017 |
1 |
No |
Trip-Zone Clear Register (3) |
TZFRC |
0x0018 |
1 |
No |
Trip-Zone Force Register (3) |
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Event-Trigger Submodule Registers |
ETSEL |
0x0019 |
1 |
No |
Event-Trigger Selection Register |
ETPS |
0x001A |
1 |
No |
Event-Trigger Pre-Scale Register |
ETFLG |
0x001B |
1 |
No |
Event-Trigger Flag Register |
ETCLR |
0x001C |
1 |
No |
Event-Trigger Clear Register |
ETFRC |
0x001D |
1 |
No |
Event-Trigger Force Register |
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PWM-Chopper Submodule Registers |
PCCTL |
0x001E |
1 |
No |
PWM-Chopper Control Register |
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High-Resolution Pulse Width Modulator (HRPWM) Extension Registers |
HRCNFG |
0x0020 |
1 |
No |
HRPWM Configuration Register (2) (3) |
(1)Locations not shown are reserved.
(2)These registers are only available on ePWM instances that include the high-resolution PWM extension. Otherwise these locations are reserved. These registers are described in the TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (SPRU924). See the device specific data manual to determine which instances include the HRPWM.
(3)EALLOW protected registers as described in the specific device version of the System Control and Interrupts Reference Guide listed in Section 1.
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Chapter 2
SPRU791D–November 2004–Revised October 2007
Seven submodules are included in every ePWM peripheral. Each of these submodules performs specific tasks that can be configured by software.
Topic |
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Page |
2.1 |
Overview.................................................................................. |
20 |
2.2 |
Time-Base (TB) Submodule........................................................ |
23 |
2.3 |
Counter-Compare (CC) Submodule ............................................. |
32 |
2.4 |
Action-Qualifier (AQ) Submodule ................................................ |
37 |
2.5 |
Dead-Band Generator (DB) Submodule........................................ |
50 |
2.6 |
PWM-Chopper (PC) Submodule .................................................. |
55 |
2.7 |
Trip-Zone (TZ) Submodule ......................................................... |
59 |
2.8 |
Event-Trigger (ET) Submodule.................................................... |
63 |
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ePWM Submodules |
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2.1Overview
Table 2-1 lists the seven key submodules together with a list of their main configuration parameters. For example, if you need to adjust or control the duty cycle of a PWM waveform, then you should see the counter-compare submodule in Section 2.3 for relevant details.
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Table 2-1. Submodule Configuration Parameters |
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Submodule |
Configuration Parameter or Option |
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Time-base (TB) |
∙ |
Scale the time-base clock (TBCLK) relative to the system clock (SYSCLKOUT). |
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∙ |
Configure the PWM time-base counter (TBCTR) frequency or period. |
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∙ |
Set the mode for the time-base counter: |
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– count-up mode: used for asymmetric PWM |
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– count-down mode: used for asymmetric PWM |
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– count-up-and-down mode: used for symmetric PWM |
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∙ |
Configure the time-base phase relative to another ePWM module. |
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∙ |
Synchronize the time-base counter between modules through hardware or software. |
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∙ |
Configure the direction (up or down) of the time-base counter after a synchronization event. |
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∙ |
Configure how the time-base counter will behave when the device is halted by an emulator. |
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∙ |
Specify the source for the synchronization output of the ePWM module: |
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– |
Synchronization input signal |
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– Time-base counter equal to zero |
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– Time-base counter equal to counter-compare B (CMPB) |
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– No output synchronization signal generated. |
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Counter-compare (CC) |
∙ |
Specify the PWM duty cycle for output EPWMxA and/or output EPWMxB |
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∙ |
Specify the time at which switching events occur on the EPWMxA or EPWMxB output |
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Action-qualifier (AQ) |
∙ |
Specify the type of action taken when a time-base or counter-compare submodule event occurs: |
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– |
No action taken |
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– Output EPWMxA and/or EPWMxB switched high |
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– Output EPWMxA and/or EPWMxB switched low |
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– Output EPWMxA and/or EPWMxB toggled |
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∙ |
Force the PWM output state through software control |
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∙ |
Configure and control the PWM dead-band through software |
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Dead-band (DB) |
∙ |
Control of traditional complementary dead-band relationship between upper and lower switches |
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∙ |
Specify the output rising-edge-delay value |
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∙ |
Specify the output falling-edge delay value |
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∙ |
Bypass the dead-band module entirely. In this case the PWM waveform is passed through |
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without modification. |
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PWM-chopper (PC) |
∙ |
Create a chopping (carrier) frequency. |
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∙ |
Pulse width of the first pulse in the chopped pulse train. |
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∙ |
Duty cycle of the second and subsequent pulses. |
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∙ |
Bypass the PWM-chopper module entirely. In this case the PWM waveform is passed through |
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without modification. |
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Trip-zone (TZ) |
∙ |
Configure the ePWM module to react to one, all, or none of the trip-zone pins. |
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∙ |
Specify the tripping action taken when a fault occurs: |
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– Force EPWMxA and/or EPWMxB high |
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– Force EPWMxA and/or EPWMxB low |
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– Force EPWMxA and/or EPWMxB to a high-impedance state |
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– Configure EPWMxA and/or EPWMxB to ignore any trip condition. |
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∙ |
Configure how often the ePWM will react to each trip-zone pin: |
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– |
One-shot |
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– Cycle-by-cycle |
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∙ |
Enable the trip-zone to initiate an interrupt. |
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∙ |
Bypass the trip-zone module entirely. |
20 |
ePWM Submodules |
SPRU791D–November 2004–Revised October 2007 |
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|
|
Overview |
|
Table 2-1. Submodule Configuration Parameters (continued) |
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Submodule |
Configuration Parameter or Option |
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Event-trigger (ET) |
∙ |
Enable the ePWM events that will trigger an interrupt. |
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∙ |
Enable ePWM events that will trigger an ADC start-of-conversion event. |
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∙ |
Specify the rate at which events cause triggers (every occurrence or every second or third |
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occurrence) |
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∙ |
Poll, set, or clear event flags |
Code examples are provided in the remainder of this document that show how to implement various ePWM module configurations. These examples use the constant definitions shown in Example 2-1. These definitions are also used in the C280x C/C++ Header Files and Peripheral Examples (SPRC191).
Example 2-1. Constant Definitions Used in the Code Examples
//TBCTL (Time-Base Control)
//= = = = = = = = = = = = = = = = = = = = = = = = = =
//TBCTR MODE bits
#define |
TB_COUNT_UP |
0x0 |
#define |
TB_COUNT_DOWN |
0x1 |
#define |
TB_COUNT_UPDOWN |
0x2 |
#define |
TB_FREEZE |
0x3 |
// PHSEN bit |
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#define |
TB_DISABLE |
0x0 |
#define |
TB_ENABLE |
0x1 |
// PRDLD bit |
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#define |
TB_SHADOW |
0x0 |
#define |
TB_IMMEDIATE |
0x1 |
// SYNCOSEL bits |
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#define |
TB_SYNC_IN |
0x0 |
#define |
TB_CTR_ZERO |
0x1 |
#define |
TB_CTR_CMPB |
0x2 |
#define |
TB_SYNC_DISABLE |
0x3 |
// HSPCLKDIV and CLKDIV bits |
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#define |
TB_DIV1 |
0x0 |
#define |
TB_DIV2 |
0x1 |
#define |
TB_DIV4 |
0x2 |
// PHSDIR bit |
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#define |
TB_DOWN |
0x0 |
#define |
TB_UP |
0x1 |
//CMPCTL (Compare Control)
//= = = = = = = = = = = = = = = = = = = = = = = = = =
//LOADAMODE and LOADBMODE bits
#define |
CC_CTR_ZERO |
0x0 |
#define |
CC_CTR_PRD |
0x1 |
#define |
CC_CTR_ZERO_PRD |
0x2 |
#define |
CC_LD_DISABLE |
0x3 |
// SHDWAMODE and SHDWBMODE bits |
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#define |
CC_SHADOW |
0x0 |
#define |
CC_IMMEDIATE |
0x1 |
//AQCTLA and AQCTLB (Action-qualifier Control)
//= = = = = = = = = = = = = = = = = = = = = = = = = =
//ZRO, PRD, CAU, CAD, CBU, CBD bits
#define |
AQ_NO_ACTION |
0x0 |
#define |
AQ_CLEAR |
0x1 |
#define |
AQ_SET |
0x2 |
#define |
AQ_TOGGLE |
0x3 |
//DBCTL (Dead-Band Control)
//= = = = = = = = = = = = = = = = = = = = = = = = = =
//MODE bits
#define |
DB_DISABLE |
0x0 |
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#define |
DBA_ENABLE |
0x1 |
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#define |
DBB_ENABLE |
0x2 |
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#define DB_FULL_ENABLE 0x3 |
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// POLSEL bits |
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#define |
DB_ACTV_HI |
0x0 |
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#define |
DB_ACTV_LOC |
0x1 |
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#define |
DB_ACTV_HIC |
0x2 |
|
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Overview
Example 2-1. Constant Definitions Used in the Code Examples (continued)
#define |
DB_ACTV_LO |
0x3 |
//PCCTL (chopper control)
//= = = = = = = = = = = = = = = = = = = = = = = = = =
//CHPEN bit
#define |
CHP_ENABLE |
0x0 |
#define CHP_DISABLE 0x1 |
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// CHPFREQ bits |
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#define |
CHP_DIV1 |
0x0 |
#define |
CHP_DIV2 |
0x1 |
#define |
CHP_DIV3 |
0x2 |
#define |
CHP_DIV4 |
0x3 |
#define |
CHP_DIV5 |
0x4 |
#define |
CHP_DIV6 |
0x5 |
#define |
CHP_DIV7 |
0x6 |
#define |
CHP_DIV8 |
0x7 |
// CHPDUTY bits |
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#define |
CHP1_8TH |
0x0 |
#define |
CHP2_8TH |
0x1 |
#define |
CHP3_8TH |
0x2 |
#define |
CHP4_8TH |
0x3 |
#define |
CHP5_8TH |
0x4 |
#define |
CHP6_8TH |
0x5 |
#define |
CHP7_8TH |
0x6 |
//TZSEL (Trip-zone Select)
//= = = = = = = = = = = = = = = = = = = = = = = = = =
//CBCn and OSHTn bits
#define |
TZ_ENABLE |
0x0 |
#define |
TZ_DISABLE |
0x1 |
//TZCTL (Trip-zone Control)
//= = = = = = = = = = = = = = = = = = = = = = = = = =
//TZA and TZB bits
#define |
TZ_HIZ |
0x0 |
#define |
TZ_FORCE_HI |
0x1 |
#define |
TZ_FORCE_LO |
0x2 |
#define |
TZ_DISABLE |
0x3 |
//ETSEL (Event-trigger Select)
//= = = = = = = = = = = = = = = = = = = = = = = = = =
//INTSEL, SOCASEL, SOCBSEL bits
#define |
ET_CTR_ZERO |
0x1 |
#define |
ET_CTR_PRD |
0x2 |
#define |
ET_CTRU_CMPA |
0x4 |
#define |
ET_CTRD_CMPA |
0x5 |
#define |
ET_CTRU_CMPB |
0x6 |
#define |
ET_CTRD_CMPB |
0x7 |
//ETPS (Event-trigger Prescale)
//= = = = = = = = = = = = = = = = = = = = = = = = = =
//INTPRD, SOCAPRD, SOCBPRD bits
#define |
ET_DISABLE |
0x0 |
#define |
ET_1ST |
0x1 |
#define |
ET_2ND |
0x2 |
#define |
ET_3RD |
0x3 |
22 |
ePWM Submodules |
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2.2Time-Base (TB) Submodule
Each ePWM module has its own time-base submodule that determines all of the event timing for the ePWM module. Built-in synchronization logic allows the time-base of multiple ePWM modules to work together as a single system. Figure 2-1 illustrates the time-base module's place within the ePWM.
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Figure 2-1. Time-Base Submodule Block Diagram |
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CTR = PRD |
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EPWMxINT |
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CTR = 0 |
Event |
PIE |
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Action |
CTR = CMPA |
Trigger |
EPWMxSOCA |
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and |
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EPWMxSYNCI |
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Qualifier |
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Interrupt |
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CTR = PRD |
(AQ) |
CTR = CMPB |
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CTR_Dir |
(ET) |
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EPWMxSYNCO |
CTR = 0 |
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EPWMxSOCB |
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(TB) |
CTR_Dir |
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EPWMxA |
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EPWMxA |
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Dead |
PWM- |
Trip |
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CTR = CMPA |
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chopper |
Zone |
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Counter |
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(TZ) |
EPWMxB |
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MUX |
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Compare |
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EPWMxB |
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CTR = CMPB |
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(CC) |
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CTR = 0 |
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PIE |
EPWMxTZINT |
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TZ1 to TZ6 |
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You can configure the time-base submodule for the following:
∙Specify the ePWM time-base counter (TBCTR) frequency or period to control how often events occur.
∙Manage time-base synchronization with other ePWM modules.
∙Maintain a phase relationship with other ePWM modules.
∙Set the time-base counter to count-up, count-down, or count-up-and-down mode.
∙Generate the following events:
–CTR = PRD: Time-base counter equal to the specified period (TBCTR = TBPRD) .
–CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000).
∙Configure the rate of the time-base clock; a prescaled version of the CPU system clock (SYSCLKOUT). This allows the time-base counter to increment/decrement at a slower rate.
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Time-Base (TB) Submodule
Table 2-2 shows the registers used to control and monitor the time-base submodule.
Table 2-2. Time-Base Submodule Registers
Register |
Address offset |
Shadowed |
Description |
TBCTL |
0x0000 |
No |
Time-Base Control Register |
TBSTS |
0x0001 |
No |
Time-Base Status Register |
TBPHSHR |
0x0002 |
No |
HRPWM extension Phase Register (1) |
TBPHS |
0x0003 |
No |
Time-Base Phase Register |
TBCTR |
0x0004 |
No |
Time-Base Counter Register |
TBPRD |
0x0005 |
Yes |
Time-Base Period Register |
(1)This register is available only on ePWM instances that include the high-resolution extension (HRPWM). On ePWM modules that do not include the HRPWM, this location is reserved. This register is described in the TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (SPRU924). See the device specific data manual to determine which ePWM instances include this feature.
The block diagram in Figure 2-2 shows the critical signals and registers of the time-base submodule. Table 2-3 provides descriptions of the key signals associated with the time-base submodule.
Figure 2-2. Time-Base Submodule Signals and Registers
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TBPRD |
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TBCTL[PRDLD] |
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Period Shadow |
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TBPRD |
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Period Active |
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16 |
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TBCTL[SWFSYNC] |
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TBCTR[15:0] |
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CTR = PRD |
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16 |
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EPWMxSYNCI |
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CTR = Zero |
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Reset |
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Zero |
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CTR_dir |
Mode |
TBCTL[CTRMODE] |
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UP/DOWN |
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CTR_max |
Max |
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CTR = Zero |
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TBCLK |
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Sync |
EPWMxSYNCO |
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TBCTR |
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Select |
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Counter Active Reg |
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TBPHS |
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TBCTL[SYNCOSEL] |
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Phase Active Reg |
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SYSCLKOUT |
Clock |
TBCLK |
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TBCTL[HSPCLKDIV] |
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TBCTL[CLKDIV] |
24 |
ePWM Submodules |
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Time-Base (TB) Submodule
|
Table 2-3. Key Time-Base Signals |
Signal |
Description |
EPWMxSYNCI |
Time-base synchronization input. |
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Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the |
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synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first ePWM |
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module (EPWM1) this signal comes from a device pin. For subsequent ePWM modules this signal is passed |
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from another ePWM peripheral. For example, EPWM2SYNCI is generated by the ePWM1 peripheral, |
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EPWM3SYNCI is generated by ePWM2 and so forth. See Section 2.2.3.2 for information on the |
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synchronization order of a particular device. |
EPWMxSYNCO |
Time-base synchronization output. |
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This output pulse is used to synchronize the counter of an ePWM module later in the synchronization chain. |
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The ePWM module generates this signal from one of three event sources: |
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1. EPWMxSYNCI (Synchronization input pulse) |
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2. CTR = Zero: The time-base counter equal to zero (TBCTR = 0x0000). |
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3. CTR = CMPB: The time-base counter equal to the counter-compare B (TBCTR = CMPB) register. |
CTR = PRD |
Time-base counter equal to the specified period. |
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This signal is generated whenever the counter value is equal to the active period register value. That is when |
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TBCTR = TBPRD. |
CTR = Zero |
Time-base counter equal to zero |
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This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x0000. |
CTR = CMPB |
Time-base counter equal to active counter-compare B register (TBCTR = CMPB). |
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This event is generated by the counter-compare submodule and used by the synchronization out logic |
CTR_dir |
Time-base counter direction. |
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Indicates the current direction of the ePWM's time-base counter. This signal is high when the counter is |
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increasing and low when it is decreasing. |
CTR_max |
Time-base counter equal max value. (TBCTR = 0xFFFF) |
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Generated event when the TBCTR value reaches its maximum value. This signal is only used only as a status |
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TBCLK |
Time-base clock. |
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This is a prescaled version of the system clock (SYSCLKOUT) and is used by all submodules within the |
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ePWM. This clock determines the rate at which time-base counter increments or decrements. |
The frequency of PWM events is controlled by the time-base period (TBPRD) register and the mode of the time-base counter. Figure 2-3 shows the period (Tpwm) and frequency (Fpwm) relationships for the up-count, down-count, and up-down-count time-base counter modes when when the period is set to 4 (TBPRD = 4). The time increment for each step is defined by the time-base clock (TBCLK) which is a prescaled version of the system clock (SYSCLKOUT).
The time-base counter has three modes of operation selected by the time-base control register (TBCTL):
∙Up-Down-Count Mode:
In up-down-count mode, the time-base counter starts from zero and increments until the period (TBPRD) value is reached. When the period value is reached, the time-base counter then decrements until it reaches zero. At this point the counter repeats the pattern and begins to increment.
∙Up-Count Mode:
In this mode, the time-base counter starts from zero and increments until it reaches the value in the period register (TBPRD). When the period value is reached, the time-base counter resets to zero and begins to increment once again.
∙Down-Count Mode:
In down-count mode, the time-base counter starts from the period (TBPRD) value and decrements until it reaches zero. When it reaches zero, the time-base counter is reset to the period value and it begins to decrement once again.
SPRU791D–November 2004–Revised October 2007 |
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Time-Base (TB) Submodule
Figure 2-3. Time-Base Frequency and Period
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PRD |
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For Up Count and Down Count
TPWM = (TBPRD + 1) x TTBCLK
FPWM = 1/ (TPWM)
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2.2.3.1Time-Base Period Shadow Register
The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to be synchronized with the hardware. The following definitions are used to describe all shadow registers in the ePWM module:
∙Active Register
The active register controls the hardware and is responsible for actions that the hardware causes or invokes.
∙Shadow Register
The shadow register buffers or provides a temporary holding location for the active register. It has no direct effect on any control hardware. At a strategic point in time the shadow register's content is transferred to the active register. This prevents corruption or spurious operation due to the register being asynchronously modified by software.
The memory address of the shadow period register is the same as the active register. Which register is written to or read from is determined by the TBCTL[PRDLD] bit. This bit enables and disables the TBPRD shadow register as follows:
∙Time-Base Period Shadow Mode:
The TBPRD shadow register is enabled when TBCTL[PRDLD] = 0. Reads from and writes to the
TBPRD memory address go to the shadow register. The shadow register contents are transferred to the active register (TBPRD (Active) ← TBPRD (shadow)) when the time-base counter equals zero (TBCTR = 0x0000). By default the TBPRD shadow register is enabled.
∙Time-Base Period Immediate Load Mode:
If immediate load mode is selected (TBCTL[PRDLD] = 1), then a read from or a write to the TBPRD memory address goes directly to the active register.
26 |
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Time-Base (TB) Submodule
2.2.3.2Time-Base Counter Synchronization
A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The input synchronization for the first instance (ePWM1) comes from an external pin. The possible synchronization connections for the remaining ePWM modules are shown in Figure 2-4, Figure 2-5, and Figure 2-6.
Scheme 1 shown in Figure 2-4 applies to the 280x and 2801x devices. Scheme 1 also applies to the 2804x devices when the ePWM pinout is configured for 280x compatible mode (GPAMCFG[EPWMMODE] = 0).
Figure 2-4. Time-Base Counter Synchronization Scheme 1
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EPWM1SYNCI |
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ePWM1 |
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MUX |
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EPWM1SYNCO |
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SYNCI
eCAP1
EPWM2SYNCI
ePWM2
EPWM2SYNCO
EPWM3SYNCI
ePWM3
EPWM3SYNCO
EPWMxSYNCI
ePWMx
EPWMxSYNCO
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Scheme 2 shown in Figure 2-5 is used by the 2804x devices when the ePWM pinout is configured for A-channel only mode (GPAMCFG[EPWMMODE] = 3). If the 2804x ePWM pinout is configured for 280x compatible mode (GPAMCFG[EPWMMODE] = 0), then Scheme 1 is used.
Figure 2-5. Time-Base Counter Synchronization Scheme 2
EPWM1SYNCI |
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ePWM1 |
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EPWM1SYNCO |
MUX |
SYNCI
eCAP1
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EPWM13SYNCI |
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EPWM9SYNCI |
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EPWM5SYNCI |
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EPWM2SYNCI |
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ePWM13 |
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ePWM9 |
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ePWM5 |
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ePWM2 |
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EPWM13SYnCO |
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EPWM9SYNCO |
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EPWM5SYNCO |
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EPWM2SYNCO |
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EPWM14SYNCI |
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EPWM10SYNCI |
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EPWM6SYNCI |
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EPWM3SYNCI |
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ePWM14 |
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ePWM10 |
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ePWM6 |
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ePWM3 |
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EPWM14SYNCO |
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EPWM10SYNCO |
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EPWM36YNCO |
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EPWM3SYNCO |
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EPWM15SYNCI |
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EPWM11SYNCI |
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EPWM7SYNCI |
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EPWM4SYNCI |
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ePWM15 |
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ePWM11 |
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ePWM7 |
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ePWM4 |
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EPWM15SYNCO |
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EPWM11SYNCO |
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EPWM7SYNCO |
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EPWM4SYNCO |
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EPWM16SYNCI |
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EPWM12SYNCI |
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EPWM8SYNCI |
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ePWM16 |
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ePWM12 |
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ePWM8 |
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EPWM16SYNCO |
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EPWM12SYNCO |
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EPWM8SYNCO |
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Scheme 3, shown in Figure 2-6, is used by all other devices.
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Figure 2-6. Time-Base Counter Synchronization Scheme 3
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EPWM1SYNCI |
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ePWM1 |
MUX |
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SYNCI |
EPWM1SYNCO |
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eCAP1 |
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EPWM2SYNCI EPWM2SYNCI ePWM4 ePWM2 EPWM2SYNCO EPWM2SYNCO
EPWM3SYNCI EPWM3SYNCI ePWM5 ePWM3 EPWM3SYNCO EPWM3SYNCO
EPWMxSYNCI
ePWM6
EPWMxSYNCO
Each ePWM module can be configured to use or ignore the synchronization input. If the TBCTL[PHSEN] bit is set, then the time-base counter (TBCTR) of the ePWM module will be automatically loaded with the phase register (TBPHS) contents when one of the following conditions occur:
∙EPWMxSYNCI: Synchronization Input Pulse:
The value of the phase register is loaded into the counter register when an input synchronization pulse is detected (TBPHS → TBCNT). This operation occurs on the next valid time-base clock (TBCLK) edge.
∙Software Forced Synchronization Pulse:
Writing a 1 to the TBCTL[SWFSYNC] control bit invokes a software forced synchronization. This pulse is ORed with the synchronization input signal, and therefore has the same effect as a pulse on EPWMxSYNCI.
This feature enables the ePWM module to be automatically synchronized to the time base of another ePWM module. Lead or lag phase control can be added to the waveforms generated by different ePWM modules to synchronize them. In up-down-count mode, the TBCTL[PSHDIR] bit configures the direction of the time-base counter immediately after a synchronization event. The new direction is independent of the direction prior to the synchronization event. The TBPHS bit is ignored in count-up or count-down modes. See Figure 2-7 through Figure 2-10 for examples.
Clearing the TBCTL[PHSEN] bit configures the ePWM to ignore the synchronization input pulse. The synchronization pulse can still be allowed to flow-through to the EPWMxSYNCO and be used to synchronize other ePWM modules. In this way, you can set up a master time-base (for example, ePWM1) and downstream modules (ePWM2 - ePWMx) may elect to run in synchronization with the master. See the Application to Power Topologies Chapter 3 for more details on synchronization strategies.
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The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM modules on a device. This bit is part of the DSPs clock enable registers and is described in the specific device version of the System Control and Interrupts Reference Guide listed in Section 1. When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped (default). When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must be set identically. The proper procedure for enabling the ePWM clocks is as follows:
1.Enable the individual ePWM module clocks. This is described in the specific device version of the
System Control and Interrupts Reference Guide listed in Section 1.
2.Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
3.Configure the prescaler values and desired ePWM modes.
4.Set TBCLKSYNC = 1.
2.2.5Time-base Counter Modes and Timing Waveforms
The time-base counter operates in one of four modes:
∙Up-count mode which is asymmetrical.
∙Down-count mode which is asymmetrical.
∙Up-down-count which is symmetrical
∙Frozen where the time-base counter is held constant at the current value
To illustrate the operation of the first three modes, the following timing diagrams show when events are generated and how the time-base responds to an EPWMxSYNCI signal.
Figure 2-7. Time-Base Up-Count Mode Waveforms
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TBCTR[15:0] |
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0xFFFF |
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TBPRD |
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TBPHS |
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EPWMxSYNCI |
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CTR_dir |
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CTR = zero |
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CTR = PRD |
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CNT_max |
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