Tern R-Engine-D Technical Manual

R-Engine-D™

16-bit Controller with 16-bit SRAM & Flash, Ethernet Interface,

Compact Flash interface with file system support, ADC/DAC

based on the 40MHz Am186ER or 80MHz RDC R1100

Technical Manual

1724 Picasso Avenue, Davis, CA 95616-0547, USA
Tel: [phone] Fax: [phone]
Email: [e-mail] http://www.tern.com

COPYRIGHT

R-Engine, R-Engine-D, MemCard-A, MotionC, and ACTF are trademarks of TERN, Inc.

Am186ER is a trademark of Advanced Micro Devices, Inc.

Paradigm C/C++ is a trademark of Paradigm Systems.

Microsoft, MS-DOS, Windows, Windows95/98/2000/NT/XP are trademarks of

Microsoft Corporation.

IBM is a trademark of International Business Machines Corporation.

Version 1.00

May 27, 2003

No part of this document may be copied or reproduced in any form or by any means

without the prior written consent of TERN, Inc.

© 2002

1724 Picasso Avenue, Davis, CA 95616-0547, USA

Tel: [phone] Fax: [phone]

Email: [e-mail] http://www.tern.com

Important Notice

TERN is developing complex, high technology integration systems. These systems are
integrated with software and hardware that are not 100% defect free. TERN products are

not designed, intended, authorized, or warranted to be suitable for use in life-support
applications, devices, or systems, or in other critical applications. TERN and the Buyer

agree that TERN will not be liable for incidental or consequential damages arising from
the use of TERN products. It is the Buyer's responsibility to protect life and property
against incidental failure.
TERN reserves the right to make changes and improvements to its products
without providing notice.

R-Engine-D Chapter 1: Introduction

Chapter 1: Introduction

1.1 Technical Manual Organization

This technical manual will require special organization to accommodate the possibility of configuring the
R-Engine-D with two different CPUs. The CPUs are very similar, yet they do have a few differences. For
purposes of organization, it will be assumed that throughout this technical manual, all information given is
accurate for both CPUs, unless otherwise stated. In general, it will be written referring to the Am186ER,
but will implicitly apply to the R1100 also. When information may deviate between CPUs, it will be
explicitly shown.

The rd.ide (tern\186) provides the user with sample and demos for hardware on the RD.

1.2 Functional Description

The R-Engine-D™ (RE) is a high performance, low cost, C/C++ programmable controller based on the
Am186ER CPU (40 MHz, 16-bit CPU, AMD). It is intended for industrial process control and high-speed
data acquisition, and especially ideal for OEM applications.The RE has 32KB internal RAM, which fulfills
many embedded OEM products SRAM requirement. No external SRAM would be required for an OEM
version of the RE (with Am186ER CPU only). This increases system reliability, while decreasing power
consumption and cost.

The RE features fast execution times through 16-bit ACTF Flash (256 KW) and battery-backed SRAM
(256 KW); it also includes 3 timers, PWMs, 32 PIOs, 24 PPIs, 512-byte serial EEPROM, an internal
UART, a sync serial port, 3 timer/counters, and a watchdog timer.

RTC

ADC

ADS 8344

8 chs.

DS1337

256KW

SRAM

256KW

Flash

J1 Header – A/D Bus

ADC

AD7852

8 chs.

J4 Header – A/D Bus

R-Engine-D

50-pin Compact

Flash interface

Am186ER – 40MHz

R1100 – 80MHz

3 16-bit timers/counters

6 external interrupts

1 Asynch / 1 Synch UART

32 I/O lines

16-bit external A/D bus

DAC

7612U

4 chs.

OR

PWM

Supervisor

MAX691

DAC

DA7625

4 chs.

J4 Header – A/D Bus

24 TTL

I/Os

Dual UART

SC29C92

512 byte

EEPROM

CS8900

Ethernet

controller

PPI

14 High
Voltage

Drivers

J5
8-pin
RJ45

1-1

Chapter 1: Introduction R-Engine-D

Figure 1.1 Functional block diagram of the R-Engine-

The three 16-bit timers can be used to count or time external events, up to 10 MHz, 20MHz with the
R1100, or to generate non-repetitive or variable-duty-cycle waveforms as PWM outputs. The 32 PIO pins
from the Am186ER are multifunctional and user programmable.

A serial real time clock (DS1337, Dallas) is a low power clock/calendar with two time-of-day alarms and a
programmable square-wave output. A Dual UART (SC26C92) provides two channels of full-duplex
asynchronous receivers and transmitters; this combines with a single port available from the processor for a
total of three RS-232 serial ports. (This differs from most other core Engine controllers, offering 2 ports
through the processor.) The receivers are quadruple buffered to minimize the potential of receiver overrun
or to reduce interrupt overhead. The UARTs incorporate 9-bit mode for multi-processor communications.
Each UART also offers 7 TTL inputs and 8 TTL outputs. The PPI (82C55) provides an additional 24 user
programmable bi-directional I/Os. The PPI chip can interface to another processor module, or to an LCD
and keypad(s). The R-Engine-D also offers 14 high voltage sinking drivers or optional 16 high voltage
sourcing drivers, capable of sinking/sourcing 350mA at 50V per line.

The DAC (DAC7612) supports two channels of 12-bit, 0-4.095V analog voltage outputs capable of
sinking or sourcing 5 mA. Two of these are available to be installed on the R-Engine-D. A high-speed, up
to 300K samples per second, 8-channel, 12-bit parallel ADC (AD7852) can be installed. This ADC
includes sample-and-hold and precision internal reference, and has an input range of 0-5 V. The RE also
supports a 4-channel, high-speed parallel DAC* (DA7625, 0-2.5V, 200KHz).

An optional 16-bit serial ADC (ADS8344, 100KHz) successive approximation converter, offering 8 single­ended input or 4-differential inputs, is also available.

A 50-pin CompactFlash receptacle can be installed to allow access to mass storage CompactFlash cards
(up to 1GB). Users can easily add mass data storage to their embedded application. FAT File system
support is available.

An Ethernet LAN controller (CS8900) can be installed to provide network connectivity. A RJ45 8-pin
connector is used to connect to a 10-baseT Ethernet network. Software libraries are available.

1.3 Features

• Dimensions: 3.9 x 3.6 inches

• Temperature: -40°C to +80°C

• 40 MHz, 16-bit CPU (Am186ER), Intel 80x86 compatible, OR

• 80 MHz, 16-bit CPU (R1100)

• 32KB internal RAM, Am186ER ONLY

• Easy to program in C/C++

• Power consumption: 160 mA

• Power-save mode: 20 mA

• Standby mode: 50µA

• Power input: + 9V to +12V unregulated DC with linear regulator (standard)

+9V to +30V unregulated DC with optional switching regulator

• Up to 256 KW 16-bit SRAM, 256 KW 16-bit Flash *

• 8-channel 300 KHz parallel 12-bit ADC (AD7852) with 0-5V analog input*

• 4-channel 200 KHz parallel 12-bit DAC (DA7625) with 0-2.5V analog output*

• 4-channels serial 12-bit DAC (DAC7612), 7us settling time*

• 8-channel serial 16-bit ADC (ADS8344) with 0-5V analog input*

• 16-bit external data bus expansion port

• 10-baseT ethenet network connectivity with LAN controller (CS8900)

1-2

R-Engine-D Chapter 1: Introduction

• Up to 1GB memory expansion via CompactFlash interface

• 3 serial ports (1 from Am186ER, plus two from SCC2692 UART) support full-duplex 7, 8 or 9-bit

asynchronous communication (only SCC2692 supports 9-bit)

• 14 sinking / 16 sourcing high voltage drivers

• 2 high-speed PWM outputs

• 6 external interrupt inputs, 3 16-bit timer/counters

• 32 multifunctional I/O lines from Am186ER

• 24 bi-directional I/O lines from 82C55 PPI

• 512-byte serial EEPROM

• Supervisor chip (691) for reset and watchdog

• Real-time clock (DS1337), lithium coin battery*

* = optional

1.4 Physical Description

The physical layout of the R-Engine-D is shown below.

SER0

(Debug serial port)

+12V

Input

Step 2 Jumper

J2 pins 38 & 40

J2 Header

Interrupts, PIOs

SCC2692

Dual UART

CS8900

Ethernet controller

High voltage

drivers

PPI

24 bi-directional

TTL level I/Os

4-ch. 12-bit

DAC 200KHz

J3, J4 Header

ADC, DAC, PPI I/O

J1 Header

Address / Data

Expansion Bus

Flash & SRAM

Up to 256KW of each

8-ch. 12

ADC 300KHz

Dual 2-ch.

12-bit DAC

8-ch.

16-bit

ADC

1-3

Chapter 1: Introduction R-Engine-D

Power On or Reset

Step 2 jumper

set?

NO

STEP 1

ACTF menu sent out through ser0

at 19200 baud

Figure 1.2 Flow chart for ACTF operation

The “ACTF boot loader” resides in the top protected sector of the 256KW on-board Flash chip (29F400).

At power-on or RESET, the “ACTF” will check the STEP 2 jumper. If STEP 2 jumper is not installed, the
ACTF menu will be sent out from serial port0 at 19200 baud. If STEP 2 jumper is installed, the “jump
address” located in the on-board serial EE (see App. E) will be read out and the CPU will jump to that
address. A DEBUG kernel “re40_115.hex” can be downloaded to a starting address of “0xFA000” of the
256KW on-board flash chip.

YES

STEP 2

Go to Application Code CS:IP
CS:IP in EEPROM:

0x10=CS high byte
0x11=CS low byte
0x12=IP high byte
0x13=IP low byte

1-4

R-Engine-D Chapter 1: Introduction

p

y

1.5 R-Engine-D Programming Overview

Preparing for Debug Mode

1. Connect RD to PC with RS-232 link at 19,200, N, 8,
1

2. Power on RD with step 2 jumper rem

3. ACTF menu sent to hyper terminal

4..Type ‘D’, <enter>. Send tern\186\ro

5. Type ‘G04000” to run l_debug.hex

6. Send tern\86\rom\re\re40_

7. Type ‘GFA000’, <enter>

8. On-board LED blinks twice then stays on.

9. Debug kernel running, ready to download

115.hex. Starts at 0xFA000

oved (J2.38, 40)

m\re\l_debug.hex

Step 1: Debug Mode

1. Launch Paradigm C/C++

2. Open “rd.ide” in the tern\186 directory

3. Run samples

4. Use samples to build application in C/C++

5. Single step, set breakpoints, debug code

6. Debug kernel must be running each time to download.

7. If LED does not blink twice then stay on, repeat steps
1-3 and 7-10 of above section.

Step 2: Standalone Mode

1. Run controller in standalone mode, away from PC.
Application resides in battery-backed SRAM. Set CS:IP
to point to application.

2. Power on RD without step 2 jumper set.

3. See menu at hyper terminal. 19,200, N, 8, 1

4. Type ‘G08000’ to jump to and execute code in SRAM

5. Set step 2 jumper, cycle power. Will execute code in
SRAM at every power-up.

6. Test application.

7. Return to Ste

1 as necessar

Step 3: Production

1. Generate application HEX file with Paradigm C/C++
based on field tested source code.

2. Power on board with step 2 jumper removed. See menu.

3. Use ‘D’ command to download l_29f400.hex in the
tern\186\rom\re directory. Will prepare flash.

4. Send application HEX file.

5. Use ‘G’ command to modify CS:IP to point to
application in flash, type ‘G80000’ at menu.

6. Set step 2 jumper.

1-5

Chapter 1: R-Engine-D

Introduction

There is no ROM socket on the RE. The user’s application program must reside in SRAM for debugging in
STEP1, reside in battery-backed SRAM for the standalone field test in STEP2, and finally be programmed
into Flash for a complete product. For production, the user must produce an ACTF-downloadable HEX file
for the application, based on the DV-P Kit. The “STEP2” jumper (J2 pins 38-40) must be installed for
every production-version board.

Step 1 settings

In order to talk to RD with Paradigm C++, the RD must meet these requirements:

1) RE40_115.HEX must be pre-loaded into Flash starting address 0xfa000.

2) The SRAM installed must be large enough to hold your program.

For a 64 KW SRAM, the physical address is 0x00000-0x01ffff
For a 256 KW SRAM, the physical address is 0x00000-0x07ffff

3) The on-board EE must have a Jump Address for the RE40_115.HEX with starting address of 0xfa000.

4) The STEP2 jumper must be installed on J2 pins 38-40.

For further information on programming the R-Engine-D, refer to the Software chapter.

1.6 Minimum Requirements for RD System Development

1.6.1 Minimum Hardware Requirements

• PC or PC-compatible computer with serial COMx port that supports 115,200 baud

• R-Engine-D controller

• PC-V25 serial cable (RS-232; DB9 connector for PC COM port and IDE 2x5 connector for controller)

• center negative wall transformer (+9V, 500 mA)

1.6.2 Minimum Software Requirements

• TERN EV-P Kit installation CD and a PC running: Windows 95/98/NT/2000/XP

With the EV-P Kit, you can program and debug the R-Engine-D in Step One and Step Two, but you cannot
run Step Three. In order to generate an application Flash file and complete a project, you will need the
Development Kit (DV-P Kit).

1-6

R-Engine-D Chapter 2: Installation

Chapter 2: Installation

2.1 Software Installation

Please refer to the Technical manual for the “C/C++ Development Kit and Evaluation Kit for TERN
Embedded Microcontrollers” for information on installing software.

The README.TXT file on the TERN EV-P/DV-P disk contains important information about the
installation and evaluation of TERN controllers.

2.2 Hardware Installation

Overview

• • Connect Debug-serial cable:

For debugging (STEP 1), place IDE connector on SER0 (H2) with
red edge of cable at pin 1

Connect wall transformer:

Connect 9V wall transformer to power and plug into power jack
adapter, which installs into green screw terminal

Hardware installation for the R-Engine-D consists primarily of connecting the microcontroller to your PC
and to power. The green screw terminal, T1, is used to supply unregulated +12V DC to the R-Engine-D,
while the 5x2 pin header, H2, is used to connect the debug serial port to your PC.

2.2.1 Connecting the R-Engine-D to power and PC

Install the power jack adapter into the T1 screw terminal. You may use an ohm meter to confirm which pin
is ground and which pin is +12V. The diagram below also illustrates the correct orientation. Plug the
output of the wall transformer into the power jack adapter. The RD will now power on. With the step 2
jumper removed, the RD will send the ACTF menu out on SER0, or H2. With the step 2 jumper installed,
the RD will fetch the CS:IP stored in the non-volatile EEPROM and jump to that CS:IP for immediate
execution. Refer to Chapter One of this manual for a synopsis on programming the RD.

Next, install the serial debug cable. The DB9 installs on an available COM port on your PC. The Paradigm
C/C++ IDE uses COM0 by default, which can be changed during the install process, or manually after
install. The 1- pin IDE connector installs on the H2 pin header on the RD. This header is the debug serial
port. Note that the red edge of the cable must align with pin 1 of the H2 header. See the below diagram to
help with correct orientation.

2-1

Chapter 2: Installation R-Engine-D

Power Jack

Red Edge of debug

cable aligned with

Pin 1 of H2

T1 Screw
Terminal

Adapter

Output of wall

transformer

GND +12V

2-2

R-Engine-D Chapter 3: Hardware

Chapter 3: Hardware

3.1 Am186ER AND RDC R1100

The R-Engine-D is compatible with two different CPUs. Both offer and support the same on-board
peripherals as well as the on the CPU itself, aside from a few differences. The Am186ER, from AMD, uses
times-four crystal frequency, while the R1100, from RDC, uses times-eight. The R-Engine-D uses a
10MHz system clock, giving the Am186ER a CPU clock of 40MHz and the R1100 a CPU clock of
80MHz. Both CPUs operate at +3.3V, with lines +5V tolerant. Secondly, the internal architectures are
different, with the Am186ER using x86 architecture, and the R1100 using the RISC architecture. Despite
the differing architectures, both CPUs offer nearly identical functionality.

3.2 Am186ER – Introduction

The Am186ER is based on the industry-standard x86 architecture. The Am186ER controllers are higher­performance, more integrated versions of the 80C188 microprocessors. In addition, the Am186ER has new
peripherals. The on-chip system interface logic can minimize total system cost. The Am186ER has one
asynchronous serial port, one synchronous serial port, 32 PIOs, a watchdog timer, additional interrupt
pins, DMA to and from serial ports, a 16-bit reset configuration register, and enhanced chip-select
functionality.

In addition, the
speed zero wait-state memory. In some instances, users can operate the R-Engine-D without external
SRAM, relying only on the Am186ER’s internal RAM.

Am186ER has 32KB of internal volatile RAM. This provides the user with access to high

3.3 RDC R1100 – Introduction

The RDC 1100 is based on RISC internal architecture. It provides faster operation than the Am186ER,
allowing it to operate at up to 80MHZ, based a 10MHz system clock and times-eight crystal operation. The
RDC R1100 does not offer internal RAM like the Am186ER, so external SRAM is mandatory if using the
RDC R1100.

3.4 Am186ER – Features

Clock

Due to its integrated clock generation circuitry, the Am186ER microcontroller allows the use of a times­four crystal frequency. The design achieves 40 MHz CPU operation, while using a 10 MHz crystal.

The R1100 offers times-eight crystal frequency, achieving 80MHz operation based on a 10MHz crystal.

The system CLKOUTA signal is routed to J1 pin 4, default 40 MHz. The CLKOUTB signal is not
connected in the R-Engine-D.

CLKOUTA remains active during reset and bus hold conditions. The R-Engine-D initial function ae_init();
disables CLKOUTA and CLKOUTB with clka_en(0); and clkb_en(0);

You may use clka_en(1); to enable CLKOUTA=CLK=J1 pin 4.

External Interrupts and Schmitt Trigger Input Buffer

There are six external interrupts: INT0-INT4 and NMI.

3-1

Chapter 3: Hardware R-Engine-D

/INT0, J2 pin 8, is used by SCC2692 UART.
/INT1, J2 pin 6
INT2, J2 pin 19, also tied to alarm output of the DS1337 R
INT3, J2 pin 21, used by the CS8900 Ethernet
INT4, not tied to

/NMI, J2 pin 7

Two external interrupt inputs, /INT0-1, are buffered by Schmitt-trigger inverters (U9, 74HC14), in order to
increase and transform slowly changing input signals to fast changing and jitter-free
si

These buffered external interrupt inputs require a falling edge (HIGH-to-LOW) to generate an interrupt.

noise immunity

gnals. As a result of this buffering, these pins are capable of only acting as input.

external pin, used by Compact Flash interface

/INT0=J2.8

interface

U9C

/INT1=J2.6

U9D

TC

INT0

INT1

=U2.56

=U2.55

Figure 3.1 External interrupt inputs

Remember that /INT0 is
unless SER1 and SER2 ar

The R-Engine-D uses vector interrupt functions to respond to external interrupts. Refer to the Am186ER
User’s manual for information about interrupt v

used by the external Dual UART. /INT0 should not be used by application

e not being used.

ectors.

Asynchronous Serial Port

The Am186ER and R1100 CPU has one asynchronous

• Full-duplex operation

• 7-bit, and 8-bit data transfers

• Odd, even, and no parity

•

One or two stop bits

•

Error detection

•

Hardware flow control

• from serial port (Am186ER ONLY)

DMA transfers to and

• eive interrupts

Transmit and rec

• /16 of the CPU clock speed

Maximum baud rate of 1

•

Independent baud rate generators

The software drivers for the asynch. serial port implement a ring-buffered DMA receiving and ring­buffered e s0_echo.c

interrupt transmitting arrangement. See the sample fil

serial channel. It support the following:

An exte n position U4. For more information about the external UART
SCC26C92, please refer to the section in this manual on the SCC26C92.

rnal SCC26C92 UART is located i

3-2

R-Engine-D Chapter 3: Hardware

Note that while the Am186ER supports DMA transfers to and from its asynchronous serial port, the
R1100 does not. Despite this difference, the TERN software drivers for the asynchronous serial port
support both CPUs.

Timer Control Unit

The timer/counter unit has

Timer0 and Timer1 are connected to four external pins:

Timer0 output = P10 = J2 pin 12
Timer0 input = P11 = J2 pin 14
Timer1 output = P1 = J2 pin 29
Timer1 input = P0 = J2 pin 20

These tw rnal events, or they can generate non-repetitive or
variable ef

Timer2 is not connected to any external pin. It can be used as an internal timer for real-time coding or
time-delay applications. It can als

Timer 0 output, P1, is used as the clock input for the AD7852. Timer 0 should therefore not be used
by application unless the AD7852 is not used.

The maximum rate at which each timer can operate is 10 MHz for the Am186ER and 20MHz for the
R1100, since each timer is serviced once every fo
cycles to respond to clock or gate events. See the sample programs timer0.c and ae_cnt0.c in the
\samples\ae directory.

o timers can be used to count or time exte

-duty-cycle wav orms.

three 16-bit programmable timers: Timer0, Timer1, and Timer2.

o prescale timer 0 and timer 1 or be used as a DMA request source.

urth CPU clock cycle. Timer inputs take up to six clock

PWM outputs

The Timer0 and
waveforms. The tim
timer output cycle is 25 ns x 6 = 150 ns (at 40 MHz).

Timer1 outputs can also be used to generate non-repetitive or variable-duty-cycle

er output takes up to 6 clock cycles to respond to the clock input. Thus the minimum

Each timer has a maximum count register that defines the maximum value the timer will reach. Both
Timer0 and Timer1 have secondary maximum count
the primary and secondary maximum count registers lets the timer alternate between two maximum values.

registers for variable duty cycle output. Using both

MAX. COUNT A

MAX. COUNT B

Power-save Mode

The R-Engine-D is an i
of the Am186ER redu
portable systems. In power-save mode, operation of the CPU and internal peripherals continues at a slower
clock frequency. When an interrupt occurs, it automatically returns to its normal operating frequency.

The DS1337 on the R-Engine-D has a VOFF signal routed to J1 pin 9. VOFF is controlled by the battery­backed DS1337. The VOFF signal can be programmed by software to be in tri-state or to be active

3-3

deal core module for low power consumption applications. The power-save mode
ces power consumption and heat dissipation, thereby extending battery life in

low.

Chapter 3: Hardware R-Engine-D

The DS1337 can be programmed in interrupt mode to drive the VOFF pin at 1 second, 1 minute, or 1 hour
intervals. The user can use the VOFF line to control an external switching power supply that turns the
power supply on/off. More details are available in the sample file poweroff.c in the 186\samples\ae
sub-directory.

3.5 Am186ER PIO lines

The Am186ER has 32 pins availabl
user-programmable input or output signal, if the normal shared function is not needed. A PIO line can be
configured to operate as an input or output with or without a weak pull-up or pull-down, or as an open­drain output. A pin’s behavior, either pull-up or pull-down, is pre-determined and shown in the table
below.

After power-on/reset, PIO pins default to various configurations. The initialization routine provided by
TERN libraries reconfigures some of these pins as needed for specific on-board usage, as well. These
configur

3.1.

ations, as well as the processor-internal peripheral usage configurations, are listed below in Table

PIO Function Power-On/Reset

status

P0 Timer1 in Input with pull-up J2 pin 20 Input with pull-up
P1 Timer1 out Input with pull-down J2 pin 29 or AD7852 Use as Clock f
P2 /PCS6/A2 Input with pull-up J2 pin 27 Input with pull-up
P3 /PCS5/A1 Input with pull-up U4 pin 39 SCC2692 select
P4 DT/R Normal J2 pin 38 Input with pull-up Step 2
P5 /DEN/DS Normal J2 pin 30 Input with pull-up
P6 SRDY Normal J2 pin 35 Input with external pull-up
P7 A17 Normal N/A A17
P8 A18 Normal N/A A18
P9 A19 Normal J2 pin 10 A19
P10 h pull-down th pull-down Timer0 out Input wit J2 pin 12 Input wi
P11 n h pull-up th pull-up Timer0 i Input wit J2 pin 14 Input wi
P12 h pull-up t DRQ0 Input wit J1 pin 26 Outpu
P13 DRQ1 Input with pull-up J2 pin 11 Input with pull-up
P14 /MCS0 Input with pull-up J2 pin 37 Input with pull-up
P15 /MCS1 Input with pull-up J2 pin 23 Input with pull-up
P16 /PCS0 Input with pull-up J1 pin 19 /PCS0
P17 /PCS1 Input with pull-up N/A /CS for U18 HC138
P18 /PCS2 Input with pull-up J2 pin 13 Input with pull-up
P19 /PCS3 Input with pull-up J2 pin 31 Input with pull-up
P20 SCLK Input with pull-up J2 pin 5 Input with pull-up
P21 SDATA Input with pull-up J2 pin 3 Input with pull-up
P22 SDEN0 n Input with pull-dow N/A Output
P23 SDEN1 n Input with pull-dow J2 pin 9 Input with pull-up
P24 /MCS2 Input with pull-up J2 pin 17 Input with pull-up
P25 /MCS3 Input with pull-up J2 pin 18 Input with pull-up
P26 UZI Input with pull-up J2 pin 4 Input with pull-up*
P27 TxD Input with pull-up J2 pin 28 TxD1

e as user-programmable I/O lines. Each of these pins can be used as a

R-Engine-D Pin No. R-Engine-D Initial

after ae_init();

function call

3-4

R-Engine-D Chapter 3: Hardware

PIO Function Power-On/Reset

status

P28 RxD Input with pull-up J2 pin 26 RxD1
P29 S6/CLKSEL1 Input with pull-up N/A Input with pull-up*
P30 INT4 Input with pull-up U24 pin 37 ith pull-up Input w
P31 INT2 Input with pull-up J2 pin 19 Input with pull-up

* P2 t N uring power-on or reset.

Note: 6 and P29 mus OT be forced low d

bl O pin def n aft on or reset

Ta e 3.1 I/ ault configuratio er power-

The E and PIODIRECTION. The

32 PIO lines, P0-P31, are configurable via two 16-bit registers, PIOMOD

setti

ngs are as follows:

MODE PIOMODE reg. PIODIRECTION reg. PIN FUNCTION

0 0 0 Normal operation
1 0 1 INPUT with pull-up/pull-down
2 1 0 OUTPUT
3 1 1 INPUT without pull-up/pull-down

ine-D in in :

R-Eng itialization on PIO pins ae_init() is listed below

ou rt(0xff78,0xc7bc); // PDIR1, TxD0, RxD0, TxD PI

tpo 1, RxD1, P16=PCS0, P17=PCS1=P
outport(0xff76,0x2040); // PIOM1
outport(0xff72,0xec73); // PDIR0, P12,A19,A18,A17,P
outport(0xff70,0x1040); // PIOM0, P12=LED

C function in the library re_lib can be used to in

The itialize PIO pins.

pio_init(char bit, char mode);

void

Where bit = 0-31 and mode = 0-3, see the table above.

R-Engine-D Pin No. R-Engine-D Initial

after ae_init();

function call

2=PCS6=RTC

Example: pio_init(1

tput

void pio , char

unsigned

Some of the I/O lines are used
source hat you are not
interferi

pio_init(1, 0); will set P1 as Timer1 ou

_wr(char bit dat);

pio_wr(12,1); set P12 pin high, if P12 is in output mode
pio_wr(12,0); set P12 pin low, if P12 is in output mode

int pio_rd(char port);

pio_rd (0); return 16-bit status of P0-P15, if correspond
p

io_rd (1); return 16-bit status of P16-P31, if corresponding pin is in input mode,

not found.). We suggest that you not use these lines unless you are sure t
ng with the operation of such components (i.e., if the component is not installed).

3-5

2, 2); will set P12 as output

ing pin is in input mode,

by the R-Engine-D system for on-board components (Error! Reference

Chapter 3: Hardware R-Engine-D

Signal Pin Function

P1 Timer1 output ADC clock 5MHz U12
P3 /PCS5 U4 SCC2692 UART chip select at base I/O address 0x0500
P4 /DT Step Two jumper
P7 A17
P8 P18
P17 1 /PCS /CS for U18 HC138

P20 SCLK Synchronous Clock for U14, U15, and U17
P21 SDAT Serial Interface for U14, 15, and U17
P22 SDEN0 Interface with RTC, EEPROM
/INT0 upt. J2 pin 8 U4 SCC2692 Dual UART interr
P27 J2 pin 34 TxD0
P28 J2 pin 32 RxD0
P29 J3 pin 3 Reserved for EEPROM, LED, RTC, and Watchdog timer
P30 INT4 Interrupt used by Compact Flash interface
P31 INT2 Tied to DS1337 RTC alarm

Ta .2 I/ used for

ble 3 O lines on-board components

Upper address line – Never use by application
Upper address line – Never use by application

3.6 I/O Mapped Devices

I/O Space

External I/O d
or outportb(port,dat). These functions will transfer one byte or word of data to the specified I/O address.
The external I/O space is 64K, ranging from 0x0000 to 0xffff.

The default I/O access time is 15 wait states. You may use the
the I/O wait states from 0 to 15. The system clock is 100 ns for both CPUs, while the CPU clock is 25ns
for the Am186ER and 12.5ns for the R1100. Details regarding this can be found in the Software chapter,
and in the Am186ER User’s Manual. Slower components, such as most LCD interfaces, might find the
maximum programmable wait state of 15 cycles still insufficient. Due to the high bus speed of the system,
some components need to be attached to I/O pins directly.

For details regarding the chip select unit, please see Chapte

The table below shows more information about I/O mapping.

*PCS0 may be use p l C-0, P50, P100, MM-A. d for other TERN eriphera boards, such as F

evices can use I/O mapping for access. You can access such I/O devices with inportb(port)

function void io_wait(char wait) to define

r 5 of the Am186ER User’s Manual.

I/O space Select Location Usage

0x0000-0x00ff P16 /PCS0 J1 pin 19= USER*
0x0100-0x01ff /PCS1 U18 pin 4 HC138
0x0200-0x02ff /PCS2 J2 pin 22=P18 , RTC EEPROM
0x0300-0x03ff /PCS3 J2 pin 31=P19 USER
0x0400-0x04ff /PCS4 Reserved
0x0500-0x05ff /PCS5 J2 pin 15=P3 SCC26C92
0x0600-0x06ff /PCS6 J2 pin 27 = P2 USER

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R-Engine-D Chapter 3: Hardware

N

To illustrate how to interface the R-Engine-D with external I/O boards, a simple decoding circuit for
interfacing to an 82C55 parallel I/O chip is shown in Figure 3.2.

74HC138

A5

A6

A7

/PCS0

VCC

15

14

13

12
11

10

9
7

C

/SEL20
/SEL40
/SEL60

/SEL80
/SELA0
/SELC0

/SELF0

1

A

2

B

3

C

G2A

4

G2B

5

G1

6

Y0

Y1

Y2

Y3
Y4

Y5

Y6
Y7

RST

A0
A1

/SEL20

/WR

/RD

D0-D7

Figure 3.2 Interface the R-Engine-D to external I/O devices

The function ae_init() by default initializes the /PCS0 line at base I/O address starting at 0x00. You
can read from the 82C55 with inportb(0x020) or write to the 82C55 with outportb(0x020,dat). The call to
inportb(0x020) will activate /PCS0, as well as putting the address 0x20 over the address bus. The decoder
will select the 82C55 based on address lines A5-7, and the data bus will be used to read the appropriate
data from the off-board component.

82C55

/CS

/WR

/RD

P00-P07

P10-P17

P20-P27

Programmable Peripheral Interface (82C55A)

U5 PPI (82C55) is a low-power CMOS programmable parallel interface unit for use in microcomputer
systems. It provides 24 I/O pins that may be individually programmed in two groups of 12 and used in
three major modes of operation.

In MODE 0, the two groups of 12 pins can be programmed in sets of 4 and 8 pins to be inputs or outputs.
In MODE 1, each of the two groups of 12 pins can be programmed to have 8 lines of input or output. Of
the 4 remaining pins, 3 are used for handshaking and interrupt control signals. MODE 2 is a strobed bi­directional bus configuration.

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Chapter 3: Hardware R-Engine-D

p

76 012345

GROUP 1

Port 2

(L ow e r)

Output

0

Input

1

Port 1

M ode

GROUP 2

Port 2

(Upper)

Port 0

M ode

Command

Select

Figure 3.3 Mode Select Command Word

The R-Engine-D maps U5, the 82C55/uPD71055, at base I/O address 0x1A0.

Output

0

Input

1

Mode 0

0

Mode 1

1

Output

0

Input

1

Output

0

Input

1

M ode 0

00

M ode 1

01

M ode 2

1X

mani

Bit

ulation

M ode

Select

0

1

The ports/registers are offsets of this I/O base address.

The command register = 0x1A6; Port 0 = 0x1A0; Port 1 = 0x1A2; Port 2 = 0x1A4.

The following code example will set all ports to output mode:

outportb(0x1A6,0x80); // mode 0 output, all pins

outportb(0x1A0,0x55); // Port 0, alternating high/low on pins

outportb(0x1A2,0x55); // Port 1, alternating high/low on pins

outportb(0x1A4,0x55); // Port 2, alternating high/low on pins

To set all ports to input mode:

outportb(0x1A6, 0x9b); // mode 0 input, all pins

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R-Engine-D Chapter 3: Hardware

You can read the ports with:

inportb(0x1A0); // port 0

inportb(0x1A2); // port 1

inportb(0x1A4); // port 2

This returns an 8-bit value for each port, with each bit corresponding to the appropriate line on the port.

Port 1 and port 2 of the PPI are routed directly to the J3 header. Neither port has external pull-up or pull­down resistors. When using these lines as input, their value will be floating unless driven by an external
source or pull resistor.

Port 0 is used as the input to the high voltage driver at U10. The corresponding outputs of the high voltage
driver are IO0 – IO7, which are also routed to the J3 header. If TTL level I/Os are necessary for Port 0 of
the PPI, a resistor pack can be installed in the U10 socket to generate eight additional TTL level I/Os. Port
0, I00 – I07, is tied to a pull-up resistor network, making the default output of the U10 high voltage driver
low.

Real-time Clock DS1337

The DS1337 serial real-time clock is a low-power clock/calendar with two programmable time-of-day
alarms and a programmable square-wave output. Address and data are transferred serially via a 2-wire,
bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year
information. The data at the end of the month is automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock operates in either 24-hour or 12-hour format with
AM/PM indicator.

The RTC is accessed via software drivers rtc_init() and rtc_rds(). Refer to sample code in the samples\re
directory for re_rtc.c. The sample code is identical to the RDs predecessor, the RE.

It is also possible to configure the real-time clock to raise an output line attached to an external interrupt, at
1/64 second, 1 second, 1 minute, or 1 hour intervals. This can be used in a time-driven application, or the
VOFF signal can be used to turn on/off the controller using an external switching power supply.

UART SCC2692

The dual UART (SCC26C92, Phillips, U4) is a 44-pin PLCC chip. The SCC26C92 includes two
independent full-duplex asynchronous receiver/transmitters, a quadruple buffered receiver data register, an
interrupt control mechanism, programmable data format, selectable baud rate for the receiver and
transmitter, a multi-functional and programmable 16-bit counter/timer, an on-chip crystal oscillator, and a
multi-purpose input/output including RTS and CTS mechanism.

A 3.6864 MHz external crystal is installed as the default crystal for the dual UART.

For more detailed information, refer to the SCC26C92 data sheets (Phillips Semiconductors) or on the CD
in the tern_docs\parts directory.

Sample programs for the SCC2692 can be found in the c:\tern\186\samples\re directory.

3.7 Other Devices

A number of other devices are also available on the R-Engine-D. Some of these are optional, and might not
be installed on the particular controller you are using. For a discussion regarding the software interface for
these components, please see the Software chapter.

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Chapter 3: Hardware R-Engine-D

On-board Supervisor with Watchdog Timer

The MAX691/LTC691 (U6) is a supervisor chip. With it installed, the R-Engine-D has several functions:
watchdog timer, battery backup, power-on-reset delay, power-supply monitoring, and power-failure
warning. These will significantly improve system reliability.

Watchdog Timer

The watchdog timer is activated by setting a jumper on J9 of the R-Engine-D. The watchdog timer
provides a means of verifying proper software execution. In the user's application program, calls to the
function hitwd() (a routine that toggles the P29 = WDI pin of the MAX691) should be arranged such that
the WDI pin is accessed at least once every 1.6 seconds. If the J9 jumper is on and the WDI pin is not
accessed within this time-out period, the watchdog timer pulls the WDO pin low, which asserts /RESET.
This automatic assertion of /RESET may recover the application program if something is wrong. After the
R-Engine-D is reset, the WDO remains low until a transition occurs at the WDI pin of the MAX691. When
controllers are shipped from the factory the J9 jumper is off, which disables the watchdog timer.

The Am186ER has an internal watchdog timer. This is disabled by default with ae_init().

Watchdog jumper

shown enabled at

J9 2-pin header

Figure 3.4 Location of watchdog timer enable jumper

Battery Backup Protection

The backup battery protection protects data stored in the SRAM and RTC. The battery-switch-over circuit
compares VCC to VBAT (+3 V lithium battery positive pin), and connects whichever is higher to the
VRAM (power for SRAM and RTC). Thus, the SRAM and the real-time clock DS1337 are backed up. In
normal use, the lithium battery should last about 3-5 years without external power being supplied. When
the external power is on, the battery-switch-over circuit will select the VCC to connect to the VRAM.

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R-Engine-D Chapter 3: Hardware

EEPROM

A serial EEPROM of 512 bytes (24C04) is be installed in U7. The R-Engine-D uses the P22=SCL (serial
clock) and P29=SDA (serial data) to interface with the EEPROM. The EEPROM can be used to store
important data such as a node address, calibration coefficients, and configuration codes. It typically has
1,000,000 erase/write cycles. The data retention is more than 40 years. EEPROM can be read and written
by simply calling the functions ee_rd() and ee_wr().

A range of lower addresses in the EEPROM is reserved for TERN use, 0x00 – 0x1F. The addresses 0x20
to 0x1FF are for user application.

ADS8344, 16-bit ADC

The ADS8344 is an 8-channel, 16-bit, sampling ADC with synchronous serial interface. In single channel
operation a 25KHz sampling rate can be achieved. The ADC can accept input voltages in the range of
0-5 volts. All eight input channels are routed to the J4 pin header to easy access to the device. The R­Engine-D employs a variety of on-board signals to interface the ADC. It uses 2 output lines from the
SCC26C92 to drive the DataIn (DIN) line and the chip select line (/CS). It also uses one of the inputs of
the SCC26C92 as the Busy (BSY) signal. In addition, the synchronous serial port on the Am186ER is used
to clock (SCLK) the ADC and read the ADC conversion results using the SDAT line. TERN provides
three software drivers for this ADC. This de-coupling of instructions to drive the ADC achieves a greater
sampling rate when in single channel mode, as you do not have to wait for the on-chip multiplexer to settle,
or delay associated with other control logic on the ADC. The following table summarizes the signals to and
from the ADC. Please refer to the sample code in the 186\samples\rd directory (rd_ad16.c)

SCLK Serial clock from Am186ER

OP3 Active low chip select. Output from SC26C92. If low, the ADC will have output on SDAT.

OP4 DIN. Serial data in. Output from SC26C92

IP6 BSY. Low while control bytes are being read, and during conversion.

SDAT Serial data out. Input to SC26C92.

SHD Active low power down. Tied to VCC, never in power down.

COM Tied to Ground

REF Tied to VCC. Sets valid analog input to 0-5V

Dual 12-bit DAC (DAC7612U)

The DAC7612 is a dual, 12-bit digital-to-analog converter with guaranteed 12-bit monotonicity
performance over the industrial temperature range. It requires a single +5V supply and contains an input
shift register, latch, 2.435V reference, a dual DAC, and high speed rail-to-rail amplifiers. For a full-scale
step, each output will settle to 1LSB within 7µs.

The DAC7612 uses a three wire serial interface to the CPU. The CPU on the R-Engine-D uses two output
lines from the SCC26C92 and two lines from the Am186ER to drive the serial interface (Data In, Clock,
Chip select and Latch Data) in an 8-lead SOIC package. The R-Engine-D offers up to two DAC7612,
providing a possible 4 12-bit serial DAC channels. The DAC7612 outputs can support a capacitive load of
500pF.

The DACs are located in the U15 and U17 positions with the analog outputs routed to the J3 pin header,
pins 47-50. See the schematic at the end of this technical manual.

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Chapter 3: Hardware R-Engine-D

Refer to data sheet in the tern_docs/parts directory of the TERN CD and to sample code in the
tern/186/samples/rd (rd_da.c) directory for additional information.

AD7852, 300KHz, 12-bit ADC

One AD7852 chip can be installed on the RD. The AD7852 is sampling parallel 12-bit A/D converter that
draws only 55 mW from a single 5V supply. This device includes 8 channels with sample-and-hold,
precision 2.5V internal reference, switched capacitor successive-approximation A/D, and needs an external
clock.

The input range of the AD7852 is 0-5V. Maximum DC specs include ±2.0 LSB INL and 12-bit no missing
codes over temperature. The ADC has a 12-bit data parallel output port that directly interfaces to the full
12-bit data bus D15-D4 for maximum data transfer rate.

The AD7852 requires 16 ADC clocks (or 3.2 µs) conversion time to complete one conversion, based on a 5
MHz ADC clock. The busy signal has an 3.2 µs low period indicating that conversion is in progress. In
order to achieve the 300 KHz sample rate, the AE86 must use polling method, not interrupt operation, to
acquire data. A sample program rd_ad12.c can be found in the c:\tern\186\samples\rd directory

DA7625, 200KHz 12-bit DAC

The DA7625 is a parallel 12-bit D/A converter. This device includes 4 voltage output channels with an
output range of 0-2.5V. It accepts 12-bit parallel input data and has double-buffered DAC input logic.

The R-Engine-D uses pins D15 to D4 to directly interface to the DAC’s full 12-bit data bus for maximum
data transfer rate.

The DA7625 has an average settling time of 5 µs, with a maximum settling time of 10µs. Additional
information is available in the tern_docs\parts directory of the CD. A sample program rd_da.c may be
found in the c:\tern\186\samples\rd directory.

Compact Flash Interface

By utilizing the compact flash interface on the RD, users can easily add widely used 50-pin CF standard
mass data storage cards to their embedded application via RS232, TTL I2C, or parallel interface. TERN
software supports Linear Block Address mode, 16-bit FAT flash file system, RS-232, TTL I2C or parallel
communication. Users can write a file to the CompactFlash card or read a file from the CompactFlash card.
Users can also transfer the file to a PC via the PCMCIA port.

This allows the user to log huge amounts of data from external sources. Files can then be accessed via
compact flash reader on a PC.

The tern\186\samples\rd directory includes sample code, rd_cf.c, to show reads and writes of raw data by
sector. In addition, tern\186\samples\fn\fs_cmds1.c is a simple file system demo with serial port based
user interface. Refer to rd.ide which has the demo built and ready for download.

Ethernet

The Ethernet LAN Controller on the R-Engine-D is the CS8900 from Crystal Semiconductor Corporation
(512-445-7222). The CS8900 includes on-chip RAM and 10BASE-T transmit and receive filters. The
CS8900 directly interfaces to the TERN controller’s data bus, providing a high-speed, full duplex
operation. The RD interface to the Ethernet is via a standard RJ45 8-pin connector (J5). The CS8900 offers
a broad range of performance features and configuration options. Its unique PacketPage architecture
automatically adapts to changing network traffic patterns and available system resources. The CS8900-

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R-Engine-D Chapter 3: Hardware

based RD can increase system efficiency and minimize CPU overhead in a 10BASE-T network. The RD
with CS8900 provides a true full-duplex Ethernet solution, incorporating all of the analog and digital
circuitry needed for a complete C/C++ programmable Ethernet node controller.

High-Voltage, High-Current Drivers

The ULN2003 has high voltage, high current Darlington transistor arrays, consisting of seven silicon NPN
Darlington pairs on a common monolithic substrate. All channels feature open-collector outputs for sinking
350 mA at 50V, and integral protection diodes for driving inductive loads. Peak inrush currents of up to
500 mA sinking are allowed. These outputs may be paralleled to achieve high-load capability, although
each driver has a maximum continuous collector current rating of 350 mA at 50V. The maximum power
dissipation allowed is 2.20 W per chip at 25 degrees C (°C).. ULN2003 is a sinking driver, not a
sourcing driver. An example of typical application wiring is shown in Figure 1.1.

O1

ULN2003 TinyDrive

Solenoid

K +12V

GND/SUB

+12V

Power Supply

GND/SUB

Figure 1.1 Drive inductive load with high voltage/current drivers.

By default the high voltage drivers are configured to sinking drivers, not sourcing, and for output. This
requires the common substrate be tied to GND and the K voltage diodes are tied to the highest voltage in
the system when driving inductive loads. The U29 socket is configured for sinking driver output only. The
common substrate is tied to ground by design, and the user can provide external voltage on K (routed to
J3.25) for inductive loads. For non-inductive loads K can be open (floating). The outputs of the U29
ULN2003A are routed to J3.27-32 and are driven by port 2 of the PPI (U5).

There are also two sockets at U10 and U30. By default they are sinking drivers for output. For the
SINKING driver configuration (default) this means that the common substrate are connected to the PCB
signal names VS and VS1 (do not be confused by the signal names on the schematic). These must be
connected to ground at the J3 header, thus J3.14 = J3.16 and J3.2 = J3.4. If inductive loads are being
driven, the user can provide external voltage on GK and GK1.

The U10 socket:

(1) Can be sourcing output

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Chapter 3: Hardware R-Engine-D

a. Install UDS2982 in U10. Pin 1 of device = pin 1 of socket
b. Connect GK1 to GND => J3.1=J3.2
c. VS1 to external voltage if inductive load, otherwise open.

(2) Can be input with sinking driver

a. Install ULN2003A so that pin 1 of device is in pin 11 of socket.
b. Connect IO0 to GND => J3.12 = J3.14
c. Read Port 0 of PPI, see rd_hv_in.c

The U30 socket can be re-configured to sourcing output only, no input with this socket

(1) Install UDS2982 in U30. Pin 1 of device = pin 1 of socket
(2) Connect GK = GND => J313 = J3.14
(3) VS to external voltage if inductive load

Refer to rd_hv.c and rd_hv_in.c for implementation. Both are included in the rd.ide project.

3.8 Headers and Connectors

The diagram below shows the location of pin 1 of each header on the RD. Most signals on J1 and J2
header are routed directory to the CPU with no buffer protection. This makes the CPU (including SRAM,
Flash, and other devices tied to the A/D bus) vulnerable to damage from out of range voltages. The user is
therefore responsible for ensuring that out of range voltages are not applied to sensitive lines.

These signals are +3.3V signals, but are +5V tolerant. Any
voltages above +5V will certainly damage the board.

Refer to the schematic at the end of this technical manual for complete signal definitions for all headers and
connectors.

Expansion Headers J1 and J2

There are two 20x2 0.1 spacing headers for R-Engine-D expansion. Most signals are directly routed to the
Am186ER processor.

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R-Engine-D Chapter 3:

Hardware

J2

J3

H2

H3

H4

J1

J4

Figure 3.5 Pin 1 locations for RD headers

GND 40 39 VCC
P4 38 37 P14
IP0 36 35 P6
TxD0 34 33
RxD0 32 31 P19
P5 30 29 P1
TxDA 28 27 P2
RxDA 26 25
IP1 24 23 P15
IP2 22 21 INT3
P0 20 19 INT2
P25 18 17 P24
IP3 16 15 IP4
P11 14 13 P18
P10 12 11 P13
A19 10 9 P23
/INT0 8 7 NMI
/INT1 6 5 SCLK
P26 4 3 SDAT
GND 2 1 OP0

J2 Signal

VCC 1 2 GND
OP1 3 4 CLK
RxDB 5 6 GND
TxDB 7 8 D0
VOFF 9 10 D1
/BHE 11 12 D2
D15 13 14 D3
/RST 15 16 D4
RST 17 18 D5
P16 19 20 D6
D14 21 22 D7
D13 23 24 GND
/HB 25 26 P12
D12 27 28 A7
/WR 29 30 A6
/RD 31 32 A5
D11 33 34 A4
D10 35 36 A3
D9 37 38 A2
D8 39 40 A1

Table 3.3 Signals for J2 and J1, 20x2 expansion ports

J1 Signal

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R-Engine-D Chapter 4: Software

Chapter 4: Software

Please refer to the Technical Manual of the “C/C++ Development Kit for TERN 16-bit Embedded
Microcontrollers” for details on debugging and programming tools.

Guidelines, awareness, and problems in an interrupt driven environment

Although the C/C++ Development Kit provides a simple, low cost solution to application engineers, some
guidelines must be followed. If they are not followed, you may experience system crashes, PC hang-ups,
and other problems.

The debugging of interrupt handlers with the Remote Debugger can be a challenge. It is possible to debug
an interrupt handler, but there is a risk of experiencing problems. Most problems occur in multi-interrupt­driven situations. Because the remote kernel running on the controller is interrupt-driven, it demands
interrupt services from the CPU. If an application program enables interrupt and occupies the interrupt
controller for longer than the remote debugger can accept, the debugger will time-out. As a result, your PC
may hang-up. In extreme cases, a power reset may be required to restart your PC.

For your reference, be aware that our system is remote kernel interrupt-driven for debugging.

The run-time environment on TERN controllers consists of an I/O address space and a memory address
space. I/O address space ranges from 0x0000 to 0xffff, or 64 KB. Memory address space ranges from
0x00000 to 0xfffff in real-mode, or 1 MB. These are accessed differently, and not all addresses can be
translated and handled correctly by hardware. I/O and memory mappings are done in software to define
how translations are implemented by the hardware. Implicit accesses to I/O and memory address space
occur throughout your program from TERN libraries as well as simple memory accesses to either code or
global and stack data. You can, however, explicitly access any address in I/O or memory space, and you
will probably need to do so in order to access processor registers and on-board peripheral components
(which often reside in I/O space) or non-mapped memory.

This is done with four different sets of similar functions, described below.

poke/pokeb
Arguments: unsigned int segment, unsigned int offset, unsigned int/unsigned char data
Return value: none

These standard C functions are used to place specified data at any memory space location. The segment
argument is left shifted by four and added to the offset argument to indicate the 20-bit address within
memory space. poke is used for writing 16 bits at a time, and pokeb is used for writing 8 bits.

The process of placing data into memory space means that the appropriate address and data are placed on
the address and data-bus, and any memory-space mappings in place for this particular range of memory
will be used to activate appropriate chip-select lines and the corresponding hardware component
responsible for handling this data.

peek/peekb
Arguments: unsigned int segment, unsigned int offset
Return value: unsigned int/unsigned char data

These functions retrieve the data for a specified address in memory space. Once again, the segment
address is shifted left by four bits and added to the offset to find the 20-bit address. This address is then
output over the address bus, and the hardware component mapped to that address should return either an

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Chapter 4: Software R-Engine-D

8-bit or 16-bit value over the data bus. If there is no component mapped to that address, this function will
return random garbage values every time you try to peek into that address.

outport/outportb
Arguments: unsigned int address, unsigned int/unsigned char data
Return value: none

This function is used to place the data into the appropriate address in I/O space. It is used most often
when working with processor registers that are mapped into I/O space and must be accessed using either
one of these functions. This is also the function used in most cases when dealing with user-configured
peripheral components.

When dealing with processor registers, be sure to use the correct function. Use outport if you are dealing
with a 16-bit register.

inport/inportb
Arguments: unsigned int address
Return value: unsigned int/unsigned char data

This function can be used to retrieve data from components in I/O space. You will find that most hardware
options added to TERN controllers are mapped into I/O space, since memory space is valuable and is
reserved for uses related to the code and data. Using I/O mappings, the address is output over the address
bus, and the returned 16 or 8-bit value is the return value.

For a further discussion of I/O and memory mappings, please refer to the Hardware chapter of this
technical manual.

4.1 Programming Overview

The ACTF loader in the RD 512KB Flash will perform the system initialization and prepare for new
application code download or immediately run the pre-loaded code. A remote debugger kernel can be
loaded into the Flash located starting 0xfa000. Debugging at baud rate of 115,200 (re40_115.HEX for the
Am186ER and re80_115.HEX for the R1100) are available. A loader file “l_debug.hex” and both
debugger files re40_115.hex and re80_115.HEX, are included in the EV-P/DV-P disk under the
c:\tern\186\rom\re\ directory.

A functional diagram of the ACTF (embedded in the RD) is shown below:

Power on or Reset

STEP2 Jumper on ?

J2 pin 38=P4=GND ?

Yes

Read EE for the jump address CS:IP

RUN the program starting at the CS:IP

No

SEND out MENU over SER0 at 19200, N, 8, 1 to

Hyperterminal of Windows95/98

Text command or download new codes

Process Commands

See ACTF-kit and Functions for detail

4-2

R-Engine-D Chapter 4: Software

S

The C function prototypes supporting Am186ER hardware can be found in header file “ae.h”, in the
c:\tern\186\include directory.

Sample programs can be found in the c:\tern\186\samples\ae and
c:\tern\186\samples\re and c:\tern\186\samples\rd directories.

4.1.1 Steps for RE based product development

Preparation for Debugging

• Connect RD to PC via RS-232 link, 19,200, 8, N, 1

• Power on RD without STEP 2 jumper installed

• ACTF menu should be sent to PC terminal

• Use “D” command to download “l_debug.HEX” in SRAM

• “G04000” to run “l_debug.”

• Download “re40_115.HEX” to Flash starting at 0xfa000

• “GFA000” to setup EE and run debug kernel

• Install the STEP2 jumper (J2.38-40)

• Power-on or reset RE, Ready for Remote debugger

STEP 1: Debugging

• Start ParadigmC++, run“RE_test.ide”

• Download code to target SRAM.

• Edit, compile, link, locate, download, and remote-debug

TEP 2:

STEP 3: DV-P Kit

There is no ROM socket on the RD. The user’s application program must reside in SRAM for debugging
in STEP1, reside in battery-backed SRAM for the standalone field test in STEP2, and finally be
programmed into Flash for a complete product.

Standalone Field Test

8”G08000” setup EE Jump Address, points to application code

resides in battery backed SRAM

8Install STEP2 jumper, then power on

8Application program running in battery-backed SRAM

(Battery lasts 3-5 years under normal conditions.)

Production

• Generate application HEX file with DV-P

• ACTF “D” to download “L_29F40R.HEX” into SRAM

• Download application HEX file into FLASH

• Modify EE jump address to 0x80000

• Set STEP2 jumper

The on-board Flash 29F400BT has 256K words of 16-bits each. It is divided into 11 sectors, comprised of
one 16KB, two 8KB, one 32KB, and seven 64KB sectors. The top one 16KB sector is pre-loaded with
ACTF boot strip, the one 8KB sector starting 0xfa000 is for loading remote debugger kernel, and the reset
all sectors are free for application use.

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The top 16KB ACTF boot strip is protected.

Two utility HEX files, “l_debug.HEX” and “L_29F40R.HEX”, are designed for downloading into SRAM
starting at 0x04000 with ACTF-PC-HyperTerminal. Use the “D” command to download, and use the “G”
command to run.

“L_DEBUG.HEX” will erase the 8KB sector and load a “re40_115.HEX” or “re80_115.HEX”.
“L_29F40R.HEX” will erase the remaining sectors for downloading your application HEX file.

Flash

SRAM

ACTF
Utility

Debug
Kernel

re40_115

0xFFFFF

0xFC000

0xFA000

0x80000

0x20000

For production, the user must produce an ACTF-downloadable HEX file for the application, based on the
DV Kit. The application HEX file can be loaded into the on-board Flash starting address at 0x80000.

The on-board EE must be modified with a “G80000” command while in the ACTF-PC-HyperTerminal
Environment.

The “STEP2” jumper (J2 pins 38-40) must be installed for every production-version board.

Step 1 settings

In order to correctly download a program in STEP1 with Paradigm C/C++, the RD must meet these
requirements:

1) re40_115.hex must be pre-loaded into Flash starting address 0xfa000.

2) The SRAM installed must be large enough to hold your program.

For a 128K SRAM, the physical address is 0x00000-0x01ffff

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For a 512K SRAM, the physical address is 0x00000-0x07ffff

3) The on-board EE must have a correct jump address for the re40_115.HEX with starting address of
0xfa000.

4) The STEP2 jumper must be installed on J2 pins 38-40.

4.2 RE.LIB

RE.LIB is a C library for basic R-Engine-D operations. It includes the following modules: AE.OBJ,
SER0.OBJ, SER1R.OBJ, and AEEE.OBJ. You need to link RE.LIB in your applications and include the
corresponding header files in your source code. The following is a list of the header files:

Include-file name Description

AE.H PPI, timer/counter, ADC, DAC, RTC, Watchdog
SER0.H Internal serial port 0
SER1R.H External UART SCC26C92
AEEE.H on-board EEPROM

4.3 Functions in AE.OBJ

4.3.1 R-Engine-D Initialization

ae_init

This function should be called at the beginning of every program running on R-Engine-D core controllers.
It provides default initialization and configuration of the various I/O pins, interrupt vectors, sets up
expanded DOS I/O, and provides other processor-specific updates needed at the beginning of every
program.

There are certain default pin modes and interrupt settings you might wish to change. With that in mind, the
basic effects of ae_init are described below. For details regarding register use, you will want to refer to the
AMD Am186ER Microcontroller User’s manual.

• Initialize the upper chip select to support the default ROM. The CPU registers are configured such
that:

− Address space for the ROM is from 0x80000-0xfffff (to map MemCard I/O window)

− 512K ROM Block size operation.

− Three wait state operation (allowing it to support up to 120 ns ROMs). With 70 ns ROMs, this

can actually be set to zero wait state if you require increased performance (at a risk of stability
in noisy environments). For details, see the UMCS (Upper Memory Chip Select Register)
reference in the processor User’s manual.

outport(0xffa0, 0x80bf); // UMCS, 512K ROM, 0x80000-0xfffff

• Initialize LCS (Lower Chip Select) for use with the SRAM. It is configured so that:

− Address space starts 0x00000, with a maximum of 512K RAM.

− Three wait state operation. Reducing this value can improve performance.

− Disables PSRAM, and disables need for external ready.

outport(0xffa2, 0x7fbf); // LMCS, base Mem address 0x0000

• Initialize MMCS and MPCS so that MCS0 and PCS0-PCS6 (except for PCS4) are configured so:

− MCS0 is mapped also to a 256K window at 0x80000. If used with MemCard, this

chip select line is used for the I/O window.

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− Sets up PCS5-6 lines as chip-select lines, with three wait state operation.

outport(0xffa8, 0xa0bf); // s8, 3 wait states
outport(0xffa6, 0x81ff); // CS0MSKH

• Initialize PACS so that PCS0-PCS3 are configured so that:

− Sets up PCS0-3 lines as chip-select lines, with fifteen wait state operation.

− The chip select lines starts at I/O address 0x0000, with each successive chip select line

addressed 0x100 higher in I/O space.

outport(0xffa4, 0x007f); // CS0MSKL, 512K, enable CS0 for RAM

• Configure the two PIO ports for default operation. All pins are set up as default input, except for
P29 (used for driving the LED), and peripheral function pins for SER0, as well as chip selects for
the PPI.

outport(0xff78,0xe73c); // PDIR1, TxD0, RxD0, TxD1, RxD1,

// P16=PCS0, P17=PCS1=PPI
outport(0xff76,0x0000); // PIOM1
outport(0xff72,0xec7b); // PDIR0, P12,A19,A18,A17,P2=PCS6=RTC
outport(0xff70,0x1000); // PIOM0, P12=LED

• Configure the PPI 82C55 to all inputs. You can reset these to inputs.

outportb(0x0103,0x9a); // all pins are input, I20-23 output
outportb(0x0100,0);
outportb(0x0101,0);
outportb(0x0102,0x01); // I20 high

The chip select lines are set to 15 wait states, by default. This makes it possible to interface with many
slower external peripheral components. If you require faster I/O access, you can modify this number down
as needed. Some TERN components, such as the Real-Time-Clock, might fail if the wait state is decreased
too dramatically. A function is provided for this purpose.

void io_wait
Arguments: char wait
Return value: none.

This function sets the current wait state depending on the argument wait.

wait=0, wait states = 0, I/O enable for 100 ns
wait=1, wait states = 1, I/O enable for 100+25 ns
wait=2, wait states = 2, I/O enable for 100+50 ns
wait=3, wait states = 3, I/O enable for 100+75 ns
wait=4, wait states = 5, I/O enable for 100+125 ns
wait=5, wait states = 7, I/O enable for 100+175 ns
wait=6, wait states = 9, I/O enable for 100+225 ns
wait=7, wait states = 15, I/O enable for 100+375 ns

4.3.2 External Interrupt Initialization

There are up to six external interrupt sources on the R-Engine-D, consisting of five maskable interrupt pins
(INT4-INT0) and one non-maskable interrupt (NMI). There are also an additional eight internal interrupt
sources not connected to the external pins, consisting of three timers, two DMA channels, both
asynchronous serial ports, and the NMI from the watchdog timer. For a detailed discussion involving the
ICUs, the user should refer to Chapter 7 of the AMD Am186ER Microcontroller User’s Manual. Or the
R1100 user’s manual, both available on the CD under the amd_docs directory. (Remember, DMA

channels to and from the serial port not available on the R1100.)

TERN provides functions to enable/disable all of the 6 external interrupts. The user can call any of the
interrupt init functions listed below for this purpose. The first argument indicates whether the particular

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R-Engine-D Chapter 4: Software

interrupt should be enabled, and the second is a function pointer to an appropriate interrupt service routine
that should be used to handle the interrupt. The TERN libraries will set up the interrupt vectors correctly
for the specified external interrupt line.

At the end of interrupt handlers, the appropriate in-service bit for the IR signal currently being handled
must be cleared. This can be done using the Nonspecific EOI command. At initialization time, interrupt
priority was placed in Fully Nested mode. This means the current highest priority interrupt will be handled
first, and a higher priority interrupt will interrupt any current interrupt handlers. So, if the user chooses to
clear the in-service bit for the interrupt currently being handled, the interrupt service routine just needs to
issue the nonspecific EOI command to clear the current highest priority IR.

To send the nonspecific EOI command, you need to write the EOI register word with 0x8000.

outport(0xff22, 0x8000);

void intx_init
Arguments: unsigned char i, void interrupt far(* intx_isr) () )
Return value: none

These functions can be used to initialize any one of the external interrupt channels (for pin locations and
other physical hardware details, see the Hardware chapter). The first argument i indicates whether this
particular interrupt should be enabled or disabled. The second argument is a function pointer, which will
act as the interrupt service routine. The overhead on the interrupt service routine, when executed, is about
20 µs.

By default, the interrupts are all disabled after initialization. To disable them again, you can repeat the call
but pass in 0 as the first argument.

The NMI (Non-Maskable Interrupt) is special in that it can not be masked (disabled). The default ISR will
return on interrupt.

void int0_init( unsigned char i, void interrupt far(* int0_isr)() );
void int1_init( unsigned char i, void interrupt far(* int1_isr)() );
void int2_init( unsigned char i, void interrupt far(* int2_isr)() );
void int3_init( unsigned char i, void interrupt far(* int3_isr)() );
void int4_init( unsigned char i, void interrupt far(* int4_isr)() );
void nmi_init(void interrupt far (* nmi_isr)());

4.3.3 I/O Initialization

Two ports of 16 I/O pins each are available on the R-Engine-D. Hardware details regarding these PIO lines
can be found in the Hardware chapter.

Several functions are provided for access to the PIO lines. At the beginning of any application where you
choose to use the PIO pins as input/output, you will probably need to initialize these pins in one of the four
available modes. Before selecting pins for this purpose, make sure that the peripheral mode operation of
the pin is not needed for a different use within the same application.

You should also confirm the PIO usage that is described above within ae_init(). During initialization,
several lines are reserved for TERN usage and you should understand that these are not available for your
application. There are several PIO lines that are used for other on-board purposes. These are all described
in some detail in the Hardware chapter of this technical manual. For a detailed discussion toward the I/O
ports, please refer to Chapter 14 of the AMD Am186ER User’s Manual.

Please see the sample program ae_pio.c in tern\186\samples\ae. You will also find that these
functions are used throughout TERN sample files, as most applications do find it necessary to re-configure
the PIO lines.

The function pio_wr and pio_rd can be quite slow when accessing the PIO pins. Depending on the pin
being used, it might require from 5-10 us. The maximum efficiency you can get from the PIO pins occur if

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you instead modify the PIO registers directly with an outport instruction Performance in this case will be
around 1-2 us to toggle any pin.

The data register is 0xff74 for PIO port 0, and 0xff7a for PIO port 1.

void pio_init
Arguments: char bit, char mode
Return value: none

bit refers to any one of the 32 PIO lines, 0-31.

mode refers to one of four modes of operation.

• 0, normal operation

• 1, input with pullup/down

• 2, output

• 3, input without pull

unsigned int pio_rd:
Arguments: char port
Return value: byte indicating PIO status

Each bit of the returned 16-bit value indicates the current I/O value for the PIO pins in the selected port.

void pio_wr:
Arguments: char bit, char dat
Return value: none

Writes the passed in dat value (either 1/0) to the selected PIO.

4.3.4 Timer Units

The three timers present on the R-Engine-D can be used for a variety of applications. All three timers run
at ¼ of the processor clock rate, which determines the maximum resolution that can be obtained. Be aware
that if you enter power save mode, the timers will operate at a reduced speed as well.

These timers are controlled and configured through a mode register that is specified using the software
interfaces. The mode register is described in detail in chapter 10 of the AMD AM186ER User’s Manual.

The timers can be used to time execution of your user-defined code by reading the timer values before and
after execution of any piece of code. For a sample file demonstrating this application, see the sample file
timer.c in the directory tern\186\samples\ae.

Two of the timers, Timer0 and Timer1 can be used to do pulse-width modulation with a variable duty
cycle. These timers contain two max counters, where the output is high until the counter counts up to
maxcount A before switching and counting up to maxcount B.

U12 AD7852 uses Timer1 output (P1=J2.29) as ADC clock, up to 5MHz.

It is also possible to use the output of Timer2 to pre-scale one of the other timers, since 16-bit resolution at
the maximum clock rate specified gives you only 150 Hz. Only by using Timer2 can you slow this down
even further. The sample files timer02.c and timer12.c, located in tern\186\samples\ae, demonstrate this.

The specific behavior that you might want to implement is described in detail in chapter 10 of the AMD
AM186ER User’s Manual.

void t0_init
void t1_init

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Arguments: int tm, int ta, int tb, void interrupt far(*t_isr)()
Return values: none

Both of these timers have two maximum counters (MAXCOUNTA/B) available. These can all be specified
using ta and tb. The argument tm is the value that you wish placed into the T0CON/T1CON mode
registers for configuring the two timers.

The interrupt service routine t_isr specified here is called whenever the full count is reached, with other
behavior possible depending on the value specified for the control register.

void t2_init
Arguments: int tm, int ta, void interrupt far(*t_isr)()
Return values: none.

Timer2 behaves like the other timers, except it only has one max counter available.

4.3.5 Analog-to-Digital Conversion

Parallel ADC AD7852

The high-speed AD7852 ADC unit (U12) is mapped into I/O space starting at 0x0140. To start a ADC
conversion on channel ??, an I/O write, outportb(0x0140+??,0); will start a new ADC conversion on the
ADC channel ??. The ADC busy signal is routed to IP5 of the SCC26C92. It goes low for 16 ADC clocks
indicating busy. A 16-bit I/O read, inport(0x0140); will return the previous ADC conversion result, with
only upper 12-bit data D15-D4 valid. A sample program rd_ad12.c demonstrating the use of the AD7852
is included in tern\186\samples\rd. This sample code is already included in the rd.ide project in
the tern\186 directory.

Serial ADC ADS8344

The ADS8344 ADC unit (U14) provides 11 channels of 0-5V analog inputs. For details regarding the
hardware configuration, see the Hardware chapter.

To increase sampling speed on the 16-bit ADC, the necessary operations to read channels have been de­coupled into three user-defined functions, instead of one function that does everything. This de-coupling
allows for the by-passing of propagation delays of internal control logic, multiplexers, etc.

The following functions will drive the 16-bit ADC. Maximum speed recorded is about 25 KHz, over two
times faster than its earlier 12-bit predecessor. The order of functions given here should be followed in
actual implementation.

unsigned char single_con_byte ( char ch);

unsigned int ad16( unsigned char k );

unsigned int format_data( unsigned int ad);

For a sample file demonstrating the use of the ADC, please see rd_ad16.c in tern\186\samples\rd.

This sample is also included in the rd.ide test project in the tern\186 directory.

4.3.6 Digital-to-Analog Conversion

Parallel DAC7625

The high-speed DAC DA7625 (U11) is mapped in 0x160 – 0x166.

Use outport(0x0x160, dac); to write upper 12-bit D15-D4 data into DAC channel 1, J3 pin 45

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Use outport(0x0602, dac); to write upper 12-bit D15-D4 data into DAC channel 2, J3 pin 46

Use outport(0x0604, dac); to write upper 12-bit D15-D4 data into DAC channel 3, J3 pin 43

Use outport(0x0606, dac); to write upper 12-bit D15-D4 data into DAC channel 4, J3 pin 44

Details regarding hardware, such as pin-outs and performance specifications, can be found in the Hardware
chapter.

A sample program demonstrating the DAC can be found in rd_da.c in the directory
tern\186\samples\rd.

Serial DAC DAC7612

Two DAC7612 chips are available on the R-Engine-D in positions U15 and U17. The chips offer two
channels, A and B, for digital-to-analog conversion. Details regarding hardware, such as pin-outs and
performance specifications, can be found in the Hardware chapter.

A sample program demonstrating the DAC can be found in rd_da.c in the directory
tern\186\samples\rd.

void ra_da1
Arguments: int dac
Return value: none

This function drives the DAC at position U15, outputs are VA and VB

The argument dac contains two pieces of information, the value to be converted and the channel to output
it on. The argument dac must be constructed in the following format:

dac = 0x2000 | (0x0FFF & dac); // channel VA, J4.16

dac = 0x3000 | (0x0FFF & dac); // channel VB, J4.18

These argument values should range from 0-4095, with units of millivolts. This makes it possible to drive
a maximum of 4.906 volts to each channel.

void ra_da2
Arguments: int dac
Return value: none

This function drives the DAC at position U17, outputs are VC and VD

The argument dac contains two pieces of information, the value to be converted and the channel to output
it on. The argument dac must be constructed in the following format:

dac = 0x2000 | (0x0FFF & dac); // channel VC, J4.22

dac = 0x3000 | (0x0FFF & dac); // channel VD, J4.24

These argument values should range from 0-4095, with units of millivolts. This makes it possible to drive
a maximum of 4.905 volts to each channel.

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4.3.7 Other library functions

On-board supervisor MAX691 or LTC691

The watchdog timer offered by the MAX691 or LTC691 offers an excellent way to monitor improper
program execution. If the watchdog timer (J9) jumper is set, the function hitwd() must be called every 1.6
seconds of program execution. If this is not executed because of a run-time error, such as an infinite loop
or stalled interrupt service routine, a hardware reset will occur.

void hitwd
Arguments: none
Return value: none

Resets the supervisor timer for another 1.6 seconds.

void led
Arguments: int ledd
Return value: none

Turns the on-board LED on or off according to the value of ledd.

Real-Time Clock

The real-time clock can be used to keep track of real time. Backed up by a lithium-coin battery, the real
time clock can be accessed and programmed using two interface functions.

There is a common data structure used to access and use both interfaces.

typedef struct{
unsigned char sec1; One second digit.
unsigned char sec10; Ten second digit.
unsigned char min1; One minute digit.
unsigned char min10; Ten minute digit.
unsigned char hour1; One hour digit.
unsigned char hour10; Ten hour digit.
unsigned char day1; One day digit.
unsigned char day10; Ten day digit.
unsigned char mon1; One month digit.
unsigned char mon10; Ten month digit.
unsigned char year1; One year digit.
unsigned char year10; Ten year digit.
unsigned char wk; Day of the week.
} TIM;

int rtc_rd
Arguments: TIM *r
Return value: int error_code

This function places the current value of the real time clock within the argument r structure. The structure
should be allocated by the user. This function returns 0 on success and returns 1 in case of error, such as
the clock failing to respond.

int rtc_rds
Arguments: char* realTime
Return value: int error_code

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This function places a string of the current value of the real time clock in the char* realTime.
The text string has a format of “year1000 year100 year10 year1 month10 month1 day10 day1 hour10
hour1 min10 min1 second10 second1”. For example” 19991220081020” presents year1999, december,
20th, eight clock 10 minutes, and 20 second.
This function returns 0 on success and returns 1 in case of error, such as the clock failing to respond.

Void rtc_init
Arguments: char* t
Return value: none

This function is used to initialize and set a value into the real-time clock. The argument t should be a null­terminated byte array that contains the new time value to be used.

The byte array should correspond to { weekday, year10, year1, month10, month1, day10, day1, hour10,
hour1, minute10, minute1, second10, second1, 0 }.

If, for example, the time to be initialized into the real time clock is June 5, 1998, Friday, 13:55:30, the byte
array would be initialized to:

unsigned char t[14] = { 5, 9, 8, 0, 6, 0, 5, 1, 3, 5, 5, 3, 0 };

Delay

In many applications it becomes useful to pause before executing any further code. There are functions
provided to make this process easy. For applications that require precision timing, you should use
hardware timers provided on-board for this purpose.

void delay0
Arguments: unsigned int t
Return value: none

This function is just a simple software loop. The actual time that it waits depends on processor speed as
well as interrupt latency. The code is functionally identical to:

While(t) { t--; }

Passing in a t value of 600 causes a delay of approximately 1 ms.

void delay_ms
Arguments: unsigned int
Return value: none

This function is similar to delay0, but the passed in argument is in units of milliseconds instead of loop
iterations. Again, this function is highly dependent upon the processor speed.

unsigned int crc16
Arguments: unsigned char *wptr, unsigned int count
Return value: unsigned int value

This function returns a simple 16-bit CRC on a byte-array of count size pointed to by wptr.

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void ae_reset
Arguments: none
Return value: none

This function is similar to a hardware reset, and can be used if your program needs to re-start the board for
any reason. Depending on the current hardware configuration, this might either start executing code from
the DEBUG ROM or from some other address.

4.4 Functions in SER0.OBJ

The functions described in this section are prototyped in the header file ser0.h in the directory

tern\186\include.

The Am186ER only provides one asynchronous serial port. The R-Engine-D comes standard with the
SCC26C92, providing two additional asynchronous ports. The serial port on the Am186ER will be called
SER0, and the two UARTs from the SCC26C92 will be referred to as SER1 and SER2.

This section will discuss functions in ser0.h only, as SER0 pertains to the Am186ER.

By default, SER0 is used by the DEBUG kernel (re40_115.hex) for application download/debugging in
STEP 1 and STEP 2. The following examples that will be used, show functions for SER0, but since it is
used by the debugger, you cannot directly debug SER0. This section will describe its operation and
software drivers. The following section will discuss, SER1 and SER2, which pertain to the external
SCC26C92 UART. SER1 and SER2 will be easier to implement in applications, as they can be directly
debugged in the Paradigm C/C++ environment.

TERN interface functions make it possible to use one of a number of predetermined baud rates. These
baud rates are achieved by specifying a divisor for 1/16 of the processor frequency.

The following table shows the function arguments that express each baud rate, to be used in TERN
functions for SER0 ONLY. SER1 and SER2 have baud rated based upon different arguments. These are
based on a 40 MHz CPU clock.

Function Argument Baud Rate

1 110

2 150

3 300

4 600

5 1200

6 2400

7 4800

8 9600

9 19,200 (default)

10 38,400

11 57,600

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Function Argument Baud Rate

12 115,200

13 250,000

14 500,000

15 1,250,000

Table 4.1 Baud rate values for ser0 only

After initialization by calling s0_init(), SER0 is configured as a full-duplex serial port and is ready to
transmit/receive serial data at one of the specified 15 baud rates.

An input buffer, ser0_in_buf (whose size is specified by the user), will automatically store the
receiving serial data stream into the memory by DMA0 operation. In terms of receiving, there is no
software overhead or interrupt latency for user application programs even at the highest baud rate. DMA
transfer allows efficient handling of incoming data. The user only has to check the buffer status with
serhit0() and take out the data from the buffer with getser0(), if any. The input buffer is used as a
circular ring buffer, as shown in Figure 4.1. However, the transmit operation is interrupt-driven.

ibuf in_tail ibuf+isizin_head

Figure 4.1 Circular ring input buffer

The input buffer (ibuf), buffer size (isiz), and baud rate (baud) are specified by the user with s0_init()
with a default mode of 8-bit, 1 stop bit, no parity. After s0_init() you can set up a new mode with
different numbers for data-bit, stop bit, or parity by directly accessing the Serial Port 0 Control Register
(SP0CT) if necessary, as described in chapter 12 of the Am186ER manual for asynchronous serial ports.

Due to the nature of high-speed baud rates and possible effects from the external environment, serial input
data will automatically fill in the buffer circularly without stopping, regardless of overwrite. If the user
does not take out the data from the ring buffer with getser0() before the ring buffer is full, new data
will overwrite the old data without warning or control. Thus it is important to provide a sufficiently large
buffer if large amounts of data are transferred. For example, if you are receiving data at 9600 baud, a 4­KB buffer will be able to store data for approximately four seconds.

However, it is always important to take out data early from the input buffer, before the ring buffer rolls
over. You may designate a higher baud rate for transmitting data out and a slower baud rate for receiving
data. This will give you more time to do other things, without overrunning the input buffer. You can use
serhit0() to check the status of the input buffer and return the offset of the in_head pointer from the
in_tail pointer. A return value of 0 indicates no data is available in the buffer.

You can use getser0() to get the serial input data byte by byte using FIFO from the buffer. The in_tail
pointer will automatically increment after every getser0() call. It is not necessary to suspend external
devices from sending in serial data with /RTS. Only a hardware reset or s0_close() can stop this
receiving operation.

For transmission, you can use putser0() to send out a byte, or use putsers0() to transmit a
character string. You can put data into the transmit ring buffer, s0_out_buf, at any time using this

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method. The transmit ring buffer address (obuf) and buffer length (osiz) are also specified at the time of
initialization. The transmit interrupt service will check the availability of data in the transmit buffer. If
there is no more data (the head and tail pointers are equal), it will disable the transmit interrupt. Otherwise,
it will continue to take out the data from the out buffer, and transmit. After you call putser0() and
transmit functions, you are free to do other tasks with no additional software overhead on the transmitting
operation. It will automatically send out all the data you specify. After all data has been sent, it will clear
the busy flag and be ready for the next transmission.

The sample program ser1_0.c demonstrates how a protocol translator works. It would receive an input
HEX file from SER1 and translate every ‘:’ character to ‘?’. The translated HEX file is then transmitted
out of SER0. This sample program can be found in tern\186\samples\ae.

Software Interface

Before using the serial ports, they must be initialized.

There is a data structure containing important serial port state information that is passed as argument to the
TERN library interface functions. The COM structure should normally be manipulated only by TERN
libraries. It is provided to make debugging of the serial communication ports more practical. Since it
allows you to monitor the current value of the buffer and associated pointer values, you can watch the
transmission process.

typedef struct {
unsigned char ready; /* TRUE when ready */
unsigned char baud;
unsigned char mode;
unsigned char iflag; /* interrupt status */
unsigned char *in_buf; /* Input buffer */
int in_tail; /* Input buffer TAIL ptr */
int in_head; /* Input buffer HEAD ptr */
int in_size; /* Input buffer size */
int in_crcnt; /* Input <CR> count */
unsigned char in_mt; /* Input buffer FLAG */
unsigned char in_full; /* input buffer full */
unsigned char *out_buf; /* Output buffer */
int out_tail; /* Output buffer TAIL ptr */
int out_head; /* Output buffer HEAD ptr */
int out_size; /* Output buffer size */
unsigned char out_full; /* Output buffer FLAG */
unsigned char out_mt; /* Output buffer MT */
unsigned char tmso; // transmit macro service operation
unsigned char rts;
unsigned char dtr;
unsigned char en485;
unsigned char err;
unsigned char node;
unsigned char cr; /* scc CR register */
unsigned char slave;
unsigned int in_segm; /* input buffer segment */
unsigned int in_offs; /* input buffer offset */
unsigned int out_segm; /* output buffer segment */
unsigned int out_offs; /* output buffer offset */
unsigned char byte_delay; /* V25 macro service byte delay */
} COM;

sn_init
Arguments: unsigned char b, unsigned char* ibuf, int isiz, unsigned char* obuf, int osiz, COM* c
Return value: none

4-15

Chapter 4: Software R-Engine-D

This function initializes either SER0 with the specified parameters. b is the baud rate value shown in Table

4.1. Arguments ibuf and isiz specify the input-data buffer, and obuf and osiz specify the location and size
of the transmit ring buffer.

The serial ports are initialized for 8-bit, 1 stop bit, no parity communication.

There are a couple different functions used for transmission of data. You can place data within the output
b

uffer manually, incrementing the head and tail buffer pointers appropriately. If you do not call one of the
following functions, however, the driver interrupt for the appropriate serial-port will be disabled, which
means that no values will be transmitted. This allows you to control when you wish the transmission of
data within the outbound buffer to begin. Once the interrupts are enabled, it is dangerous to manipulate the
values of the outbound buffer, as well as the values of the buffer pointer.

putsern
Arguments: unsigned char outch, COM *c
Return value: int return_value

This function places one byte outch into the transmit buffer for the appropriate serial port. The return value
returns one in case of success, and zero in any other case.

putsersn
Arguments: char* str, COM *c
Return value: int return_value

This function places a null-terminated character string into the transmit buffer. The return value returns one
in case of success, and zero in any other case.

DMA transfer automatically places incoming data into the inbound buffer. serhitn() should be called
before trying to retrieve data.

serhitn
Arguments: COM *c
Return value: int value

This function returns 1 as value if there is anything present in the in-bound buffer for this serial port.

getsern
Arguments: COM *c
Return value: unsigned char value

This function returns the current byte from sn_in_buf, and increments the in_tail pointer. Once again, this
function assumes that serhitn has been called, and that there is a character present in the buffer.

getsersn
Arguments: COM c, int len, char* str
Return value: int value

This function fills the character buffer str with at most len bytes from the input buffer. It also stops
retrieving data from the buffer if a carriage return (ASCII: 0x0d) is retrieved.

4-16

R-Engine-D Chapter 4: Software

This function makes repeated calls to getser, and will block until len bytes are retrieved. The return value
indicates the number of bytes that were placed into the buffer.

Be careful when you are using this function. The returned character string is actually a byte array
terminated by a null character. This means that there might actually be multiple null characters in the byte
array, and the returned value is the only definite indicator of the number of bytes read. Normally, we
suggest that the getsers and putsers functions only be used with ASCII character strings. If you are
working with byte arrays, the single-byte versions of these functions are probably more appropriate.

Miscellaneous Serial Communication Functions

One thing to be aware of in both transmission and receiving of data through the serial port is that TERN
drivers only use the basic serial-port communication lines for transmitting and receiving data. Hard
flow control in the form of CTS (Clear-To-Send) and RTS (Ready-To-Send) is not implemented.
are, however, functions available that allow you to check and set the value of these I/O pins appropri
w

hatever form of flow control you wish to implement. Before using these functions, you should once

a

gain be aware that the peripheral pin function you are using might not be selected as needed. For details,

please refer to the Am186ES User’s Manual.

char sn_cts(void)
Retrieves value of CTS pin.

void sn_rts(char b)
Sets the value of RTS to b.

Completing Serial Communications

After completing y
default system resources.

_close

sn
Arguments: COM *c
Return value: none

This closes down the serial port, by shutting down the hardware as well as disabling the interrupt.

our serial communications, you can re-initialize the serial port with s1_init(); to reset

ware

There

ate for

The asynchronous serial I/O port available on the Am186ER processor have many other features that might
be useful for y
the manual for a detaile

our application. If you are truly interested in having more control, please read Chapter 12 of

d discussion of other features available to you.

4.5 Functions in SER1R.OBJ

T

he functions found in this object file are prototyped in ser1r.h in the tern\186\include directory.

The SCC26C92 is a component that is used to provide a two additional asynchronous ports. It uses a

3.6864 MHz crystal, different from the system clock speed, for driving serial communications. This means
the divisors and function arguments for setting up the baud rate for SE
SER0.

The SCC26C92 component has its own 3.68
generation of industry standard baud rates.

R1 and SER 2 are different than for

64 MHz crystal providing the clock signal. This allows for the

4-17

Chapter 4: Software R-Engine-D

Function Argument Baud Rate

6 28,800

7 4,800

8 9,600

9 19,200

10 38,400

11 57,600

12 0 115,20

Table 4.2 Baud rate val for SER1 and SE

Unlike the other serial ports, DMA transfer is not used to fill the input buffer for SCC. Instead, an
interrupt-service-routine is used t ce characters into t buffer. If the processor does not respond
to the interrupt—because it is masked, for example—the interrupt service routine might never be able to
complete this process. Over time means data might the SCC as bytes overflow.

Initialization occurs in a manner ilar to SE M structure is once again used to hold

information for the serial port. The in-bound and out-bo

state und buffers operate as before, and must be

ided upon in tialization.

prov i

s1_init
Arguments: unsigned char b, unsigned char* ibuf, int isiz, unsigned char* obuf, int osiz, COM* c
Return value: none

This function initializes SER1 with the specified parameters. b is the baud rate value shown in Table 4.2.
Arguments ibuf and isiz specify the input-data buffer, and obuf and osiz specify the location and size of
the transmit ring buffer.

s2_init
Arguments: unsigned char b, unsigned char* ibuf, int isiz, unsigned char* obuf, int osiz, COM* ca,
COM * cb
Return value: none

This function initializes SER2 with the specified parameters. b is the baud rate value shown in Table 4.1.
Arguments ibuf and isiz specify the input-data buffer, and obuf and osiz specify the location and size of
the transmit ring buffer.

NOTE: The only difference between functions for SER1 and SER2 is that SER2 functions requires
both COM arguments.

ues R 2

o pla he input

, this be lost in

otherwise sim R0. A CO

As a part of initializing th
h

andles the data transfer between the SCC26C92 and the AM186ER. The SCC26C92 UART takes up
external interrupt /INT0 on the CPU. As a part of the “ser1r.h”, s1_isr(); has been created t
automatically handle the n
th

e same interrupt, there is no need for an ISR for SER2.

e serial port, the function call also sets up the interrupt service routine that

eed for an interrupt service routine. Since both channels on the SCC26C92 use

4-18

o

R-Engine-D Chapter 4: Software

By default, the SCC26C92 is enabled for both transmit and receive. This will allow for the use of an
RS-232 in full-duplex mode. Once this is done, you can transmit and receive data as needed. If you do
need to do limited flow control, the MPO pin on the J1 header can be used for RTS. For a sample file
showing RS232 full duplex communications, please see re_scc.c in the directory
tern\186\samples\re.

RS485 is slightly more complex to use than RS232. RS
transmission does not occur concurrently with reception. The RS485 driver will echo back bytes sent to
the SCC. As a result, assuming you are using the RS485 driver installed on another TERN peripheral
board, you will need to disable receive while transmitting. While transmitting, you will also need to place
the RS485 driver in transmission mode as well. While you are receiving data, the RS485 driver will need
to be placed in receive mode.

sn_send_e/sn_rec_e
Arguments: none
Return value: none

This function enables transmission or reception on the SCC26C92 UART for channel n, where n can be
‘1’ or ’2’. After initialization, both of these functions are disabled by default. If you are using RS485,
only one of these two functions should be enabled at any one time.

Transmission and reception of data using the SCC is in most ways identical to SER0. The functions used
to transmit and receive data are similar. For details regarding these functions, please refer to the previous
section.

putsern

putsersn

ern

gets

etsersn

g

h nctions work for both SER1 and SER2, yet it is still important to remember that any function

T e above fu

l to SER2 must

cal pass both COM arguments. Refer to the full definition of s2_init() for the format that
mu

st be followed for all calls to SER2

F

low control is also handled in a mostly similar fashion. The follow table summarizes the flow control

nals.

sig

Channel Flow control line SCC name Location on RE

SER1 RTS OP0 J2 pin 27

485 operation is half-duplex only, which means

SER1 CTS IP0 J2 pin 36

SER2 RTS OP1 J1 pin 3

SER2 CTS IP1 J2 pin 24

4-19

Chapter 4: Software R-Engine-D

unsigned char s1_cts ( void ); reads IP0 = J2

oid s1_rts ( char b ); // drives OP0 = J2.27

v

unsigned char s2_cts ( void ); // reads IP1 = J2.24

void s2_rts ( char b ); // drives OP1 = J1.3

Other SCC functions are similar hose for SER0 and SE

sn_close

serhitn

clean_sern

4.6 Functio

he 512-byte serial EEPROM (24C04) provided on-board allows easy storage of non-volatile program

T

arameters. This is usually an ideal location to store important configuration values that do not need to be

p
changed often. Access to the EEPROM
controller.

ns in AEEE.OBJ

// .36

to t R1.

is quite slow, compared to memory access on the rest of the

Part of the EEPROM is reserved for TERN use specifically for this purpose.

Addresses 0x00 to 0x1f on the EEPROM is reserved for system use, including configuration information
about the controller itself, jump address for Step Two, and other data that is of a more permanent nature.

The rest of the EEPROM memory space, 0x20 to 0x1ff, is available for your application use.

ee_wr
Arguments: int addr, unsigned char dat
Return value: int status

This function is used to write the passed in dat to the specified addr. The return value is 0 in success.

ee_rd
Arguments: int addr
Return value: int data

This function returns one byte of data from the specified address.

4-20

R-Engine-D Chapter 4: Software

4.7 Other Sample code

The following is a list of other sample code available for the R-Engine-D. Each will show an example
im

plementation of the specific hardware and are located in the tern\186\samples\rd directory. Most can also

be found in the rd.ide test project.

rd_cs89.c // Ethernet controller

rd_cf.c // Compact flash interface, shows raw reads/writes by sector

tern\186\samples\fn\fs_cmds1.c // file system demo, see rd.ide

rd_hv.c // high voltage drivers.

4.7.1 File system support

TERN libraries support FAT file system
F

lashCore technical manual (tern_docs\manuals\flashcore.pdf) for a summary of the available routines.

T

he libraries and header files are as follows:

fileio.h

filegio.h

filesy16.lib

mm16.lib

Libraries are found in the tern\186\lib directory and header files in the tern\186\include directory. Refer to
rd.ide for two samples, rd_

cf.c and fs_cmds1.c.

for the Compact Flash interface. Refer to Chapter 4 of the

4-21

GND 1 2

GND

CLK

J1

3 4

5 6

7 8

9 10
VOFF

VCCGND

OP1

RXDB

TXDB

VCC

VCC

P14

P6

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31 32

33 34

35 36

37 38

39 40

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TXD0

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V+

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GNDD1D0D2D3D4D5D6D7

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6A136Y125A115Y104A 94Y

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Y015Y114Y213Y312Y411Y510Y6 9Y7

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1VO 2VI 3
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4

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GND

16MHZ

BB1117

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U16

D4D3D2D1D0

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11 12

13 14

15 16

17 18

19 20

21 22

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21 22

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A1648/BY47GND46D15

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2

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P18

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GND

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DAC7625

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NMI

OP0

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1 2

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REF+5V

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GND

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11 12

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AH65VGND

COMVCC

H1H2H3H4H5

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1C162C153C144C135C126C117C
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10K

1
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39 40

41 42

43 44

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47 48

49 50

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6

D4

/AD

U30

5V

VCC20CLK

AD0

1

AH0

10K

RAM44

D

0

2

7

W

R

2

8

BSY

2

9

CLK

3

0

R

D

3

1

C

S

3

2

5

V

5V

HV0

1I2 2I3 3I4 4I5 5I6 6I7 7I8 8VS 9
Q0Q1Q2Q3Q4Q5Q6

SCLK

19

2

AH1

A0

1A1 2A2 3A3 4A4 5A5 6A6 7A7 8
AD0

AD1

HV1

HV2

HV3

HV4

HV5

HV6

O118O217O316O415O514O613O712O8
I1

SDAT

IP6

OP3

OP4

18

CS

DIN17BSY16DOU15GND14GND13VCC12REF

AD1

AD2

AD3

AD4

AD5

AD6

AD7

3

4

5

6

7

8

AH2

AH3

AH4

AH5

AH6

AH7 GND

C2

/RST

RST

WDO

16

15

RST

WDO14CEI13CEO12WDI11PFO10PFI

/RST

VB

VCC

U6

1VO 2

3

VRAM

VBAT

VCC

GK1

10

G

VS1

D8

AD2

HV7

11

Q7

5V

COM

9

GND

COMGND

/LCS

GND

4

C18

5V 5V

5V

5V

UDS2982

D10

D9

AD3

AD4

GK

10

G

VS

5V5V

REF+

11

SHD

10

P29

J9

1 2
WDI

/RAM

BON

/LL

5

6

C7

C01

10UF

ALCAP2

C23

10UF

ALCAP2

VCC

I01

1

RN2

D13

D12

D11

D917D818D719D620D521D422D323D2

DGN

AD5

AD6

AD7

UDS2982

U28

ADS8344

HDRD2

VCC

/PFO

9

OSI

OSS

7

8

V+

5V5VV+

5V 85V 79V 69V

NC

U26

1PG 2

I02

I03

I04

I05

AD7852

1

D10

1

D11

1

A

0

1

A

1

1

A

2

1

G

1

RF+

A

G

Q0Q1Q2Q3Q4

5

6

7

Q0 4Q1

Q2

Q3

D

S0

S1

13

1

2

D0

A1A2A3

L1

LED

LC

R1

680

VCC P29

VCC

GND

7

8

WP

VCC

A0

MAX691

U7

1A1 2A2 3

GND

GND

C41

10UF

V+

5

GND

3EN 4

I06

I07

8 7 6 5 4 3 2

D14

6
5
4
3
2
1
0
9

GND

Q5

10

Q4 9Q5

S2

3

H1

P22

P29

5

SCL 6SDA

4

GND

GND

ALCAP2

TPS765

1K

VCC

D15REF1

Q7 GND A1

11

12

Q6

G

14

15

/RST

/HA Q6

1 2

VOFF GND

VSS

24C04S

TPS765

C02

A2A3

Q7

CLR

74HC259

HDRD2

STE

10UF

ALCAP2

R-Drive

Title

B RD1-MAN.SCH

Date: May 30, 2003 Sheet 1 of 1

Size Document Number REV

D11

D12

D13

CD126D1127D1228D1329D1430D15

GND

U24

1D3 2D4 3D5 4D6 5D7 6

D4D6D3

D5

GND

D14

/CF

VCC

D15

31

33

/RD34/WR35/WE36RDY37VCC38/CS39VS240RST41/WT42/IP

/CE232/VS1

/CE1

A10

/OE

7

8

9A9 10A8 11A7 12

D7

/RD2

GND

/CF

VCC

/WR2

VCC

INT4

RST

43

VCC

13A6 14A5 15A4 16A3 17A2 18A1 19A0 20D0 21D1 22D2 23WP 24

A3A1D0D2A2

VCC

A4

GND

GND

GND

GND

GND

GND

VCCD9D8

46

44

BV245BV1

/REG

D1

48

D847D9

D10

D1049GND

GND

GND

50

25

CD2

CFB

VCC

VCC

GND

+12V

GND

RST

RST

+12V

/ET

/ET

/CF

TXD0

/CF

RXD0

TXD0

TXDA

RXD0

TXDA

RXDA

RXDA

RXDB

TXDB

RXDB

OP1

OP1

TXDB

D9D8D10

D11

D12

D13

D14

D10

D11

D12

D13

D14

D15

D15

STE

RD I/O

D4D3D2D1D0

D7D6D5

A2A1/RST

/RD2

/WR2

A3

IP5

IP1

D0D1D2D3D4

IP5

IP1

V+

V+

A4

D5D6D7A2A1

A3

A4

/RD2

/WR2

/RST

INT3

INT4

INT3

INT4

/RD

/RD

/WR

/WR

VOFF

VOFF

D8

D9

RXD-

R8

10PF

XTAL4

XG XD

10PF

VCC

RXD+

RES

GND

4.99K

GND

C26

C25

VCC GND

20MHZ

TXD+

TXD-

XG

GND

HC1

VCC

GND

XD

LINKLED

U25

VCC

7
7
7
7
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9

100

LANLED

C30

68PF

TX-

24.9

C28

0.1UF

R+

RCAP

RXD+

RC

R-

R17

TXD-

TCAP

C31

0.1UF

24.9

T-

TX-

TX+

R18

TXD+

C29

TCAP

TC

24.9

0.1UF

T+

9

TX+

C32

1234567

T+T-R+

R10

L2

VCC

ST7011

10BT

0.1UF

RJ45

LINKLED

R11

680

V2

L3

VCC

LANLED

680

V3

LED

RXD+

R16

GND

VCCD0D1D2D3

D4D5D6D7RSTGND

71

D774D673D572D4

ELCS

EECS

2

3

4

EESK

5

GND70VDD

EEDO

EEDI

6

GND

69

D368D267D166D0

CHIPSEL

GND

7

8

75

RESET

6

TES

T

7

SLP

8

HC1

9

DI+

0

DI-

1

CI+

2

CI-

3

DO+

4

DO-

5

AVD

D

6

AGN

D

7

TXD

+

8

TXD

-

9

AGN

D

0

AVD

D

1

RXD

+

2

RXD

-

3

RES

4

AGN

D

5

AVD

D

6

AGN

D

7

X

1

8

X

2

9

HC0
LLE

D

AGND

1

/WR2

/RD2

/ET

65

64

AEN63IOW62IOR61A1960A1859A1758GND57VDD56GND55A1654A1553A1452A13

IORDY

VDD

GND

DRQ2

DACK2

DRQ1

DACK1

DRQ0

9

10

11

12

13

14

GND

VCC

15

VCC

VCC

DACK0

16

17

VCC

GND

CSOUT

D15

18

19

GND

VCC

D14

20

GND

IOCS1

D13

D12

21

22
VCC

A12

FRESH

A11
A10

SBH
INT

MCS16

INT
INT
INT

MRD
MWR

VDD

GND

D11

23

24

GND

51

A
A
A
A
A
A
A
A
A
A

D
D

25

9
8
7
6
5
4
3
2
1
0
E
3

6
0
1
2

8
9

D10

CS8900

GND

5

0

4

9

4

8

4

7

4

6

4

5

4

4

4

3

4

2

4

1

4

0

3

9

3

8

3

7

3

6

3

5

3

4

3

3

3

2

3

1

3

0

2

9

2

8

2

7

2

6

GND

VCC

VCC

GND

VCCVCC GND

INT3

RXD-

RCAP

R-

O116O215O314NC13NC12O411O510O6
I1

A4A1

U20

A2 A3

1I2 2I3 3NC 4NC 5I4 6I5 7I6 8

RXD-

8

J5

Title

B RD2-MAN.SCH

Date: May 30, 2003 Sheet 2 of 2

Size Document Number REV

/TXDB

/CTS

/RTS

220

VCC

10K

R13

R14

5 6

7 8

/RXDB

5 6

7 8

/RXD0

R12

9 10

GND

H3

9 10H2 1 2

GND

/RXDB

H4

1 2

3 4

/TXDB

1 2

3 4

/TXD0

/RXDB /TXDB

3 4

5 6

/TXDA

/RXDA

10K

/TXDBGND

7 8

9 10

VCC

U02

/TXDB

8

VCC
RO

1

2DE 3DI 4

GND

RXDB

/RXDB

6

B 7A

/RE

OP1

5

GND

TXDB

VCC

LTC485

U23

+12V

D1

+12VI

8

VCC
RO

1

RXDB

/CTS

/RTS

6

5

B 7A

/RE

2DE 3DI 4

GND

C39

1N5817

GND

LTC485

+12V

R15

123 45

LM2575

1M

U19

VOFF

VCC

LX1

+12V

C27

GND

D2

I1 330uH

1N5817

C33

0.1UF

C5+

C2+

GND

RXDA

/RXDA

/TXDA C5-

VCC

VCC16GND15T1O14R1I13R1O12T1I11T2I10R2O

C1+

C1-

C2+

1V+ 2

C5+

V+

1

2

+12VI

GND

3

C5-

4

C2+

T2

C2-

5V- 6

C2-

U21

T1

C34

TXD0

TXDA

7

/TXD0

V-

0.1UF

C2-

RXD0

9

T2O

R2I

8

/RXD0

C3+

VCC

VCC16GND15T1O14R1I13R1O12T1I11T2I10R2O

C1+

MAX232D

MAX232D

U22

1V+ 2

C3+

C35

GND

V+

0.1UF

C3-

/RTS

3

C3-

C4+

OP1

/CTS

IP1

C1-

C2+

C2-

4

5V- 6

C4+

C4-V-/RXDB

C36

0.1UF

C4-

TXDB

RXDB

9

T2O

R2I

7

8

/TXDB

V+

MAX232D

MAX232D

C37

0.1UF

GND

C38

0.1UF

V-