Standard Microsystems Corporation FDC87W22 Datasheet

FDC87W22

Power I/O Controller

FEATURES

• 5 Volt Operation

• Floppy Disk Controller (FDC)

- Compatible with IBM PC/AT Disk Drive
Systems

- Variable Write Pre-Compensation with
Track Selectable Capability

- DMA Enable Logic

- Non-Burst Mode DMA Option

- Supports Floppy Disk Drives and Tape

Drives

- Detects All Overrun and Underrun
Conditions

- Data Rate and Drive Control Registers

- Built-in Address Mark Detection Circuit to

Simplify the Read Electronics

- IBM PC System Address Decoder

- Supports up to Two Embedded Hard

Disk Drives (IDE AT BUS)

- Single 24 MHz Crystal Input

- FDD Anti-Virus Functions With Software

Write Protect and FDD Write Enable
Signal, Write Data Signal Force Inactive

- Supports up to Four 3.5-Inch or 5.25­Inch Floppy Disk Drives

- Completely Compatible with Industry
Standard 82077

- 360Kbps/720K/1.2M/1.44M/2.88M
Format

- 250Kbps, 300Kbps, 500Kbps, 1 Mbps
Data Transfer Rate

- Supports Vertical Recording Format

- 16-Byte Data FIFOs

• Serial Ports

- Two High-speed 16550 Compatible
UARTs with 16-Byte Send/Receive
FIFOs

- MIDI Compatible

- Fully Programmable Serial-Interface

Characteristics:

- 5, 6, 7 or 8-Bit Characters

- Even, Odd or No Parity Bit

Generation/Detection

- 1, 1.5 or 2 Stop Bits Generation

- Internal Diagnostic Capabilities:

- Loop-Back Controls for

Communications Link Fault Isolation

- Break, Parity, Overrun, Framing Error
Simulation

- Programmable Baud Generator Allows
Division of 1.8461 MHz and 24 MHz by 1
to (216-1)

• Parallel Port

- Compatible with IBM Parallel Port

- Supports Parallel Port with Bidirectional

Lines

- Supports Enhanced Parallel Port (EPP)

- Compatible with IEEE 1284

Specification

- Supports Extended Capabilities Port
(ECP)

- Compatible with IEEE 1284
Specification

- Extension FDD Mode Supports Disk
Drive B Through Parallel Port

- Extension Adapter Mode Supports
Pocket Devices Through Parallel Port

2

- Extension 2FDD Mode Supports Disk
Drives A And B Through Parallel Port

- JOYSTICK Mode Supports Joystick
Through Parallel Port

• Programmable Configuration Settings

• Immediate or Automatic Power-Down Mode

for Power Management

• ISA Host Interface

• All Hardware Power-On Settings Have

Internal Pull-Up or Pull-Down Resistors as
Default Value

• Configurable Plug and Play Registers

• Infrared Communication Port

• 100 Pin QFP Package

GENERAL DESCRIPTION

The FDC87W22 integrates a disk drive adapter,
serial port (UART), parallel port, IDE bus
interface, and game port decoder onto a single
chip. The FDC87W22 also has additional
powerful features such as configurable plug­and-play registers for the whole chip and
infrared support in one of the serial ports.

The disk drive adapter functions of the
FDC87W22 include a floppy disk drive controller
compatible with the industry standard
82077/765 data separator, write pre­compensation circuit, decode logic, data rate
selection, clock generator, drive interface control
logic, and interrupt and DMA logic. The wide
range of functions integrated into the
FDC87W22 greatly reduces the number of
components required for interfacing with floppy
disk drives. The FDC87W22 supports four
360K, 720K, 1.2M, 1.44M, or 2.88M disk drives
and data transfer rates of 250 Kb/S, 300 Kb/S,
500 Kb/S, and 1 Mb/S.

The FDC87W22 provides two high-speed serial
communication ports (UARTs), one of which
supports serial Infrared communication. Each
UART includes a 16-byte send/receive FIFO, a
programmable baud rate generator, complete
modem control capability, and a processor
interrupt system.

The FDC87W22 supports one PC-compatible
printer port. Additional bidirectional I/O

capability is available by hardware control or
software programming. The parallel port also
supports the Enhanced Parallel Port (EPP) and
Extended Capabilities Port (ECP). The
FDC87W22 supports two embedded hard disk
drive (AT bus) interfaces and a game port with
decoded read/write output. The chip's Extension
FDD Mode and Extension 2FDD Mode allow one
or two external floppy disk drives to be
connected to the computer through the printer
interface pins in notebook computer
applications.

The Extension Adapter Mode of the FDC87W22
allows pocket devices to be installed through the
printer interface pins in notebook computer
applications according to a protocol set by
SMSC, but with upgraded performance. The
JOYSTICK mode allows a joystick to be
connected to a parallel port with a signal
switching cable. The configuration registers
support mode selection, function enable/disable,
and power down function selection. Moreover,
the configurable PnP registers are compatible
with the plug-and-play feature in Windows 95TM,
which makes system resource allocation more
efficient than ever.

Standard Microsystems is a registered trademark and
SMSC is a trademark of Standard Microsystems
Corporation. Other product and company names are
trademarks or registered trademarks of their respective
holders.

3

TABLE OF CONTENTS

FEATURES....................................................................................................................................... 1

GENERAL DESCRIPTION ................................................................................................................ 2

PIN CONFIGURATION...................................................................................................................... 5

PIN DESCRIPTION .......................................................................................................................... 6

HOST INTERFACE.............................................................................................................................. 6

SERIAL PORT INTERFACE ................................................................................................................... 7

GAME PORT/POWER DOWN INTERFACE...............................................................................................9

MULTI-MODE PARALLEL PORT .......................................................................................................... 10

IDE AND FDC INTERFACE ............................................................................................................... 18

FDC FUNCTIONAL DESCRIPTION................................................................................................. 20

FDC87W22 FDC.......................................................................................................................... 20

AT INTERFACE............................................................................................................................... 20

FIFO (DATA)................................................................................................................................. 20

DATA SEPARATOR .......................................................................................................................... 21

WRITE PRECOMPENSATION .............................................................................................................. 21

PERPENDICULAR RECORDING MODE .................................................................................................. 21

FDC CORE ................................................................................................................................... 22

FDC COMMANDS............................................................................................................................ 23

REGISTER DESCRIPTIONS................................................................................................................. 32

STATUS REGISTER A (SA REGISTER) (READ BASE ADDRESS + 0).......................................................... 33

STATUS REGISTER B (SB REGISTER) (READ BASE ADDRESS + 1).......................................................... 35

DIGITAL OUTPUT REGISTER (DO REGISTER) (WRITE BASE ADDRESS + 2)............................................... 37

TAPE DRIVE REGISTER (TD REGISTER) (READ BASE ADDRESS + 3)........................................................ 37

MAIN STATUS REGISTER (MS REGISTER) (READ BASE ADDRESS + 4)..................................................... 38

DATA RATE REGISTER (DR REGISTER) (WRITE BASE ADDRESS + 4) ...................................................... 39

FIFO REGISTER (R/W BASE ADDRESS + 5) ........................................................................................ 40

STATUS REGISTER 0 (ST0).............................................................................................................. 41

STATUS REGISTER 1 (ST1).............................................................................................................. 41

STATUS REGISTER 2 (ST2).............................................................................................................. 42

STATUS REGISTER 3 (ST3).............................................................................................................. 42

DIGITAL INPUT REGISTER (DI REGISTER) (READ BASE ADDRESS + 7) ...................................................... 42

CONFIGURATION CONTROL REGISTER (CC REGISTER) (WRITE BASE ADDRESS + 7) ................................. 44

IDE.................................................................................................................................................. 45

IDE DECODE DESCRIPTION..............................................................................................................45

UART PORT ................................................................................................................................... 46

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)............................................ 46

UART CONTROL REGISTER (UCR) (READ/WRITE).............................................................................49

UART STATUS REGISTER (USR) (READ/WRITE)................................................................................ 50

4

HANDSHAKE CONTROL REGISTER (HCR) (READ/WRITE)...................................................................... 51

HANDSHAKE STATUS REGISTER (HSR) (READ/WRITE) ........................................................................ 52

UART FIFO CONTROL REGISTER (UFR) (WRITE ONLY)..................................................................... 53

INTERRUPT STATUS REGISTER (ISR) (READ ONLY).............................................................................. 54

INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) ........................................................................ 56

PROGRAMMABLE BAUD GENERATOR (BLL/BHL) (READ/WRITE)............................................................ 56

USER-DEFINED REGISTER (UDR) (READ/WRITE) ................................................................................ 57

PARALLEL PORT.......................................................................................................................... 58

PRINTER INTERFACE LOGIC .............................................................................................................. 58

ENHANCED PARALLEL PORT (EPP)................................................................................................... 61

DATA SWAPPER ............................................................................................................................. 61

PRINTER STATUS BUFFER................................................................................................................61

PRINTER CONTROL LATCH AND PRINTER CONTROL SWAPPER ............................................................... 62

EPP ADDRESS PORT......................................................................................................................63

EPP DATA PORT 0-3...................................................................................................................... 63

EPP OPERATION............................................................................................................................ 65

EXTENDED CAPABILITIES PARALLEL (ECP) PORT................................................................................. 65

EXTENSION FDD MODE (EXTFDD)..................................................................................................74

EXTENSION 2FDD MODE (EXT2FDD).............................................................................................. 74

SPECIFICATIONS..........................................................................................................................116

ABSOLUTE MAXIMUM RATINGS.................................................................................................116

DC CHARACTERISTICS................................................................................................................116

AC CHARACTERISTICS................................................................................................................118

TIMING WAVEFORMS ..................................................................................................................124

APPLICATION CIRCUITS..............................................................................................................136

PACKAGE DIMENSIONS ..............................................................................................................139

80 Arkay Drive
Hauppauge, NY 11788
[phone]
FAX [phone]

5

PIN CONFIGURATION

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

nINDEX

nSTEP

nDSA
nDSB

nWE
nWD

nRWC

nHEAD

nDIR
GND

nIDBEN

IRQ_B

nIRQIN

nCS0
nCS1

IRQ_A

TC

nDACK_B

IRQ_F

DRQ_B

nMOB

nMOA

nTRAK0

NWP

nDSKCHG

A10

nRDATAD7D6D5D4D3D2D1D0

GND

nIOW

nIOR

AENA9A8A7A6A5VDDA4A3A2A1

A0

8079787776757473727170696867666564636261605958575655545352

51

nRIB
nDCDB
nDSRB
nCTSB
nDTRB
nRTSB
IRQ_C
SOUTB
SINB
nGMRD
GND
nGMWR
SOUTA
IRQ_D
nRTSA
nDTRA
nCTSA
nDSRA
nDCDA
nRIA

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

1234567891011121314151617181920212223242526272829

30

nRESIDE

nCS

nPDCIN

DRQ_C

IOCHRDY

MR

XTAL1

XTAL2

PD0

PD1

PD2

PD3

PD4

PD5

VDD

PD6

PD7

nDACK_C

nSTB

nAFD

nINIT

nSLIN

IRQ_E

BUSY

GND

nACK

PE

SLCT

nERR

SINA

FDC87W22

6

PIN DESCRIPTION

I/O8t TTL level bidirectional pin with 8 mA source-sink capability
I/O12t TTL level bidirectional pin with 12 mA source-sink capability
I/O24t TTL level bidirectional pin with 24 mA source-sink capability

OUT8t TTL level output pin with 8 mA source-sink capability

OUT12t TTL level output pin with 12 mA source-sink capability

OD12 Open-drain output pin with 12 mA sink capability
OD24 Open-drain output pin with 24 mA sink capability

INt TTL level input pin

INc CMOS level input pin

INcs CMOS level schmitt-triggered input pin

Note: Refer to DC CHARACTERISTICS section for details.

Host Interface

SYMBOL PIN I/O FUNCTION

D0−D7

66-73 I/O

24t

System data bus bits 0-7

A0−A9

51-55
57-61

IN

c

System address bus bits 0-9

A10 75 IN

c

In ECP Mode, this pin is the A10 address input.

IOCHRDY 5 OD

24

In EPP Mode, this pin is the IO Channel Ready output to
extend the host read/write cycle.

MR 6 IN

cs

Master Reset. Active high. MR is low during normal
operations.

nCS 2 IN

t

Active low chip select signal

AEN 62 IN

c

System address bus enable

nIOR 63 IN

cs

CPU I/O read signal

nIOW 64 IN

cs

CPU I/O write signal

DRQ_B 100 OUT

12t

DMA request signal B

nDACK_B 98 IN

c

DMA Acknowledge signal B

DRQ_C 4 OUT

12t

DMA request signal C

nDACK_C 18 IN

c

DMA Acknowledge signal C

TC 97 IN

c

Terminal Count. When active, this pin indicates termination
of a DMA transfer.

nIRQIN 93 IN

c

Interrupt request input
IRQ_A/
GIO1

96 OUT

12t

I/O

12t

When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal

A;

When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port

1.

7

SYMBOL PIN I/O FUNCTION

IRQ_B/
GIO0

92 OUT

12t

I/O

12t

When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal

B;

When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port

0.

IRQ_C 44 OUT

12t

Interrupt request signal C
IRQ_D 37 OUT

12t

Interrupt request signal D
IRQ_E 23 OUT

12t

Interrupt request signal E
IRQ_F 99 OUT

12t

Interrupt request signal F
XTAL1 7 IN

c

XTAL oscillator input
XTAL2 8 OUT

8t

XTAL oscillator output

Serial Port Interface

SYMBOL PIN I/O FUNCTION

nCTSA
nCTSA

34
47

IN

t

Clear To Send is the modem control input.

The function of these pins can be tested by reading Bit 4 of

the handshake status register.
nDSRA

nDSRB

33
48

IN

t

Data Set Ready. An active low indicates the modem or data

set is ready to establish a communication link and transfer

data to the UART.
nDCDA
nDCDB

32
49

IN

t

Data Carrier Detect. An active low indicates the modem or

data set has detected a data carrier.
nRIA

nRIB

31
50

IN

t

Ring Indicator. An active low indicates that a ring signal is

being received by the modem or data set.
SINA

SINB/IRRX1

30
42

IN

t

Serial Input. Used to receive serial data from the

communication link.
SOUTA/

PIRIDE

38 I/O

8t

UART A Serial Output. Used to transmit serial data out to

the communication link.

During power-on reset, this pin is pulled up internally and is

defined as PIRIDE, which provides the power-on value for

CR16 bit 1 (IRIDE). A 47 kΩ is recommended when intends

to pull down at power-on reset.
SOUTB/
IRTX1/
PGMDRQ

43 I/O

8t

UART B Serial Output. Used to transmit serial data out to

the communication link.

During power-on reset, this pin is pulled up internally and is

defined as PGMDRQ, which provides the power-on value for

CR16 bit 3 (GMDRQ). A 47 kΩ is recommended when

intends to pull down at power-on reset.

8

SYMBOL PIN I/O FUNCTION

nDTRA
PHEFRAS

35 I/O

8t

UART A Data Terminal Ready. An active low informs the

modem or data set that the controller is ready to

communicate.

During power-on reset, this pin is pulled down internally and

is defined as PHEFRAS, which provides the power-on value

for CR16 bit 0 (HEFRAS). A 47 kΩ is recommended when

intends to pull up at power-on reset.
nDTRB 46 O

8t

UART B Data Terminal Ready. An active low informs the

modem or data set that controller is ready to communicate.
nRTSA

PPNPCVS

36 I/O

8t

UART A Request To Send. An active low informs the

modem or data set that the controller is ready to send data.

During power-on reset, this pin is pulled up internally and is

defined as PPNPCVS, which provides the power-on value

for CR16 bit 2 (PNPCVS). A 47 kΩ is recommended when

intends to pull down at power-on reset.
nRTSB
PGOIQSEL

45 I/O

8t

UART B Request To Send. An active low informs the

modem or data set that the controller is ready to send data.

During power-on reset, this pin is pulled down internally and

is defined as PGOIQSEL, which provides the power-on

value for CR16 bit 4 (GOIQSEL). A 47 kΩ is recommended

when intends to pull up at power-on reset.

9

Game Port/Power Down Interface

If Bit 3 of CR16 (GMDRQ) is 1, Bit 4 of CR3
(GMODS0) determines whether the game port is

in Adapter mode or Portable mode (default is
Adapter mode). If Bit 3 of CR16 is 0, pin 39 and
41 are used for DMA A operation.

SYMBOL PIN I/O FUNCTION

nGMRD
PFDCEN

nDACK_A

41 OUT

8t

OUT

8t

IN

t

When CR16 Bit 3 (GMDRQ) = 1:

Adapter mode: Game port read control signal.

Portable mode: When parallel port is selected as Extension

FDD/Extension 2FDD mode, this pin will be active. The active

state is dependent on bit 7 of CRA (PFDCACT), and default is

low active.

When CR16 Bit 3 (GMDRQ) = 0:

DMA acknowledge signal A.
nGMWR
PEXTEN

DRQ_A

39 OUT

8t

OUT

8t

OUT

8t

When CR16 Bit 3 (GMDRQ) = 1:

Adapter mode: Game port write control signal.

Portable mode: When a particular extended mode is selected

for the parallel port, this pin will be active. The extended

modes include Extension Adapter mode, EPP mode, ECP

mode, and ECP/EPP mode, which are selected using bit 3 -

bit 0 of CRA. The active state is dependent on bit 6 of CRA

(PEXTACT); the default is low active.

When CR16 Bit 3 (GMDRQ) = 0:

DMA request signal A.
PDCIN 3 IN

c

This input pin controls the chip power down. When this pin is

active, the clock supply to the chip will be inhibited and the

output pins will be tri-stated as defined in CR4 and CR6. The

PDCIN is pulled down internally. Its active state is defined by

bit 4 of CRA (PDCHACT). Default is high active.

10

Multi-Mode Parallel Port

The following pins have eight functions, which
are controlled by bits PRTMOD0, PRTMOD1,
and PRTMOD2 of CR0 and CR9 (refer to the
Extended Functions section).

SYMBOL PIN I/O FUNCTION

BUSY 24 IN

t

OD

12

IN

t

OD

12

_

PRINTER MODE: BUSY

An active high input indicates that the printer is not ready to

receive data. This pin is pulled high internally. Refer to the

description of the parallel port for the definition of this pin in

ECP and EPP mode.

EXTENSION FDD MODE: nMOB2

This pin is for Extension FDD B; the function of this pin is the

same as that of the nMOB pin.

EXTENSION ADAPTER MODE: XIRQ

This pin is an interrupt request generated by the Extension

Adapter and is an active high input.

EXTENSION 2FDD MODE: nMOB2

This pin is for Extension FDD A and B; the function of this pin

is the same as that of the nMOB pin.

JOYSTICK MODE: NC pin.
nACK 26 IN

t

OD

12

IN

t

OD

12

_

PRINTER MODE: nACK

An active low input on this pin indicates that the printer has

received data and is ready to accept more data. This pin is

pulled high internally. Refer to the description of the parallel

port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nDSB2

This pin is for the Extension FDD B; its functions are the

same as those of the nDSB pin.

EXTENSION ADAPTER MODE: XDRQ

DMA request generated by the Extension Adapter. An active

high input.

EXTENSION 2FDD MODE: nDSB2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nDSB pin.

JOYSTICK MODE: NC pin.

11

SYMBOL PIN I/O FUNCTION

PE 27 IN

t

OD

12

OUT

12t

OD

12

_

PRINTER MODE: PE

An active high input on this pin indicates that the printer has

detected the end of the paper. This pin is pulled high

internally.

Refer to the description of the parallel port for the definition of

this pin in ECP and EPP mode.

EXTENSION FDD MODE: nWD2

This pin is for Extension FDD B; its function is the same as

that of the nWD pin.

EXTENSION ADAPTER MODE: XA0

This pin is system address A0 for the Extension Adapter.

EXTENSION 2FDD MODE: nWD2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nWD pin.

JOYSTICK MODE: NC pin.
SLCT 28 IN

t

OD

12

OUT

12t

OD

12

_

PRINTER MODE: SLCT

An active high input on this pin indicates that the printer is

selected. This pin is pulled high internally. Refer to the

description of the parallel port for the definition of this pin in

ECP and EPP mode.

EXTENSION FDD MODE: nWE2

This pin is for Extension FDD B; its functions are the same as

those of the nWE pin.

EXTENSION ADAPTER MODE: XA1

This pin is system address A1 for the Extension Adapter.

EXTENSION 2FDD MODE: nWE2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nWE pin.

JOYSTICK MODE: NC pin.

12

SYMBOL PIN I/O FUNCTION

nERR 29 IN

t

OD

12

OUT

12t

OD

12

_

PRINTER MODE: nERR

An active low input on this pin indicates that the printer has

encountered an error condition. This pin is pulled high

internally. Refer to the description of the parallel port for the

definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nHEAD2

This pin is for Extension FDD B; its function is the same as

that of the nHEAD pin.

EXTENSION ADAPTER MODE: XA2

This pin is system address A2 for the Extension Adapter.

EXTENSION 2FDD MODE: nHEAD2

This pin is for Extension FDD A and B; its function is the

same as that of the nHEAD pin.

JOYSTICK MODE: NC pin.

nSLIN 22 OD

12

OD

12

OUT

12t

OD

12

OUT

12t

PRINTER MODE: nSLIN

Output line for detection of printer selection. This pin is pulled

high internally. Refer to the description of the parallel port for

the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nSTEP2

This pin is for Extension FDD B; its function is the same as

that of the nSTEP pin.

EXTENSION ADAPTER MODE: XTC

This pin is the DMA terminal count for the Extension Adapter.

The count is sent by TC directly.

EXTENSION 2FDD MODE: nSTEP2

This pin is for Extension FDD A and B; its function is the

same as that of the nSTEP pin .

JOYSTICK MODE: VDD for joystick.

13

SYMBOL PIN I/O FUNCTION

nINIT 21 OD

12

OD

12

OUT

12t

OD

12

OUT

12t

PRINTER MODE: nINIT

Output line for the printer initialization. This pin is pulled high

internally. Refer to the description of the parallel port for the

definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nDIR2

This pin is for Extension FDD B; its function is the same as

that of the nDIR pin.

EXTENSION ADAPTER MODE: nXDACK

This pin is the DMA acknowledge output for the Extension

Adapter; the output is sent directly from nPDACKX.

EXTENSION 2FDD MODE: nDIR2

This pin is for Extension FDD A and B; its function is the

same as that of the nDIR pin.

JOYSTICK MODE: VDD for joystick.

nAFD 20 OD

12

OD

12

OUT

12t

OD

12

OUT

12t

PRINTER MODE: nAFD

An active low output from this pin causes the printer to auto

feed a line after a line is printed. This pin is pulled high

internally. Refer to the description of the parallel port for the

definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nRWC2

This pin is for Extension FDD B; its function is the same as

that of the nRWC pin.

EXTENSION ADAPTER MODE: nXRD

This pin is the I/O read command for the Extension Adapter.

When the Extension Adapter base address is written to the

Extension Adapter address register, nXRD and nXWR go low

simultaneously so that the command register on the

Extension Adapter can latch the same base address.

EXTENSION 2FDD MODE: nRWC2

This pin is for Extension FDD A and B; its function is the

same as that of the nRWC pin.

JOYSTICK MODE: VDD for joystick.

14

SYMBOL PIN I/O FUNCTION

nSTB 19 OD

12

-

OUT

12t

-

OUT

12t

PRINTER MODE: nSTB

An active low output is used to latch the parallel data into the

printer. This pin is pulled high internally. Refer to the

description of the parallel port for the definition of this pin in

ECP and EPP mode.

EXTENSION FDD MODE:

This pin is a tri-state output.

EXTENSION ADAPTER MODE: nXWR

This pin is the I/O write command for the Extension Adapter.

When the Extension Adapter base address is written to the

Extension Adapter address register, nXRD and nXWR go low

simultaneously so that the command register on the

Extension Adapter can latch the same base address.

EXTENSION 2FDD MODE: This pin is a tri-state output.

JOYSTICK MODE: VDD for joystick.

PD0 9 I/O

24t

IN

t

I/O

24t

IN

t

I/O

24t

PRINTER MODE: PD0

Parallel port data bus bit 0. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE: nINDEX2

This pin is for Extension FDD B; the function of this pin is the

same as that of the nINDEX pin. This pin is pulled high

internally.

EXTENSION ADAPTER MODE: XD0

This pin is system data bus D0 for the Extension Adapter.

EXTENSION 2FDD MODE: nINDEX2

This pin is for Extension FDD A and B; this function of this pin

is the same as nINDEX pin. This pin is pulled high internally.

JOYSTICK MODE: JP0

This pin is the paddle 0 input for joystick.

15

SYMBOL PIN I/O FUNCTION

PD1 10 I/O

24t

IN

t

I/O

24t

IN

t

I/O

24t

PRINTER MODE: PD1

Parallel port data bus bit 1. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE: nTRAK02

This pin is for Extension FDD B; the function of this pin is the

same as that of the nTRAK0 pin. This pin is pulled high

internally.

EXTENSION ADAPTER MODE: XD1

This pin is system data bus D1 for the Extension Adapter.

EXTENSION. 2FDD MODE: nTRAK02

This pin is for Extension FDD A and B; this function of this pin

is the same as nTRAK0 pin. This pin is pulled high internally.

JOYSTICK MODE: JP1

This pin is the paddle 1 input for joystick.

PD2 11 I/O

24t

IN

t

I/O

24t

IN

t

-

PRINTER MODE: PD2

Parallel port data bus bit 2. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE: nWP2

This pin is for Extension FDD B; the function of this pin is the

same as that of the nWP pin. This pin is pulled high

internally.

EXTENSION ADAPTER MODE: XD2

This pin is system data bus D2 for the Extension Adapter.

EXTENSION. 2FDD MODE: nWP2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nWP pin. This pin is pulled high

internally.

JOYSTICK MODE: NC pin

16

SYMBOL PIN I/O FUNCTION

PD3 12 I/O

24t

IN

t

I/O

24t

IN

t

-

PRINTER MODE: PD3

Parallel port data bus bit 3. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE: nRDATA2

Motor on B for Extension FDD B; the function of this pin is the

same as that of the nRDATA pin. This pin is pulled high

internally.

EXTENSION ADAPTER MODE: XD3

This pin is system data bus D3 for the Extension Adapter.

EXTENSION 2FDD MODE: nRDATA2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nRDATA pin. This pin is pulled high

internally.

JOYSTICK MODE: NC pin

PD4 13 I/O

24t

IN

t

I/O

24t

IN

t

IN

t

PRINTER MODE: PD4

Parallel port data bus bit 4. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE: nDSHCHG2

Drive select B for Extension FDD B; the function of this pin is

the same as that of nDSHCHG pin. This pin is pulled high

internally.

EXTENSION ADAPTER MODE: XD4

This pin is system data bus D4 for the Extension Adapter.

EXTENSION 2FDD MODE: nDSKCHG2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nDSKCHG pin. This pin is pulled

high internally.

JOYSTICK MODE: JB0

This pin is the button 0 input for the joystick.

17

SYMBOL PIN I/O FUNCTION

PD5 14 I/O

24t

-

I/O

24t

-

IN

t

PRINTER MODE: PD5

Parallel port data bus bit 5. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE:

This pin is a tri-state output.

EXTENSION ADAPTER MODE: XD5

This pin is system data bus D5 for the Extension Adapter

EXTENSION 2FDD MODE:

This pin is a tri-state output.

JOYSTICK MODE: JB1

This pin is the button 1 input for the joystick.

PD6 16 I/O

24t

-

I/O

24t

OD

24

-

PRINTER MODE: PD6

Parallel port data bus bit 6. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE:

This pin is a tri-state output.

EXTENSION ADAPTER MODE: XD6

This pin is system data bus D6 for the Extension Adapter

EXTENSION. 2FDD MODE: nMOA2

This pin is for Extension FDD A; its function is the same as

that of the nMOA pin.

JOYSTICK MODE: NC pin

PD7 17 I/O

24t

-

I/O

24t

OD

24

-

PRINTER MODE: PD7

Parallel port data bus bit 7. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE:

This pin is a tri-state output.

EXTENSION ADAPTER MODE: XD7

This pin is system data bus D7 for the Extension Adapter.

EXTENSION 2FDD MODE: nDSA2

This pin is for Extension FDD A; its function is the same as

that of the nDSA pin.

JOYSTICK MODE: NC pin

18

IDE and FDC Interface

SYMBOL PIN I/O FUNCTION

nRESIDE/
IRQ_G

1 OUT

12t

OUT

12t

When CR16 Bit 1 (IRIDE) = 0: Active low reset signal for

IDE;

When CR16 Bit 1 (IRIDE) = 1: Interrupt request signal G.

nIDBEN/
IRQ_H

91 OUT

12t

OUT

12t

When CR16 Bit 1 (IRIDE) = 0: Active low enable signal for

IDE;

When CR16 Bit 1 (IRIDE) = 1: Interrupt request signal H.

nCS1/

IRTX2

95 OUT

12t

OUT

12t

When CR16 Bit 1 (IRIDE) = 0: This pin is used to select the

IDE

controller. nCS1 decodes the HDC addresses specified in

CR22.

When CR16 Bit 1 (IRIDE) = 1: Function as a InfraRed

transmission data line.

nCS0/

IRRX2

94 OUT

12t

IN

t

When CR16 Bit 1 (IRIDE) = 0: This pin is used to select the

IDE

controller. nCS0 decodes HDC addresses specified in

CR21.

When CR16 Bit 1 (IRIDE) = 1: Function as a InfraRed

receiving line.

nWE 85 OD

24

Write enable. An open drain output.

nDIR 89 OD

24

Direction of the head step motor. An open drain output.

Logic 1 = outward motion

Logic 0 = inward motion

nHEAD 88 OD

24

Head select. This open drain output determines which disk

drive head is active.

Logic 1 = side 0

Logic 0 = side 1

nRWC 87 OD

24

Reduced write current. This signal can be used on two-

speed disk drives to select the transfer rate. An open drain

output.

Logic 0 = 250 Kb/s

Logic 1 = 500 Kb/s

When bit 5 of CR9 (EN3MODE) is set to high, the three-

mode FDD function is enabled, and the pin will have a

different definition. Refer to the EN3MODE bit in CR9.

nWD 86 OD

24

Write data. This logic low open drain writes

precompensation serial data to the selected FDD. An open

drain output.

nSTEP 82 OD

24

Step output pulses. This active low open drain output

produces a pulse to move the head to another track.

19

SYMBOL PIN I/O FUNCTION

nINDEX 81 IN

cs

This schmitt input from the disk drive is active low when the

head is positioned over the beginning of a track marked by

an index hole. This input pin is pulled up internally by an

approximately 1K ohm resistor. The resistor can be

disabled by bit 4 of CR6 (FIPURDWN).

nTRAK0 78 IN

cs

Track 0. This schmitt input from the disk drive is active low

when the head is positioned over the outermost track. This

input pin is pulled up internally by an approximately 1K

ohm resistor. The resistor can be disabled by bit 4 of CR6

(FIPURDWN).

nWP 77 IN

cs

Write protected. This active low schmitt input from the disk

drive indicates that the diskette is write-protected. This

input pin is pulled up internally by an approximately 1K

ohm resistor. The resistor can be disabled by bit 4 of CR6

(FIPURDWN).

nRDATA 74 IN

cs

The read data input signal from the FDD. This input pin is

pulled up internally by an approximately 1K ohm resistor.

The resistor can be disabled by bit 4 of CR6 (FIPURDWN).

nDSKCHG 76 IN

cs

Diskette change. This signal is active low at power on and

whenever the diskette is removed. This input pin is pulled

up internally by an approximately 1K ohm resistor. The

resistor can be disabled by bit 4 of CR6 (FIPURDWN).

nMOA 79 OD

24

Motor A On. When set to 0, this pin enables disk drive 0.

This is an open drain output.

nMOB 80 OD

24

Motor B On. When set to 0, this pin enables disk drive 1.

This is an open drain output.

nDSA 83 OD

24

Drive Select A. When set to 0, this pin enables disk drive A.

This is an open drain output.

nDSB 84 OD

24

Drive Select B. When set to 0, this pin enables disk drive B.

This is an open drain output.

VDD 15, 56 +5 power supply for the digital circuitry
GND 25, 40

65, 90

Ground

20

FDC FUNCTIONAL DESCRIPTION

FDC87W22 FDC

The floppy disk controller of the FDC87W22
integrates all of the logic required for floppy disk
control. The FDC implements a PC/AT or PS/2
solution. All programmable options default to
compatible values. The FIFO provides better
system performance in multi-master systems.
The digital data separator supports up to 1 M
bits/sec data rate.

The FDC includes the following blocks: AT
interface, Precompensation, Data Rate
Selection, Digital Data Separator, FIFO, and
FDC Core.

AT Interface

The interface consists of the standard
asynchronous signals: nRD, nWR, A0-A3, IRQ,
DMA control, and a data bus. The address lines
select between the configuration registers, the
FIFO and control/status registers. This interface
can be switched between PC/AT, Model 30, or

PS/2 normal modes. The PS/2 register sets are
a superset of the registers found in a PC/AT.

FIFO (Data)

The FIFO is 16 bytes in size and has
programmable threshold values. All command
parameter information and disk data transfers
go through the FIFO. Data transfers are
governed by the RQM and DIO bits in the Main
Status Register.

The FIFO defaults to disabled mode after any
form of reset. This maintains PC/AT hardware
compatibility. The default values can be
changed through the CONFIGURE command.
The advantage of the FIFO is that it allows the
system a larger DMA latency without causing
disk errors. The following tables give several
examples of the delays with a FIFO. The data
are based upon the following formula:

THRESHOLD # × (1/DATA/RATE) *8 - 1.5 µS =
DELAY

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 500K BPS

Data Rate

1 Byte

1 × 16 µS - 1.5 µS = 14.5 µS

2 Byte

2 × 16 µS - 1.5 µS = 30.5 µS

8 Byte

8 × 16 µS - 1.5 µS = 6.5 µS

15 Byte

15 × 16 µS - 1.5 µS = 238.5 µS

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 1M BPS

Data Rate

1 Byte

1 × 8 µS - 1.5 µS = 6.5 µS

2 Byte

2 × 8 µS - 1.5 µS = 14.5 µS

8 Byte

8 × 8 µS - 1.5 µS = 62.5 µS

15 Byte

15 × 8 µS - 1.5 µS = 118.5 µS

21

At the start of a command the FIFO is always
disabled and command parameters must be
sent based upon the RQM and DIO bit settings
in the main status register. When the FDC
enters the command execution phase, it clears
the FIFO of any data to ensure that invalid data
are not transferred.

An overrun and underrun will terminate the
current command and the data transfer. Disk
writes will complete the current sector by
generating a 00 pattern and valid CRC. Reads
require the host to remove the remaining data
so that the result phase may be entered.

DMA transfers are enabled with the SPECIFY
command and are initiated by the FDC by
activating the DRQ pin during a data transfer
command. The FIFO is enabled directly by
asserting nDACK and addresses need not be
valid.

Note that if the DMA controller is programmed
to function in verify mode a pseudo read is
performed by the FDC based only on nDACK.
This mode is only available when the FDC has
been configured into byte mode (FIFO disabled)
and is programmed to do a read. With the FIFO
enabled the above operation is performed by
using the new VERIFY command. No DMA
operation is needed.

Data Separator

The function of the data separator is to lock onto
the incoming serial read data. When a lock is
achieved the serial front end logic of the chip is
provided with a clock which is synchronized to
the read data. The synchronized clock, called
the Data Window, is used to internally sample
the serial data portion of the bit cell, and the
alternate state samples the clock portion. Serial
to parallel conversion logic separates the read
data into clock and data bytes.

The Digital Data Separator (DDS) has three
parts: control logic, error adjustment, and speed
tracking. The DDS circuit cycles once every 12
clock cycles ideally. Any data pulse input will be
synchronized and then adjusted by immediate
error adjustment. The control logic will generate
RDD and RWD for every pulse input. During any
cycle where no data pulse is present, the DDS
cycles are based on speed. A digital integrator is
used to keep track of the speed changes in the
input data stream.

Write Precompensation

The write precompensation logic is used to
minimize bit shifts in the RDDATA stream from
the disk drive. Shifting of bits is a known
phenomenon in magnetic media and is
dependent on the disk media and the floppy
drive.

The FDC monitors the bit stream that is being
sent to the drive. The data patterns that require
precompensation are well known. Depending
upon the pattern, the bit is shifted either early or
late relative to the surrounding bits.

Perpendicular Recording Mode

The FDC is also capable of interfacing directly
to perpendicular recording floppy drives.
Perpendicular recording differs from the
traditional longitudinal method in that the
magnetic bits are oriented vertically. This
scheme packs more data bits into the same
area.

FDCs with perpendicular recording drives can
read standard 3.5" floppy disks and can read
and write perpendicular media. Some
manufacturers offer drives that can read and
write standard and perpendicular media in a
perpendicular media drive.

22

A single command puts the FDC into
perpendicular mode. All other commands
operate as they normally do. The perpendicular
mode requires a 1 Mbps data rate for the FDC.
At this data rate the FIFO eases the host
interface bottleneck due to the speed of data
transfer to or from the disk.

FDC Core

The FDC87W22 FDC is capable of performing
twenty commands. Each command is initiated
by a multi-byte transfer from the
microprocessor. The result can also be a multi-

byte transfer back to the microprocessor. Each
command consists of three phases: command,
execution, and result.
Command
The microprocessor issues all required
information to the controller to perform a
specific operation.
Execution
The controller performs the specified operation.
Result
After the operation is completed, status
information and other housekeeping information
is provided to the microprocessor.

23

FDC Commands

Command Symbol Descriptions:
C: Cylinder number 0 - 256
D: Data Pattern
DIR: Step Direction
DIR = 0, step out
DIR = 1, step in
DS0: Disk Drive Select 0
DS1: Disk Drive Select 1
DTL: Data Length
EC: Enable Count
EOT: End of Track
EFIFO: Enable FIFO
EIS: Enable Implied Seek
EOT: End of track
FIFOTHR: FIFO Threshold
GAP: Gap length selection
GPL: Gap Length
H: Head number
HDS: Head number select
HLT: Head Load Time
HUT: Head Unload Time
LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset
MFM: MFM or FM Mode
MT: Multitrack
N: The number of data bytes written in a sector
NCN: New Cylinder Number
ND: Non-DMA Mode
OW: Overwritten
PCN: Present Cylinder Number
POLL: Polling Disable
PRETRK: Precompensation Start Track Number
R: Record
RCN: Relative Cylinder Number
R/W: Read/Write
SC: Sector/per cylinder
SK: Skip deleted data address mark
SRT: Step Rate Time
ST0: Status Register 0
ST1: Status Register 1
ST2: Status Register 2
ST3: Status Register 3
WG: Write gate alters timing of WE

24

(1) Read Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 0 1 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0
W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID
information prior
to command

execution
W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD
and system

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command

execution

25

(2) Read Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 1 1 0 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0
W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID

information prior

to command

execution

W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD
and system

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command

execution

26

(3) Read A Track

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 0 0 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0
W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID
information prior to

command execution
W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD
and system; FDD
reads contents of all
cylinders from index
hole to EOT

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command execution

27

(4) Read ID

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 0 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0

Execution The first correct ID

information on the
cylinder is stored
in Data Register

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Disk status after

the command has

been completed

(5) Verify

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 1 0 1 1 0 Command codes

W EC 0 0 0 0 HDS DS1 DS0
W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID

information prior to

command

execution
W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL/SC -------------------

Execution No data transfer

takes place

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command

execution

28

(6) Version

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 0 0 Command code
Result R 1 0 0 1 0 0 0 0 Enhanced

controller

(7) Write Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 0 1 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0
W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID

information prior to

Command

execution

W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD
and system

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after Command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

Command

execution

29

(8) Write Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 1 0 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0
W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID

information prior to

command

execution
W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

Execution Data transfer

between the FDD
and system

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command

execution

(9) Format A Track

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 1 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0
W
W

---------------------- N ------------------------

--------------------- SC -----------------------

Bytes/Sector

Sectors/Cylinder
W
W

--------------------- GPL ---------------------

---------------------- D ------------------------

Gap 3

Filler Byte

Execution
for Each
Sector
Repeat:

W
W
W
W

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Input Sector

Parameters

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information

after command

execution

R
R
R
R

---------------- Undefined -------------------

---------------- Undefined -------------------

---------------- Undefined -------------------

---------------- Undefined -------------------

30

(10) Recalibrate

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 1 1 Command codes

W 0 0 0 0 0 0 DS1 DS0

Execution Head retracted to

Track 0 Interrupt

(11) Sense Interrupt Status

PHASE R/W D7 76 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 0 0 0 Command code
Result R

R

---------------- ST0 -------------------------

---------------- PCN -------------------------

Status information at
the end of each seek
operation

(12) Specify

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 0 1 1 Command codes

W
W

| ---------SRT ----------- | --------- HUT ---------- |

|------------ HLT ----------------------------------| ND

(13) Seek

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 1 1 1 Command codes

W
W

0 0 0 0 0 HDS DS1 DS0

-------------------- NCN -----------------------

Execution R Head positioned

over proper cylinder
on diskette

(14) Configure

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 1 1 Configure

information
W
W
W

0 0 0 0 0 0 0 0

0 EIS EFIFO POLL | ------ FIFOTHR ----|

| --------------------PRETRK ---------------------- |

Execution Internal registers

written