Standard Microsystems Corporation FDC87W21 Datasheet

FDC87W21

Power I/O Controller with Fast Infrared Support

FEATURES

• 5 Volt Operation

• Plug & Play 1.0A Compliant

• Supports Eight IRQs, Four DMA Channels,

480 Relocatable Addresses

• Floppy Disk Controller (FDC)

- Compatible with IBM PC/AT Disk Drive
Systems

- Variable Write Precompensation with
Track Selectable Capability

- DMA Enable Logic

- Supports Floppy Disk Drives and Tape

Drives

- Detects All Over-Run and Under-Run
Conditions

- Data Rate and Drive Control Registers

- Built-in Address Mark Detection Circuit

to Simplify the Read Electronics

- IBM PC System Address Decoder

- 24 MHz Crystal Input (48 MHz when for

2 Mbps Fast Tape Drive)

- FDD Anti-Virus Functions with Software
Write Protect and FDD Write Enable
Signal (Write Data Signal Was Forced
to Be Inactive)

- Supports up to Four 3.5-Inch or 5.25­Inch Floppy Disk Drives

- Completely Compatible with Industry
Standard 82077/ 765A

- Supports
360K/720K/1.2M/1.44M/2.88M Format;
250 Kbps, 300 Kbps, 500 Kbps, 1
Mbps, 2 Mbps Data Transfer Rate

- Supports Perpendicular Recording
Format

- Supports 3-Mode FDD and Win95
Driver

- 16-Byte Data FIFOs

• Serial Ports

- Two High-Speed 16550 Compatible
UARTs with 16-Byte Send/Receive
FIFOs

- MIDI Compatible

- Fully Programmable Serial-Interface

Characteristics:

- 5, 6, 7 or 8-Bit Characters

- Even, Odd or No Parity Bit

Generation/Detection

- 1, 1.5 or 2 Stop Bits Generation

- Internal Diagnostic Capabilities:

- Loop-Back Controls For

Communications Link Fault
Isolation

- Break, Parity, Overrun, Framing

Error Simulation

- Programmable Baud Generator Allows
Division of 1.8461 MHz and 24 MHz by
1 to (216-1)

- Maximum Baud Rate Is up to 911.6 (8
times of 115.2 Kbps) for 1.8461 MHz
and 1.5 Mbps for 24 MHz

• Infrared

- Supports IrDA Version 1.0 SIR Protocol
with Maximum Baud Rate up to 115.2
Kbps

- Supports SHARP ASK-IR Protocol with
Maximum Baud Rate up to 57600 bps

- Supports IrDA Version 1.1 MIR (1.152
Mbps) and FIR (4 Mbps) Protocol

- Two DMA Channel for Transmitter

and Receiver

- 32-Byte FIFO is Supported in the

TX/RX Terminal

2

- 8-Byte Status FIFO Is Supported
to Store Received Frame Status
(Such as Overrun, CRC Error,
Etc.)

- Supports Auto-Config SIR and FIR

• Parallel Port

- Compatible with IBM Parallel Port

- Supports Parallel Port with Bi-

Directional Lines

- Supports Enhanced Parallel Port (EPP)

− Compatible with IEEE 1284

Specification

- Supports Extended Capabilities Port
(ECP) − Compatible with IEEE 1284
Specification

- Extension FDD Mode Supports Disk
Drive B; and Extension 2FDD Mode

Supports Disk Drives A and B Through
Parallel Port

- Extension Adapter Mode Supports
Pocket Devices Through Parallel Port

- JOYSTICK Mode Supports Joystick
Through Parallel Port

• ISA Host Interface

• IDE

- Supports up to Two Embedded Hard
Disk Drives (IDE AT BUS)

• Programmable Configuration Settings

• Immediate or Automatic Power-Down Mode

for Power Management

• All Hardware Power-On Settings Have
Internal Pull-Up or Pull-Down Resistors as
Default Value

• 100 Pin QFP Package

GENERAL DESCRIPTION

The FDC87W21 is an enhanced version of the
FDC87W22 --- which integrates the disk drive
adapter, serial port (UART), IrDA 1.0 SIR,
parallel port, IDE interface, configurable plug­and-play registers for the whole chip --- adding
powerful features: IrDA 1.1 (MIR for 1.152 Mbps
or FIR for 4 Mbps), TV remote IR. In addition to
the function enhancement, FDC87W21 is pin-to­pin compatible to FDC87W22.

The disk drive adapter functions of the
FDC87W21 include a floppy disk drive controller
compatible with the industry standard
82077/765 data separator, write pre­compensation circuit, decode logic, data rate
selection, clock generator, drive interface control
logic, interrupt and DMA logic. The wide range
of functions integrated into the FDC87W21
greatly reduces the number of components
required for interfacing with floppy disk drives.
The FDC87W21 supports up to 4 Three-mode
Floppy Disk Drives (FDD) of formats 360K,
720K, 1.2M, 1.44M, or 2.88M, and data transfer
rates of 250 Kbps, 300 Kbps, 500 Kbps, 1
Mbps, and 2 Mbps.

The FDC87W21 provides two high-speed serial
communication ports (UARTs), one of which
supports serial Infrared communication. Each

UART includes a 16-byte send/receive FIFO, a
programmable baud rate generator, complete
modem control capability, and a processor
interrupt system. One of UART supports infrared
(IR) includes 32-byte FIFO, serial IR (115, 200
bps), MIR (1.152 Mbps or 0.576 Mbps), FIR (4
Mbps), and TV remote IR (supported NEC, RC­5, extended RC-5, and RECS-80 protocols).

The FDC87W21 supports one PC-compatible
printer port (SPP), bi-directional Printer Port
(BPP), and also Enhanced Parallel Port (EPP)
and Extended Capabilities Port (ECP).

Through the printer port interface pins, also
available are: Extension FDD Mode and
Extension 2FDD Mode allowing one or two
external floppy disk drives to be attached.
Especially in the application of notebook
computer, this feature is very useful.

The Extension Adapter Mode of the FDC87W21
also allows pocket devices to be installed
through the printer interface pins in notebook
computer applications according to a protocol
set by SMSC, but with upgraded performance.
The JOYSTICK mode allows a joystick to be
connected to a parallel port with a signal
switching cable.

3

The FDC87W21 supports two embedded hard
disk drive (IDE AT bus) interfaces and a game
port with decoded read/write output.

The configuration registers support mode
selection, function enable/disable, and power
down function selection. Moreover, the
configurable PnP registers are compatible with

the plug-and-play feature in Windows 95,
which makes system resource allocation more
efficient than ever.

Standard Microsystems is a registered trademark and
SMSC is a trademark of Standard Microsystems
Corporation. Other product and company names are
trademarks or registered trademarks of their respective
holders.

4

TABLE OF CONTENTS

FEATURES....................................................................................................................................... 1

GENERAL DESCRIPTION ................................................................................................................ 2

PIN CONFIGURATION...................................................................................................................... 6

PIN DESCRIPTION ........................................................................................................................ 7

HOST INTERFACE..............................................................................................................................7

FDC FUNCTIONAL DESCRIPTION................................................................................................. 17

FDC87W21 FDC..........................................................................................................................17

REGISTER DESCRIPTIONS........................................................................................................ 31

IDE.................................................................................................................................................. 42

IDE DECODE DESCRIPTION .............................................................................................................. 42

UART PORT ................................................................................................................................... 43

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)............................................ 43

REGISTER ADDRESS........................................................................................................................ 43

IR PORT........................................................................................................................................ 54

PARALLEL PORT........................................................................................................................... 83

PRINTER INTERFACE LOGIC ..................................................................................................... 83

ENHANCED PARALLEL PORT (EPP)..........................................................................................85

EXTENDED CAPABILITIES PARALLEL (ECP) PORT.................................................................. 89

EXTENSION FDD MODE (EXTFDD).................................................................................................. 98

EXTENSION 2FDD MODE (EXT2FDD) .............................................................................................. 98

EXTENSION ADAPTER MODE (EXTADP) (PATENT PENDING) ................................................................. 98

JOYSTICK MODE (PATENT PENDING)................................................................................................... 99

GAME PORT DECODER ...............................................................................................................100

PLUG AND PLAY CONFIGURATION ............................................................................................100

EXTENDED FUNCTION REGISTERS ............................................................................................100

EXTENDED FUNCTIONS ENABLE REGISTERS (EFERS)..........................................................................101

EXTENDED FUNCTION INDEX REGISTERS (EFIRS), EXTENDED FUNCTION DATA REGISTERS (EFDRS) ........101

BIT MAP CONFIGURATION REGISTERS ...............................................................................................137

SPECIFICATIONS..........................................................................................................................139

ABSOLUTE MAXIMUM RATINGS..........................................................................................................139

DC CHARACTERISTICS .............................................................................................................139

AC CHARACTERISTICS....................................................................................................................141

TIMING WAVEFORMS ..................................................................................................................147

FDC............................................................................................................................................147

UART/PARALLEL...........................................................................................................................149

MODEM CONTROL TIMING................................................................................................................150

PARALLEL PORT.............................................................................................................................151

PARALLEL PORT TIMING ..................................................................................................................151

EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.9)..................................................................152

EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.9)................................................................153

EPP DATA OR ADDRESS READ CYCLE (EPP VERSION 1.7)..................................................................154

5

EPP DATA OR ADDRESS WRITE CYCLE (EPP VERSION 1.7)................................................................155

PARALLEL PORT FIFO TIMING .........................................................................................................155

ECP PARALLEL PORT FORWARD TIMING ...........................................................................................156

ECP PARALLEL PORT REVERSE TIMING.............................................................................................156

EXTENSION ADAPTER MODE COMMAND CYCLE ...................................................................................157

EXTENSION ADAPTER MODE INTERRUPT CYCLE..................................................................................157

EXTENSION ADAPTER MODE DMA CYCLE..........................................................................................158

APPLICATION CIRCUITS..............................................................................................................158

PARALLEL PORT EXTENSION FDD ....................................................................................................158

PARALLEL PORT EXTENSION FDD ....................................................................................................159

PARALLEL PORT EXTENSION 2FDD ..................................................................................................160

PARALLEL PORT JOYSTICK MODE .....................................................................................................161

FOUR FDD MODE..........................................................................................................................161

PACKAGE DIMENSIONS ..............................................................................................................162

80 Arkay Drive
Hauppauge, NY 11788
[phone]
FAX [phone]

6

PIN CONFIGURATION

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

nINDEX

nSTEP

nDSA
nDSB

nWE
nWD

nRWC

nHEAD

nDIR
GND

nIDBEN

IRQ_B

nIRQIN

nCS0
nCS1

IRQ_A

TC

nDACK_B

IRQ_F

DRQ_B

nMOB

nMOA

nTRAK0

NWP

nDSKCHG

A10

nRDATAD7D6D5D4D3D2D1D0

GND

nIOW

nIOR

AENA9A8A7A6A5VDDA4A3A2A1

A0

8079787776757473727170696867666564636261605958575655545352

51

nRIB
nDCDB
nDSRB
nCTSB
nDTRB
nRTSB
IRQ_C
SOUTB
SINB
nGMRD
GND
nGMWR
SOUTA
IRQ_D
nRTSA
nDTRA
nCTSA
nDSRA
nDCDA
nRIA

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

1234567891011121314151617181920212223242526272829

30

nRESIDE

nCS

nPDCIN

DRQ_C

IOCHRDY

MR

XTAL1

XTAL2

PD0

PD1

PD2

PD3

PD4

PD5

VDD

PD6

PD7

nDACK_C

nSTB

nAFD

nINIT

nSLIN

IRQ_E

BUSY

GND

nACK

PE

SLCT

nERR

SINA

FDC87W21

PIN DESCRIPTION

(Note: Refer to the DC Characteristics Section for details.)
I/O8tc TTL level output pin with 8 mA source-sink capability; CMOS level input voltage

I/O12t TTL level bi-directional pin with 12 mA source-sink capability
I/O24t TTL level bi-directional pin with 24 mA source-sink capability
OUT8t TTL level output pin with 8 mA source-sink capability
OUT12t TTL level output pin with 12 mA source-sink capability
OD12 Open-drain output pin with 12 mA sink capability
OD24 Open-drain output pin with 24 mA sink capability
INt TTL level input pin
INts TTL level Schmitt-triggered input pin
INc CMOS level input pin
INcs CMOS level Schmitt-triggered input pin

Host Interface

SYMBOL PIN I/O FUNCTION

HOST INTERFACE

D0−D7

66-73 I/O

24t

System data bus bits 0-7

A0−A9

51-55
57-61

IN

t

System address bus bits 0-9

A10 75 IN

t

In ECP Mode, this pin is the A10 address input.

IOCHRDY 5 OD

24

In EPP Mode, this pin is the IO Channel Ready output to extend the
host read/write cycle.

MR 6 IN

ts

Master Reset. Active high. MR is low during normal operations.
nCS
nDACK_N
IRSL1
IRSL2

2 IN

t

IN

t

OUT

12t

OUT

12t

Active low chip select signal.

DMA acknowledge signal D.

IR module mode select 1.

IR module mode select 2.
AEN 62 IN

t

System address bus enable
nIOR 63 IN

ts

CPU I/O read signal
nIOW 64 IN

ts

CPU I/O write signal
DRQ_B 100 OUT

12t

DMA request signal B
nDACK_B 98 IN

ts

DMA Acknowledge signal B
DRQ_C 4 OUT

12t

DMA request signal C
nDACK_C 18 IN

ts

DMA Acknowledge signal C
TC 97 IN

ts

Terminal Count. When active, this pin indicates termination of a

DMA transfer.
IRQIN
DRQ_D
IRSL2
IRRXH/
IRSL0

93 IN

t

OUT

12t

OUT

12t

I/O

12t

Interrupt request input.

DMA request signal D.

IR module mode selection 2.

When input, act as a function of high speed IR receiving terminal.

When output selected, act as a IR module mode selection 0.
IRQ_A
GIO1

96 OUT

12t

I/O

12t

When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal A;

When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port 1.
IRQ_B
GIO0

92 OUT

12t

I/O

12t

When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal B;

When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port 0.
IRQ_C 44 OUT

12t

Interrupt request signal C

8

SYMBOL PIN I/O FUNCTION

IRQ_D 37 OUT

12t

Interrupt request signal D
IRQ_E 23 OUT

12t

Interrupt request signal E
IRQ_F 99 OUT

12t

Interrupt request signal F
XTAL1 7 CLK IN XTAL oscillator input
XTAL2 8 CLK

OUT

XTAL oscillator output

SERIAL PORT INTERFACE

nCTSA
nCTSB

34
47

IN

t

IN

t

Clear To Send is the modem control input.

The function of these pins can be tested by reading Bit 4 of the

handshake status register.
nDSRA
nDSRB

33
48

IN

t

IN

t

Data Set Ready. An active low indicates the modem or data set is

ready to establish a communication link and transfer data to the

UART.
nDCDA
nDCDB

32
49

IN

t

IN

t

Data Carrier Detect. An active low indicates the modem or data set

has detected a data carrier.
nRIA
nRIB

31
50

IN

t

IN

t

Ring Indicator. An active low indicates that a ring signal is being

received by the modem or data set.
SINA
SINB/
IRRX1

30
42

IN

t

IN

t

Serial Input. Used to receive serial data from the communication

link.
SOUTA
PIN2IPSEL

38 O

8tc

I

8tc

UART A Serial Output. Used to transmit serial data out to the

communication link.

During power-on reset, this pin is pulled up internally and is defined

as PIN2IPSEL, which provides the power-on value for CR16 bit 1

(PIN2IPSEL). A 4.7 k is recommended when intends to pull down

at power-on reset.
SOUTB
IRTX1
PGMDRQ

43 O

8tc

O

8tc

I

8tc

UART B Serial Output. Used to transmit serial data out to the

communication link.

During power-on reset, this pin is pulled down internally and is

defined as PGMDRQ, which provides the power-on value for CR16

bit 3 (GMDRQ). A 4.7 k is recommended when intends to pull up

at power-on reset.
nDTRA

PHEFRAS

35 O

8tc

I

8tc

UART A Data Terminal Ready. An active low informs the modem

or data set that the controller is ready to communicate.

During power-on reset, this pin is pulled down internally and is

defined as PHEFRAS, which provides the power-on value for CR16

bit 0 (HEFRAS). A 4.7 k is recommended when intends to pull up

at power-on reset.
nDTRB 46 O

8t

UART B Data Terminal Ready. An active low informs the modem

or data set that controller is ready to communicate.
nRTSA

PPNPCVS

36 O

8tc

I

8tc

UART A Request To Send. An active low informs the modem or

data set that the controller is ready to send data.

During power-on reset, this pin is pulled up internally and is defined

as PPNPCVS, which provides the power-on value for CR16 bit 2

(PNPCVS). A 4.7 k is recommended when intends to pull down

at power-on reset.

9

SYMBOL PIN I/O FUNCTION

nRTSB
PGOIQSEL

45 O

8tc

I

8tc

UART B Request To Send. An active low informs the modem or

data set that the controller is ready to send data.

During power-on reset, this pin is pulled down internally and is

defined as PGOIQSEL, which provides the power-on value for

CR16 bit 4 (GOIQSEL). A 4.7 k is recommended when intends to

pull up at power-on reset.

Game Port/Power Down Interface

If Bit 3 of CR16 (GMDRQ) is 1, Bit 4 of CR3 (GMODS0) determines whether the game port is in
Adapter mode or Portable mode (default is Adapter mode). If Bit 3 of CR16 is 0, pin 39 and 41 are
used for DMA A operation.
nGMRD 41 OUT8tWhen CR16 Bit 3 (GMDRQ) = 1, Adapter mode: Game port read

control signal.
PFDCEN OUT8tPortable mode: When parallel port is selected as Extension

FDD/Extension 2FDD mode, this pin will be active. The active state

is dependent on bit 7 of CRA (PFDCACT), and default is low active.
nDACK_A IN

t

When CR16 Bit 3 (GMDRQ) = 0, DMA acknowledge signal A.
nGMWR 39 OUT8tWhen CR16 Bit 3 (GMDRQ) = 1, Adapter mode: Game port write

control signal.
PEXTEN OUT8tPortable mode: When a particular extended mode is selected for

the parallel port, this pin will be active. The extended modes

include Extension Adapter mode, EPP mode, ECP mode, and

ECP/EPP mode, which are selected using bit 3 - bit 0 of CRA. The

active state is dependent on bit 6 of CRA (PEXTACT); the default is

low active.
DRQ_A OUT8tWhen CR16 Bit 3 (GMDRQ) = 0: DMA request signal A.
PDCIN 3 IN

t

This input pin controls the chip power down. When this pin is

active, the clock supply to the chip will be inhibited and the output

pins will be tri-stated as defined in CR4 and CR6. The PDCIN is

pulled down internally. Its active state is defined by bit 4 of CRA

(PDCHACT). Default is high active.
nDACK_N IN

t

DMA acknowledge signal D.
IRSL1 OUT

12t

IR module mode select 1.
IRRXH/
IRSL0

I/O

12t

When input pin, high speed IR received terminal. When as output

pin, IR module mode select 0. Input or output are definied in high

speed IR register.

Multi-Mode Parallel Port

The following pins have eight functions, which are controlled by bits PRTMOD0, PRTMOD1, and
PRTMOD2 of CR0 and CR9. (Refer to the Extended Functions Section).

10

SYMBOL PIN I/O FUNCTION

BUSY 24 IN

t

OD

12

IN

t

OD

12

-

PRINTER MODE: BUSY

An active high input indicates that the printer is not ready to receive

data. This pin is pulled high internally. Refer to the description of

the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nMOB2

This pin is for Extension FDD B; the function of this pin is the same

as that of the nMOB pin.

EXTENSION ADAPTER MODE: XIRQ

This pin is an interrupt request generated by the Extension Adapter

and is an active high input.

EXTENSION 2FDD MODE: nMOB2

This pin is for Extension FDD A and B; the function of this pin is the

same as that of the nMOB pin.

JOYSTICK MODE: NC pin.
nACK 26 IN

t

OD

12

IN

t

OD

12

-

PRINTER MODE: nACK

An active low input on this pin indicates that the printer has

received data and is ready to accept more data. This pin is pulled

high internally. Refer to the description of the parallel port for the

definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nDSB2

This pin is for the Extension FDD B; its functions are the same as

those of the nDSB pin.

EXTENSION ADAPTER MODE: XDRQ

DMA request generated by the Extension Adapter. An active high

input.

EXTENSION 2FDD MODE: nDSB2

This pin is for Extension FDD A and B; this function of this pin is

the same as that of the nDSB pin.

JOYSTICK MODE: NC pin.
PE 27 IN

t

OD

12

OUT

12t

OD

12

-

PRINTER MODE: PE

An active high input on this pin indicates that the printer has

detected the end of the paper. This pin is pulled high internally.

Refer to the description of the parallel port for the definition of this

pin in ECP and EPP mode.

EXTENSION FDD MODE: nWD2

This pin is for Extension FDD B; its function is the same as that of

the nWD pin.

EXTENSION ADAPTER MODE: XA0

This pin is system address A0 for the Extension Adapter

EXTENSION 2FDD MODE: nWD2

This pin is for Extension FDD A and B; this function of this pin is

the same as that of the nWD pin.

JOYSTICK MODE: NC pin.

11

SYMBOL PIN I/O FUNCTION

SLCT 28 IN

t

OD

12

OUT

12t

OD

12

-

PRINTER MODE: SLCT

An active high input on this pin indicates that the printer is selected.

This pin is pulled high internally. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: WE2

This pin is for Extension FDD B; its functions are the same as

those of the nWE pin.

EXTENSION ADAPTER MODE: XA1

This pin is system address A1 for the Extension Adapter.

EXTENSION 2FDD MODE: nWE2

This pin is for Extension FDD A and B; this function of this pin is

the same as that of the nWE pin.

JOYSTICK MODE: NC pin.
nERR 29 IN

t

OD

12

OUT

12t

OD

12

-

PRINTER MODE: nERR

An active low input on this pin indicates that the printer has

encountered an error condition. This pin is pulled high internally.

Refer to the description of the parallel port for the definition of this

pin in ECP and EPP mode.

EXTENSION FDD MODE: nHEAD2

This pin is for Extension FDD B; its function is the same as that of

the nHEAD pin.

EXTENSION ADAPTER MODE: XA2

This pin is system address A2 for the Extension Adapter.

EXTENSION 2FDD MODE: nHEAD2

This pin is for Extension FDD A and B; its function is the same as

that of the nHEAD pin.

JOYSTICK MODE: NC pin.
nSLIN 22 OD

12

OD

12

OUT

12t

OD

12

OUT

12t

PRINTER MODE: nSLIN

Output line for detection of printer selection. This pin is pulled high

internally. Refer to the description of the parallel port for the

definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nSTEP2

This pin is for Extension FDD B; its function is the same as that of

the nSTEP pin.

EXTENSION ADAPTER MODE: XTC

This pin is the DMA terminal count for the Extension Adapter. The

count is sent by TC directly.

EXTENSION 2FDD MODE: nSTEP2

This pin is for Extension FDD A and B; its function is the same as

that of the nSTEP pin.

JOYSTICK MODE: VDD for joystick.

12

SYMBOL PIN I/O FUNCTION

nINIT 21 OD

12

OD

12

OUT

12t

OD

12

OUT

12t

PRINTER MODE: nINIT

Output line for the printer initialization. This pin is pulled high

internally. Refer to the description of the parallel port for the

definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nDIR

This pin is for Extension FDD B; its function is the same as that of

the nDIR pin.

EXTENSION ADAPTER MODE: nXDACK

This pin is the DMA acknowledge output for the Extension Adapter;

the output is sent directly from nPDACKX.

EXTENSION 2FDD MODE: nDIR2

This pin is for Extension FDD A and B; its function is the same as

that of the nDIR pin.

JOYSTICK MODE: VDD for joystick.
nAFD 20 OD

12

OD

12

OUT

12t

OD

12

OUT

12t

PRINTER MODE: nAFD

An active low output from this pin causes the printer to auto feed a

line after a line is printed. This pin is pulled high internally. Refer to

the description of the parallel port for the definition of this pin in

ECP and EPP mode.

EXTENSION FDD MODE: nRWC2

This pin is for Extension FDD B; its function is the same as that of

the nRWC pin.

EXTENSION ADAPTER MODE: nXRD

This pin is the I/O read command for the Extension Adapter.

When the Extension Adapter base address is written to the

Extension Adapter address register, nXRD and nXWR go low

simultaneously so that the command register on the Extension

Adapter can latch the same base address.

EXTENSION 2FDD MODE: nRWC2

This pin is for Extension FDD A and B; its function is the same as

that of the nRWC pin.

JOYSTICK MODE: VDD for joystick.
nSTB 19 OD

12

-

OUT

12t

-

OUT

12t

PRINTER MODE: nSTB

An active low output is used to latch the parallel data into the

printer. This pin is pulled high internally. Refer to the description of

the parallel port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.

EXTENSION ADAPTER MODE: nXWR

This pin is the I/O write command for the Extension Adapter. When

the Extension Adapter base address is written to the Extension

Adapter address register, nXRD and nXWR go low simultaneously

so that the command register on the Extension Adapter can latch

the same base address.

EXTENSION 2FDD MODE: This pin is a tri-state output.

JOYSTICK MODE: VDD for joystick.

13

SYMBOL PIN I/O FUNCTION

PD0 9 I/O

24t

IN

t

I/O

24t

IN

t

I/O

24t

PRINTER MODE: PD0

Parallel port data bus bit 0. Refer to the description of the parallel

port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nINDEX2

This pin is for Extension FDD B; the function of this pin is the same

as that of the nINDEX pin. This pin is pulled high internally.

EXTENSION ADAPTER MODE: XD0

This pin is system data bus D0 for the Extension Adapter.

EXTENSION 2FDD MODE: nINDEX2

This pin is for Extension FDD A and B; this function of this pin is

the same as nINDEX pin. This pin is pulled high internally.

JOYSTICK MODE: JP0

This pin is the paddle 0 input for joystick.
PD1 10 I/O

24t

IN

t

I/O

24t

IN

t

I/O

24t

PRINTER MODE: PD1

Parallel port data bus bit 1. Refer to the description of the parallel

port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nTRAK02

This pin is for Extension FDD B; the function of this pin is the same

as that of the nTRAK0 pin. This pin is pulled high internally.

EXTENSION ADAPTER MODE: XD1

This pin is system data bus D1 for the Extension Adapter.

EXTENSION. 2FDD MODE: nTRAK02

This pin is for Extension FDD A and B; this function of this pin is

the same as nTRAK0 pin. This pin is pulled high internally.

JOYSTICK MODE: JP1

This pin is the paddle 1 input for joystick.
PD2 11 I/O

24t

IN

t

I/O

24t

IN

t

-

PRINTER MODE: PD2

Parallel port data bus bit 2. Refer to the description of the parallel

port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nWP2

This pin is for Extension FDD B; the function of this pin is the same

as that of the nWP pin. This pin is pulled high internally.

EXTENSION ADAPTER MODE: XD2

This pin is system data bus D2 for the Extension Adapter.

EXTENSION. 2FDD MODE: nWP2

This pin is for Extension FDD A and B; this function of this pin is

the same as that of the nWP pin. This pin is pulled high internally.

JOYSTICK MODE: NC pin

14

SYMBOL PIN I/O FUNCTION

PD3 12 I/O

24t

IN

t

I/O

24t

IN

t

-

PRINTER MODE: PD3

Parallel port data bus bit 3. Refer to the description of the parallel

port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nRDATA2

Motor on B for Extension FDD B; the function of this pin is the

same as that of the nRDATA pin. This pin is pulled high internally.

EXTENSION ADAPTER MODE: XD3

This pin is system data bus D3 for the Extension Adapter.

EXTENSION 2FDD MODE: nRDATA2

This pin is for Extension FDD A and B; function of this pin is the

same as that of the nRDATA pin. This pin is pulled high internally.

JOYSTICK MODE: NC pin
PD4 13 I/O

24t

IN

t

I/O

24t

IN

t

IN

t

PRINTER MODE: PD4

Parallel port data bus bit 4. Refer to the description of the parallel

port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nDSKCHG2

Drive select B for Extension FDD B; the function of this pin is the

same as that of nDSKCHG pin. This pin is pulled high internally.

EXTENSION ADAPTER MODE: XD4

This pin is system data bus D4 for the Extension Adapter.

EXTENSION 2FDD MODE: nDSKCHG2

This pin is for Extension FDD A and B; this function of this pin is

the same as that of the nDSKCHG pin. This pin is pulled high

internally.

JOYSTICK MODE: JB0

This pin is the button 0 input for the joystick.
PD5 14 I/O

24t

-

I/O

24t

-

IN

t

PRINTER MODE: PD5

Parallel port data bus bit 5. Refer to the description of the parallel

port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.

EXTENSION ADAPTER MODE: XD5

This pin is system data bus D5 for the Extension Adapter.

EXTENSION 2FDD MODE: This pin is a tri-state output.

JOYSTICK MODE: JB1

This pin is the button 1 input for the joystick.
PD6 16 I/O

24t

-

I/O

24t

OD

24

-

PRINTER MODE: PD6

Parallel port data bus bit 6. Refer to the description of the parallel

port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.

EXTENSION ADAPTER MODE: XD6

This pin is system data bus D6 for the Extension Adapter.

EXTENSION. 2FDD MODE: nMOA2

This pin is for Extension FDD A; its function is the same as that of

the nMOA pin.

JOYSTICK MODE: NC pin

15

SYMBOL PIN I/O FUNCTION

PD7 17 I/O

24t

-

I/O

24t

OD

24

-

PRINTER MODE: PD7

Parallel port data bus bit 7. Refer to the description of the parallel

port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: This pin is a tri-state output.

EXTENSION ADAPTER MODE: XD7

This pin is system data bus D7 for the Extension Adapter.

EXTENSION 2FDD MODE: nDSA2

This pin is for Extension FDD A; its function is the same as that of

the nDSA pin.

JOYSTICK MODE: NC pin

IDE AND FDC INTERFACE

nRESIDE
IRQ_G
DRQ_D
IRSL2

1 OUT

12t

OUT

12t

OUT

12t

OUT

12t

When CR16 Bit 1 (IRIDE) = 0: Active low reset signal for IDE;

When CR16 Bit 1 (IRIDE) = 1: Interrupt request signal G.

DMA request signal.

IR module mode select 2.
nIDBEN
IRQ_H
IRSL2
nDACK_N
IRRXH/
IRSL0

91 OUT

12t

OUT

12t

OUT

12t

IN

t

I/O

12t

When CR16 Bit 1 (IRIDE) = 0: Active low enable signal for IDE;

When CR16 Bit 1 (IRIDE) = 1: Interrupt request signal H.

IR module mode selection 2.

DMA acknowledge signal D.

When input selected, act as high speed IR receiving terminal.

When output selected, act as IR module mode selection 0.
nCS1

IRTX2

95 OUT

12t

OUT

12t

When CR16 Bit 1 (IRIDE) = 0: This pin is used to select the IDE

controller. nCS1 decodes the HDC addresses specified in CR22.

When CR16 Bit 1 (IRIDE) = 1: Function as a InfraRed transmission

data line.
nCS0

IRRX2

94 OUT

12t

IN

t

When CR16 Bit 1 (IRIDE) = 0: This pin is used to select the IDE

controller. nCS0 decodes HDC addresses specified in CR21.

When CR16 Bit 1 (IRIDE) = 1: Function as a InfraRed receiving

line.
nWE 85 OD

24

Write enable. An open drain output.
nDIR 89 OD

24

Direction of the head step motor. An open drain output.

Logic 1 = outward motion

Logic 0 = inward motion
nHEAD 88 OD

24

Head select. This open drain output determines which disk drive

head is active.

Logic 1 = side 0

Logic 0 = side 1
nRWC 87 OD

24

Reduced write current. This signal can be used on two-speed disk

drives to select the transfer rate. An open drain output.

Logic 0 = 250 Kbps

Logic 1 = 500 Kbps

When bit 5 of CR9 (EN3MODE) is set to high, the three-mode

FDD function is enabled, and the pin will have a different definition.

Refer to the EN3MODE bit in CR9.
nWD 86 OD

24

Write data. This logic low open drain writes precompensation serial

data to the selected FDD. An open drain output.
nSTEP 82 OD

24

Step output pulses. This active low open drain output produces a

pulse to move the head to another track.

16

SYMBOL PIN I/O FUNCTION

nINDEX 81 IN

cs

This schmitt input from the disk drive is active low when the head is

positioned over the beginning of a track marked by an index hole.

This input pin is pulled up internally by an approximately 1K ohm

resistor. The resistor can be disabled by bit 4 of CR6

(FIPURDWN).
nTRAK0 78 IN

cs

Track 0. This schmitt input from the disk drive is active low when

the head is positioned over the outermost track. This input pin is

pulled up internally by an approximately 1K ohm resistor. The

resistor can be disabled by bit 4 of CR6 (FIPURDWN).
nWP 77 IN

cs

Write protected. This active low schmitt input from the disk drive

indicates that the diskette is write-protected. This input pin is pulled

up internally by an approximately 1K ohm resistor. The resistor can

be disabled by bit 4 of CR6 (FIPURDWN).
nRDATA 74 IN

cs

The read data input signal from the FDD. This input pin is pulled up

internally by an approximately 1K ohm resistor. The resistor can be

disabled by bit 4 of CR6 (FIPURDWN).
nDSKCHG 76 IN

cs

Diskette change. This signal is active low at power on and

whenever the diskette is removed. This input pin is pulled up

internally by an approximately 1K ohm resistor. The resistor can be

disabled by bit 4 of CR6 (FIPURDWN).
nMOA 79 OD

24

Motor A On. When set to 0, this pin enables disk drive 0. This is an

open drain output.
nMOB 80 OD

24

Motor B On. When set to 0, this pin enables disk drive 1. This is an

open drain output.
nDSA 83 OD

24

Drive Select A. When set to 0, this pin enables disk drive A. This is

an open drain output.
nDSB 84 OD

24

Drive Select B. When set to 0, this pin enables disk drive B. This is

an open drain output.
V

DD

15,

56

+5 Volt power supply for the digital circuitry
GND 25,

40,
65,

90

Ground

17

FDC FUNCTIONAL DESCRIPTION

FDC87W21 FDC

The floppy disk controller of the FDC87W21
integrates all of the logic required for floppy disk
control. The FDC implements a PC/AT or PS/2
solution. All programmable options default to
compatible values. The FIFO provides better
system performance in multi-master systems.
The digital data separator supports up to data
rate 1 Mbps. (2 Mbps for fast tape drive with 48
MHz crystal in.) The FDC includes the following
blocks: AT Interface, Precompensation, Data
Rate Selection, Digital Data Separator, FIFO,
and FDC Core.

AT Interface

The interface consists of the standard
asynchronous signals: nRD, nWR, A0-A3, IRQ,
DMA control, and a data bus. The address lines
select between the configuration registers, the
FIFO and control/status registers. This interface
can be switched between PC/AT, Model 30, or

PS/2 normal modes. The PS/2 register sets are
a superset of the registers found in a PC/AT.

FIFO (Data)

The FIFO is 16 bytes in size and has
programmable threshold values. All command
parameter information and disk data transfers
go through the FIFO. Data transfers are
governed by the RQM and DIO bits in the Main
Status Register. The FIFO defaults to disabled
mode after any form of reset. This maintains
PC/AT hardware compatibility. The default
values can be changed through the
CONFIGURE command. The advantage of the
FIFO is that it allows the system a larger DMA
latency without causing disk errors. The
following tables give several examples of the
delays with a FIFO. The data are based upon
the following formula:

THRESHOLD × (1/Data Rate) *8 - 1.5 µS =

DELAY

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 500 KBPS

Data Rate

1 Byte

1 × 16 µS - 1.5 µS = 14.5 µS

2 Byte

2 × 16 µS - 1.5 µS = 30.5 µS

8 Byte

8 × 16 µS - 1.5 µS = 6.5 µS

15 Byte

15 × 16 µS - 1.5 µS = 238.5 µS

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 1 MBPS

Data Rate

1 Byte

1 × 8 µS - 1.5 µS = 6.5 µS

2 Byte

2 × 8 µS - 1.5 µS = 14.5 µS

8 Byte

8 × 8 µS - 1.5 µS = 62.5 µS

15 Byte

15 × 8 µS - 1.5 µS = 118.5 µS

18

At the start of a command the FIFO is always
disabled and command parameters must be
sent based upon the RQM and DIO bit settings
in the main status register. When the FDC
enters the command execution phase, it clears
the FIFO of any data to ensure that invalid data
are not transferred.

An overrun and underrun will terminate the
current command and the data transfer. Disk
writes will complete the current sector by
generating a 00 pattern and valid CRC. Reads
require the host to remove the remaining data
so that the result phase may be entered.

DMA transfers are enabled with the SPECIFY
command and are initiated by the FDC by
activating the DRQ pin during a data transfer
command. The FIFO is enabled directly by
asserting nDACK and addresses need not be
valid.

Note that if the DMA controller is programmed
to function in verify mode a pseudo read is
performed by the FDC based only on nDACK.
This mode is only available when the FDC has
been configured into byte mode (FIFO disabled)
and is programmed to do a read. With the FIFO
enabled the above operation is performed by
using the new VERIFY command. No DMA
operation is needed.

Data Separator

The function of the data separator is to lock onto
the incoming serial read data. When a lock is
achieved the serial front end logic of the chip is
provided with a clock which is synchronized to
the read data. The synchronized clock, called
the Data Window, is used to internally sample
the serial data portion of the bit cell, and the
alternate state samples the clock portion. Serial
to parallel conversion logic separates the read
data into clock and data bytes.

The Digital Data Separator (DDS) has three
parts: control logic, error adjustment, and speed
tracking. The DDS circuit cycles once every 12

clock cycles ideally. Any data pulse input will be
synchronized and then adjusted by immediate
error adjustment. The control logic will generate
RDD and RWD for every pulse input. During any
cycle where no data pulse is present, the DDS
cycles are based on speed. A digital integrator is
used to keep track of the speed changes in the
input data stream.

Write Precompensation

The write precompensation logic is used to
minimize bit shifts in the RDDATA stream from
the disk drive. Shifting of bits is a known
phenomenon in magnetic media and is
dependent on the disk media and the floppy
drive.

The FDC monitors the bit stream that is being
sent to the drive. The data patterns that require
precompensation are well known. Depending
upon the pattern, the bit is shifted either early or
late relative to the surrounding bits.

Perpendicular Recording Mode

The FDC is also capable of interfacing directly
to perpendicular recording floppy drives.
Perpendicular recording differs from the
traditional longitudinal method in that the
magnetic bits are oriented vertically. This
scheme packs more data bits into the same
area.

FDCs with perpendicular recording drives can
read standard 3.5" floppy disks and can read
and write perpendicular media. Some
manufacturers offer drives that can read and
write standard and perpendicular media in a
perpendicular media drive.

A single command puts the FDC into
perpendicular mode. All other commands
operate as they normally do. The perpendicular
mode requires a 1 Mbps data rate for the FDC.
At this data rate the FIFO eases the host
interface bottleneck due to the speed of data
transfer to or from the disk.

19

Tape Drive

The FDC87W21 supports standard tape drives
(1 Mbps, 500 Kbps, 250 Kbps) and new fast
tape drive (2 Mbps). When working at 2 Mbps,
you need to change the crystal to 48 MHz.

FDC Core

The FDC87W21 FDC is capable of performing
twenty commands. Each command is initiated
by a multi-byte transfer from the
microprocessor. The result can also be a multi­byte transfer back to the microprocessor. Each

command consists of three phases: command,
execution, and result.

Command
The microprocessor issues all required
information to the controller to perform a
specific operation.

Execution
The controller performs the specified operation.

Result
After the operation is completed, status
information and other housekeeping information
is provided to the microprocessor.

20

FDC Commands

Command Symbol Descriptions:
C: Cylinder number 0 - 256

D: Data Pattern
DIR: Step Direction
DIR = 0, step out
DIR = 1, step in
DS0: Disk Drive Select 0
DS1: Disk Drive Select 1
DTL: Data Length
EC: Enable Count
EOT: End of Track
EFIFO: Enable FIFO
EIS: Enable Implied Seek
EOT: End of track
FIFOTHR: FIFO Threshold
GAP: Gap length selection
GPL: Gap Length
H: Head number
HDS: Head number select
HLT: Head Load Time
HUT: Head Unload Time
LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset
MFM: MFM or FM Mode
MT: Multitrack
N: The number of data bytes written in a sector
NCN: New Cylinder Number
ND: Non-DMA Mode
OW: Overwritten
PCN: Present Cylinder Number
POLL: Polling Disable
PRETRK: Precompensation Start Track Number
R: Record
RCN: Relative Cylinder Number
R/W: Read/Write
SC: Sector/per cylinder
SK: Skip deleted data address mark
SRT: Step Rate Time
ST0: Status Register 0
ST1: Status Register 1
ST2: Status Register 2
ST3: Status Register 3
WG: Write gate alters timing of WE

21

FDC Instruction Sets

(1) Read Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

MT MFM SK 0 0 1 1 0

Command codes

W

0 0 0 0 0 HDS DS1 DS0

W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID
information prior
to command

execution
W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD
and system

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command

execution

22

(2) Read Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

MT MFM SK 0 1 1 0 0

Command codes

W

0 0 0 0 0 HDS DS1 DS0

W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID
information prior to

command execution
W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD
and system

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command
execution

R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID
information after
command execution

23

(3) Read A Track

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 MFM 0 0 0 0 1 0

Command codes

W

0 0 0 0 0 HDS DS1 DS0

W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID information
prior to command

execution
W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD and
system; FDD reads
contents of all
cylinders from index
hole to EOT

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command
execution

R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information
after command
execution

24

(4) Read ID

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 MFM 0 0 1 0 1 0

Command codes

W

0 0 0 0 0 HDS DS1 DS0

Execution The first correct ID

information on the
cylinder is stored in
Data Register

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Disk status after the

command has been

completed

(5) Verify

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

MT MFM SK 1 0 1 1 0

Command codes

W

EC 0 0 0 0 HDS DS1 DS0

W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID information
prior to command

execution
W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL/SC -------------------

Execution No data transfer

takes place

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID information

after command

execution

25

(6) Version

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 0 0 1 0 0 0 0

Command codes

Result W

1 0 0 1 0 0 0 0

Enhanced controller

(7) Write Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

MT MFM 0 0 0 1 0 1

Command codes

W

0 0 0 0 0 HDS DS1 DS0

W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID
information prior to
Command

execution
W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD
and system

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after Command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

Command

execution

26

(8) Write Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

MT MFM 0 0 1 0 0 1

Command codes

W

0 0 0 0 0 HDS DS1 DS0

W
W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID
information prior to

command execution
W
W

---------------------- R ------------------------

---------------------- N -----------------------­W
W
W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

Execution Data transfer

between the FDD
and system

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information
after command

execution
R
R
R
R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command execution

27

(9) Format A Track

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 MFM 0 0 1 1 0 1

Command codes

W

0 0 0 0 0 HDS DS1 DS0

W
W

---------------------- N ------------------------

--------------------- SC -----------------------

Bytes/Sector

Sectors/Cylinder
W
W

--------------------- GPL ---------------------

---------------------- D ------------------------

Gap 3

Filler Byte

Execution for
Each Sector
Repeat:

W
W
W
W

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Input Sector

Parameters

Result R

R
R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information

after command

execution

R
R
R
R

---------------- Undefined -------------------

---------------- Undefined -------------------

---------------- Undefined -------------------

---------------- Undefined -------------------

28

(10) Recalibrate

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 0 0 0 0 1 1 1

Command codes

W

0 0 0 0 0 0 DS1 DS0

Execution Head retracted to

Track 0 Interrupt

(11) Sense Interrupt Status

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 0 0 0 1 0 0 0

Command codes

Result R

R

---------------- ST0 -------------------------

---------------- PCN -------------------------

Status information at
the end of each seek
operation

(12) Specify

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 0 0 0 0 0 1 1

Command codes
W
W

| ---------SRT ----------- | --------- HUT ---------- |

|------------ HLT -----------------------------------| ND

(13) Seek

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 0 0 0 1 1 1 1

Command codes
W

0 0 0 0 0 HDS DS1 DS0

W -------------------- NCN -----------------------

Execution R Head positioned over

proper cylinder on

diskette

(14) Configure

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 0 0 1 0 0 1 1

Configure

information
W

0 0 0 0 0 0 0 0

W
W

0 EIS EFIFO POLL | ------ FIFOTHR ----|

| --------------------PRETRK ---------------------- |

Execution Internal registers

written

29

(15) Relative Seek

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

1 DIR 0 0 1 1 1 1

Command codes
W

0 0 0 0 0 HDS DS1 DS0

W | -------------------- RCN ---------------------------- |

(16) Dumpreg

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 0 0 0 1 1 1 0

Registers placed in

FIFO

Result R

R
R
R
R
R
R
R
R
R

-------------------- PCN-Drive 0-----------------

-------------------- PCN-Drive 1 ----------------

-------------------- PCN-Drive 2-----------------

-------------------- PCN-Drive 3 ----------------

-------SRT ----------------- | --------- HUT --------

------------ HLT -------------------------------------| ND

-------------------- SC/EOT -------------------­LOCK 0 D3 D2 D1 D0 GAP WG

0 EIS EFIFO POLL | --- FIFOTHR ---- |

--------------------PRETRK ---------------------

(17) Perpendicular Mode

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 0 0 1 0 0 1 0

Command code

W

OW 0 D3 D2 D1 D0 GAP WG

(18) Lock

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

LOCK 0 0 1 0 1 0 0

Command code

Result R

0 0 0 LOCK 0 0 0 0

30

(19) Sense Drive Status

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W

0 0 0 0 0 1 0 0

Command code

W

0 0 0 0 0 HDS DS1 DS0

Result R ---------------- ST3 ------------------------- Status information

about disk drive

(20) Invalid

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W ------------- Invalid Codes ----------------- Invalid codes (no

operation - FDC
goes into standby
state)

Result R -------------------- ST0 ---------------------- ST0 = 80H