!" 3.3V Operation With 5V Tolerant Buffers
!" ACPI 1.0 and PC99 Compliant
!" Three Power Planes
!" ACPI Embedded Controller Interface
!" Low Standby Current in Sleep Mode
!" Configuration Register Set Compatible With
ISA Plug-and-Play Standard (Version 1.0a)
!" Serial IRQ Interface Compatible With
Serialized IRQ Support for PCI Systems
!" Floppy Disk Interface on Parallel Port
!" 8051 Controller uses Parallel Port to
Reprogram the Flash ROM
!" Advanced Infrared Communications
Controller (IrCC 2.0)
- IrDA V1.1 (4Mbps), HPSIR, ASKIR,
Consumer IR Support
- Two IR Ports
- Relocatable Base I/O Address
!" 512k Byte Flash ROM Interface
- 8051/Host CPU Multiplexed Interface
- Sixteen 32K Pages - 8051 Keyboard
BIOS
- Eight 64K Pages - Host System BIOS
- Embedded Controller uses Parallel Port
to Reprogram Flash ROM
!" ISA Host Interface With Clock Run Support
and ACPI SCI Interface
- 16 Bit Address Qualification
- 8 Bit Data Bus
- Zero Wait-State I/O Register Access
- Shadowed Write Only registers
- IOCHRDY for ECP, IRCC 2.0 and Flash
Cycles
- 15 Direct IRQs Including nSMI
- Four 8 Bit DMA Channels
- XNOR Test Chain
!"High-Performance Embedded 8051
Keyboard and System Controller
- Provides System Power Management
- System Watch Dog Timer (WDT)
- 8042 Style Host Interface
- Asynchronous Access to Two Data
Registers and One Status Register
- Supports Interrupt and Polling Access
- 2K Internal ROM, nEA Pin Select
- 32K Bank Switchable External Flash
ROM Interface
- 256 Bytes Data RAM
- On-Chip Control Registers Available via
MOVX External Data Access Commands
- ChiProtect Circuitry to Prevent Printer
Power-On Damage
- Relocatable to 480 Different Base I/O
Addresses
- 15 IRQ Options
- 4 DMA Options
- Microsoft and HP compatible High Speed
Mode
- 12 mA Output Drivers
!"
Serial Port
- High-Speed NS16550A-Compatible
UART with 16-Byte Send/Receive FIFOs
- Programmable Baud Rate Generator
Modem Control Circuitry Including 230k
and 460k Baud
- Relocatable to 480 Different Base I/O
Addresses
- 15 IRQ Options
!"
208 Pin TQFP Package Options
!"
208 Pin FBGA Package Options
2
GENERAL DESCRIPTION
The FDC37N972 is a 208-pin 3.3V ISA Host
ACPI 1.0 and PC98 (/PC99)-compliant Ultra I/O
Controller with Fast Infrared for mobile
applications.
The FDC37N972 incorporates a highperformance 8051-based keyboard controller; a
512k byte Flash ROM interface; four PS/2 ports;
a real-time clock; SMSC's true CMOS 765B
floppy disk controller with advanced digital data
separator and 16-byte data FIFO; an
NS16C550A-compatible UART, SMSC’s
advanced Infrared Communications Controller
(IrCC 2.0) with a UART and a Synchronous
Communications Engine to provide IrDA v1.1
(Fast IR) capabilities; one Multi-Mode parallel
port with ChiProtect circuitry plus EPP and ECP
support; two 8584-style Access Bus controllers;
a Serial IRQ peripheral agent interface; an ACPI
Embedded Controller Interface; General
Purpose I/O pins; two independently
programmable pulse width modulators; twofloppy direct drive support; and maskable
hardware wake-up events.
The true CMOS 765B core provides 100%
compatibility with IBM PC/XT and PC/AT
architectures in addition to providing data
overflow and underflow protection. The SMSC
advanced digital data separator incorporates
SMSC's patented data separator technology,
allowing for ease of testing and use.
The parallel port is compatible with IBM PC/AT
architecture, as well as EPP and ECP. The
8051 controller can also take control of the
parallel port interface to provide remote
diagnostics or “Flashing” of the Flash memory.
The FDC37N972 has three separate power
planes to provide “instant on” and system power
management functions. Additionally, the
FDC37N972 incorporates sophisticated power
control circuitry (PCC). The PCC supports
multiple low power down modes. Wake-up
events and ACPI-related functions are supported
through the SCI Interface.
The FDC37N972’s configuration register set is
compatible with the ISA Plug-and-Play Standard
(Version 1.0a) and provides the functionality to
support Windows '95. Through internal
configuration registers, each of the
FDC37N972's logical device's I/O address, DMA
channel and IRQ channel may be programmed.
There are 480 I/O address location options, 15
IRQ options, and four DMA channel options for
each logical device.
The FDC37N972 does not require any external
filter components and is, therefore, easy to use
and offers lower system cost and reduced board
area. The FDC37N972 is software and register
compatible with SMSC's proprietary 82077AA
core.
Device functions per pin are shown in TABLE 2.
Buffer Modes symbols in TABLE 2 are described
in Table 3. Multifunction pins are summarized
in Table 4, including a multiplex controls
reference.
The pins and descriptions in Table 2 are
organized by primary pin function. For example,
the PS2 Serial Clock and PS2 Serial Data pins
are technically part of the KEYBOARD AND
MOUSE INTERFACE but are listed in the
GENERAL PURPOSE I/O INTERFACE because
the GPIO function of these pins is the default.
TABLE 2 - PIN FUNCTION DESCRIPTION
TQFP
PIN#NOTESNAMEDESCRIPTION
POWER
PLANE
BUFFER
MODES
FDD INTERFACE (15)
The following FDC output pins can be configured as either Open Drain outputs capable of sinking 12mA
(OD12) or as push-pull outputs capable of driving 6mA and sinking 12mA (O12). The FDC output pins
must tristate when the FDC is in powerdown mode (The board designer must provide external pull-up
resistors on these output pins).
4DRVDEN0Drive Density Select 0VCC2(O12/OD12)
5DRVDEN1Drive Density Select 1VCC2(O12/OD12)
6nMTR0Motor On 0VCC2(O12/OD12)
8nDS0Drive Select 0VCC2(O12/OD12)
9nDIRStep DirectionVCC2(O12/OD12)
10nSTEPStep PulseVCC2(O12/OD12)
11nWDATAWrite Disk DataVCC2(O12/OD12)
12nWGATEWrite GateVCC2(O12/OD12)
13nHDSELHead SelectVCC2(O12/OD12)
14nINDEXIndex Pulse InputVCC2IS
15nTRK0Track 0VCC2IS
16nWRTPRTWrite ProtectedVCC2IS
17nRDATARead Disk DataVCC2IS
18nDSKCHGDisk ChangeVCC2IS
19FPDFloppy Power Down Output ControlVCC2O8
Keyboard Scan Outputs (14 × 8).
NOTE: GPIO4 and GPIO5 can be
configured as KSO14 and KSO15
VCC1OD4
(16 × 8).
233KSO12/
OUT8/
KBRST
2211KSO13/
GPIO18
Keyboard Scan Output
General Purpose Output
CPU_RESET
Keyboard Scan Output
General Purpose I/O
VCC1OD4/OD4/
VCC1OD4/IOD4
37:44KSI[0:7]Keyboard Scan InputsVCC1ISP
193nEAExternal Access for 2k ROMVCC1I
52EMCLKEM Serial ClockVCC2IOD16
53EMDATEM Serial DataVCC2IOD16
47IMCLKIM Serial ClockVCC2IOD16
48IMDATIM Serial DataVCC2IOD16
51KDATKeyboard DataVCC2IOD16
Initiate Output
FDC Direction Control
Printer Select Input
FDC Step Pulse
Port Data 0
FDC Index
Port Data 1
FDC Track 0
Port Data 2
FDC Write Protected
Port Data 3
FDC Read Disk Data
Port Data 4
FDC Disk Change
VCC2(OD14/
OP14)/OD14
VCC2(OD14/
OP14)/OD14
VCC2IOP14/I
VCC2IOP14/I
VCC2IOP14/I
VCC2IOP14/I
VCC2IOP14/I
118PD5Port Data 5VCC2IOP14
117PD6/
nMTR0
Port Data 6
FDC Motor On 0
VCC2IOP14/OD14
116PD7Port Data 7VCC2IOP14
112SLCT/
nWGATE
113PE/
nWDATA
114BUSY/
nMTR1
Printer Selected Status
FDC Write Gate
Paper End
FDC Write Data
Busy
FDC Motor On 1
130RXDReceive DataVCC2I
131TXDTransmit DataVCC2O12
133nDSRData Set ReadyVCC2I
134nRTSRequest to SendVCC2O8
135nCTSClear to SendVCC2I
136nDTRData Terminal ReadyVCC2O8
138nRIRing IndicatorVCC1I
137nDCDData Carrier DetectVCC2I
MISCELLANEOUS (11)
10832kHz_OUT32.768kHz Output Clock --The 32
VCC1O8
KHz output is enabled / disabled by
setting / clearing bit-0 of the Output
Enable 8051 memory mapped
register. When disabled the 32
KHz_OUT pin is driven low. The 32
KHz_OUT pin defaults to the
disabled state on VCC1 POR.
10524MHz_OUT24MHz Clock Output
VCC2O24
Programmable Clock Output.
1.8432 MHz (default = 24 MHz/13)
14.318 MHz
16 MHz
24 MHz
48 MHz
103CLOCKI14.318MHz Clock InputVCC2ICLK
194MODEConfiguration Ports Base Address
VCC1I
Select
15710XOSELExternal 32kHz Clock Enable InputVCC0I
BUFFER
MODES
(OD14/OP14)/
OD14
(OD14/OP14)/
OD14
2
18
TQFP
PIN#NOTESNAMEDESCRIPTION
1099VCC1_PWRGDVCC1 Power Good Input. The
POWER
PLANE
VCC1IP
BUFFER
MODES
trailing edge of VCC1 POR is
released 20ms from the assertion of
this pin. If this pin is pulled low
while VCC1 is valid, then VCC1
POR will be asserted and held until
20ms from re-assertion of this pin.
This pin has an internal weak
(90µA) pull-up to VCC1.
102
nRESET_OUT
System ResetVCC2O8
197nBAT_LEDBattery LED (0 = ON)VCC1OD12
110nPWR_LEDPower LED (0 = ON)VCC1OD12
198nFDD_LEDFloppy LED (0 = ON). This pin is
VCC1OD12
asserted whenever either DRVSEL1
or DRVSEL0 is asserted or
controlled by the 8051.
1119PWRGDVCC2 Power Good InputVCC1I
ACCESS BUS INTERFACE (2)
195AB1_DATAACCESS.bus 1 Serial DataVCC1IOD12
196AB1_CLKACCESS.bus 1 ClockVCC1IOD12
NOTE 1:These pins default to “output”, “low” to prevent infrared transceiver damage (see
Section IRTX Output Pins DEFAULT).
NOTE 2:Buffer Modes per function on multiplexed pins are separated by a slash “/”; e.g., a
pin with two multiplexed functions where the primary function is an input and the
secondary function is an 8mA bidirectional driver is represented as “I/IO8”. Buffer
Modes in parenthesis represent multiple buffer modes for a single pin function.
NOTE 3:This pin is tristated when PWRGD is inactive and the pin is configured as a VCC2-
powered alternate function.
NOTE 4:These devices can generate wake-up events on either edge of the signal that is
applied when the pin is configured as an input. The interrupts are masked by the
Wake-up Mask Register bits.
NOTE 5:These devices can generate wake-up events on selectable edges of the signal that is
applied when the pin is configured as an input. The interrupts are masked by the
Wake-up Mask Registers and selected edges are programmed via the Edge Select
registers (see section 8051 Internal PARALLEL on page 170).
NOTE 6:This interrupt is masked by INT1 Mask Register bit 3. GPIO3 is the only GPIO pin
which does not generate a wakeup event.
NOTE 7:The nEC_SCI pin can be controlled by hardware and 8051 software. The nEC_SCI
pin can drive either the ACPI Run-time GPE Chipset input or the Wake GPE Chipset
input (FIGURE 7). Depending how the nEC_SCI pin is used, other ACPI-related SCI
functions may be best supplied by FDC37N972 general purpose output OUT0.
NOTE 8:OUT0 and GPIO7 are suitable as an SCI output pin because the buffer type can be
configured as a push-pull or open-drain output (see a description of the MISC21 and
MISC23 bits in Multiplexing_3 Register on page 278).
NOTE 9:Input levels for the PWRGD and VCC1_PWRGD pins are rail-to-rail ±400mV; e.g.,
PWRGD VIL = .4V max, PWRGD VIH = 2.7V min. @ VCC1 min.
NOTE 10:The function of these pins are described in Section 32kHz Clock Input
The FDC37N972 uses the XOSEL pin to select either a 32.768kHz input clock or a
32.768kHz crystal to drive the Real Time Clock Interface (Table 2 - PIN FUNCTION
DESCRIPTION).
When XOSEL = ‘0’, the RTC uses a 32.768kHz crystal connected between the
XTAL1 and XTAL2 pins. When XOSEL = ‘1’, the RTC is driven by a 32.768kHz
single-ended clock source connected to THE XTAL2 PIN.
NOTE: ICC0 ≥≥ 10µA for time-keeping operations under VCC0 using a single-ended
clock source. ICC1 = 30µA under VCC1 using a single-ended clock source.
NOTE 11:The GPIO18 alternate function of the KS013 pin has no wake-up capability (see note
NOTE 1:See a description in Section MULTIFUNCTION PIN on page 271.
NOTE 2:The FDC37N972 pins are identified by primary pin function (see
DESCRIPTION OF PIN FUNCTIONS on page 11). Note that some functions are
available on more than one pin; e.g., OUT8, GPIO18 and KBRST.
NOTE 3:When this pin is configured as an alternate function output and PWRGD is inactive,
i.e. VCC2 is 0v, the pin will tri-state to prevent back-biasing of external circuitry (see
Section General Purpose I/O (GPIO) on page 265).
NOTE 4:This pin defaults to “output”, “low” for both the default (GPIO) function and the
alternate (IRTX) function, regardless of the state of PWRGD (see Section General
Purpose I/O (GPIO) on page 265).
NOTE 5:MISC5 must be inactive for MISC22 to enable KBRST.
NOTE 6:The ALT WRITE SELECT bit is in the Flash Configuration Register (see Section
ALT WRITE SELECT Bit, D3 on page 197).
23
There are three power planes in the FDC37N972
V
CC0, VCC1,
and V
with the following power
CC2
sequencing requirement:
1. V
simultaneously with or after V
2. V
simultaneously with or after V
All internal components which utilize V
shall have power applied
CC2
shall have power applied
CC1
CC1
CC0
.
.
CC0
power
plane are switched internally between the VCC1
and VCC0 pins according to VCC1_PWRGD
See Table 5 for power consumption in various
states.
Two FDC37N972 power supply configurations
can be utilized. These power supply
configuration types fundamentally differ upon
the need for a backup battery (V
to V
.
CC0
) connection
BAT
TYPE 1 devices do not require a V
CC0
battery
connection. Power supply requirements for
TYPE 1 devices are as follows: V
VSS, V
supply, and V
is connected to the main battery
CC1
is switched from either the
CC2
is tied to
CC0
main battery or AC power if available. In this
configuration all internal components which
utilize V
power plane are switched internally
CC0
to the VCC1 upon POR according to
VCC1_PWRGD.
TYPE 2 devices require a V
CC0
battery
connection. Power supply requirements for
TYPE 2 devices are as follows: V
connected to a backup battery (V
BAT
connected to the main battery supply, and V
), V
CC0
CC1
is
is
CC2
is switched from either the main battery or AC
power if available. In this configuration all
internal components which utilize V
plane only when V
is absent. Normally (when
CC1
CC0
power
VCC1_PWRGD is asserted) they are switched
internally to the VCC1 power plane.
FLOPPY @ 1 Meg Data Rate
I2C @ 24 MHz
Floppy @ 500K Data Rate
I2C @ 12 MHz
PLL On
I2C Off
PLL Off
7 ma
PLL Off
I2C Off
PLL Off
I2C Off
160 µaXOSEL=1
cc0
< 4 VDC,
XOSEL=1,
00I
CC0
0.4 µa1.5 µa2.4 < V
< 4 VDC,
cc0
XOSEL = 0
Note:When a single-ended 32.768kHz clock source is selected (see Section 32kHz Clock Input).
The FDC37N972 uses the XOSEL pin to select either a 32.768kHz input clock or a
32.768kHz crystal to drive the Real Time Clock Interface (Table 2 - PIN FUNCTION
DESCRIPTION). When XOSEL = ‘0’, The RTC uses a 32.768kHz crystal connected between
the XTAL1 and XTAL2 pins. When XOSEL = ‘1’, the RTC is driven by a 32.768kHz singleended clock source connected to the XTAL2 pin.
25
TABLE 7 - POWER PIN LIST
BIAS PINS
156VCC0RTC (V
)Supply Voltage 2.7-3.3V ibat<2ma
BAT
29, 143, 176VCC18051 + AB + CI + RTC+ ACPI + PM1 + WDT + MR + CR
+ PM + AB2 + FI + PWM + KI + GPIO + LED + IR + 3.3V
+/-5% Supply Voltage (Note)
+3.3V +/-5%Supply Voltage
160AGNDAnalog Ground for VCC0.
1, 7, 49, 73, 89,
VSSDigital Ground
107, 132, 167, 192
Note:
AB= ACCESS.bus
CI = Control Inputs
WDT = Watch Dog Timer
MR = Mailbox Registers
CR = Control Registers
PM = Power Management
AB2 = ACCESS.BUS2
FI = Flash Interface
KI= Keyboard Interface
GPIO= General Purpose I/O Interface
IR= Infrared
SR= System Reset
PCG= PLL Clock Generator
FDC= Floppy Disk Controller
DDS= Digital Data Seperator
PP= Multi-Mode Parallel Port
PWRGD and VCC1_PWRGD timing is illustrated in FIGURE 3 through FIGURE 5.
26
10µs
PWRGD
VCC2
CLOCKI
min.
3V
FIGURE 3 – POWER-FAIL EVENT
PWRGD
10µs
min.
VCC2
CLOCKI
3V
FIGURE 4 - VCC2 POWER-UP TIMING
1µs
min.
VCC1_PWRGD
VCC1
3V3V
FIGURE 5 - VCC1_PWRGD TIMING
These figures also appear in the “Timing Diagrams” section of this spec.
1µs
min.
27
FUNCTIONAL DESCRIPTION
FDC37N972 OPERATING REGISTERS
The address map, shown below in TABLE 8,
shows the set of operating registers and
addresses for each of the logical blocks of the
FDC37N972 Ultra I/O controller. The base
addresses of the FDC, Parallel, Serial 1 and
Infrared ports can be moved via the
configuration registers.
TABLE 8 - FDC37N972 OPERATING REGISTER ADDRESSES
LOGICAL
DEVICE
NUMBER
0x00FDC[0x100:0x0FF8]
0x03Parallel
LOGICAL
DEVICE
Port
BASE I/O
RANGE
(NOTE3)
ON 8 BYTE
BOUNDARIES
[0x100:0x0FFC]
ON 4 BYTE
BOUNDARIES
(EPP Not supported)
or
[0x100:0x0FF8]
ON 8 BYTE
BOUNDARIES
(all modes
supported,
EPP is only available
when the base
address is on an 8byte boundary)
HOST PROCESSOR INTERFACE
The host processor communicates with the
FDC37N972 through a series of read/write
registers. The range of base I/O port addresses
for these registers is shown in TABLE 8.
Register access is accomplished through
programmed I/O or DMA transfers. All registers
are 8 bits. Most of the registers support zero
wait-state access (NOWS). All host interface
output buffers are capable of sinking a minimum
of 6 mA.
ISA
FIXED
BASE OFFSETS
+0 : SRA
+1 : SRB
+2 : DOR
+3 : TSR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
+0 : Data / ecpAfifo
+1 : Status
+2 : Control
+400h : cfifo / ecpDfifo
tfifo / cnfgA
+401h : cnfgB
+402h : ecr
+0 : Register Block N,
address 0
+1 : Register Block N,
address 1
+2 : Register Block N,
address 2
+3 : Register Block N,
address 3
+4 : Register Block N,
address 4
+5 : Register Block N,
address 5
+6 : Register Block N,
address 6
+7 : SCE Master Control
Reg.
0x70, 0x74 : Address
Register
0x71, 0x76 : Data Register
0x60 : Data Register
0x64 : Command/Status
Reg.
ISA
CYCLE
TYPE
NOWS
NOWS
NOWS
Std. ISA I/O
NOWS
Note 1: Refer to the configuration register descriptions for setting the base address
Note 2: This chip uses all ISA address bits to decode the base address of each of its logical devices.
29
FLOPPY DISK CONTROLLER
The Floppy Disk Controller (FDC) provides the
interface between a host microprocessor and
the Floppy Disk Drives (FDD). The FDC
integrates the functions of the
formatter/controller, Digital Data Separator,
Write Precompensation and data rate Selection
logic for an IBM XT/AT compatible FDC. The
true CMOS 765B core guarantees 100% IBM
PC XT/AT compatibility in addition to providing
data overflow and underflow protection.
TABLE 9 - STATUS, DATA AND CONTROL REGISTERS
FDC PRIMARY BASE I/O
ADDRESS OFFSETR/WREGISTER
0RStatus Register A (SRA)
1RStatus Register B (SRB)
2R/WDigital Output Register (DOR)
3R/WTape Drive Register (TDR)
4RMain Status Register (MSR)
4WData Rate Select Register (DSR)
5R/WData (FIFO)
6Reserved
7RDigital Input Register (DIR)
7WConfiguration Control Register (CCR)
The FDC is compatible to the 82077AA using
SMSC's proprietary FDC core.
FDC INTERNAL REGISTERS
The FDC contains eight internal registers, which
facilitate the interfacing between the host
microprocessor and the disk drive TABLE 9
shows the addresses required toaccess these
registers. Registers other than the ones shown
are not supported.
STATUS REGISTER A (SRA)
FDC I/O BASE ADDRESS + 0x00
(READ ONLY)
This register is read-only and monitors the state of the FDC Interrupt pin and several disk
interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2
mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of
SRA.
30
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