Standard Microsystems Corporation FDC37C935FR, FDC37C932FR Datasheet

FDC37C93xFR

ADVANCE INFORMATION

Plug and Play Compatible Ultra I/O Controller

with Fast IR

FEATURES

• 5 Volt Operation

• ISA Plug-and-Play Standard (Version 1.0a)

Compatible Register Set

• Soft Power Management, SMI Support

• ACCESS.bus Support

• 8042 Keyboard Controller

- 2K Program ROM

- 256 Bytes Data RAM

- Asynchronous Access to Two Data

Registers and One Status Register

- Supports Interrupt and Polling Access

- 8 Bit Timer/Counter

- Port 92 Support

- Fast Gate A20 and Hardware Keyboard

Reset

• Real Time Clock

- MC146818 and DS1287 Compatible

- 256 Bytes of Battery Backed CMOS in

Two Banks of 128 Bytes

- 128 Bytes of CMOS RAM Lockable in

4x32 Byte Blocks

- 12 and 24 Hour Time Format

- Binary and BCD Format

- 1µA Standby Current (typ)

• Intelligent Auto Power Management

• 2.88MB Super I/O Floppy Disk Controller

- Relocatable to 480 Different Addresses

- 13 IRQ Options

- Four DMA Options

- Licensed CMOS 765B Floppy Disk

Controller

- Advanced Digital Data Separator

- Software and Register Compatible with

SMSC's Proprietary 82077AA Compatible Core

- Sophisticated Power Control Circuitry

(PCC) Including Multiple Powerdown Modes for Reduced Power Consumption

- Game Port Select Logic

- Supports Two Floppy Drives Directly

- 24mA AT Bus Drivers

- Low Power CMOS Design

• Licensed CMOS 765B Floppy Disk Controller Core

- Supports Vertical Recording Format

- 16 Byte Data FIFO

- 100% IBM® Compatibility

- Detects All Overrun and Underrun

Conditions

- 48mA Drivers and Schmitt Trigger Inputs

- DMA Enable Logic

- Data Rate and Drive Control Registers

• Enhanced Digital Data Separator

- Low Cost Implementation

- No Filter Components Required

- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,

250 Kbps Data Rates

- Programmable Precompensation Modes

• Serial Ports

- Relocatable to 480 Different Addresses

- 13 IRQ Options

- Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs

TABLE OF CONTENTS

FEATURES...................................................................................................................................... 1

GENERAL DESCRIPTION................................................................................................................ 3

PIN CONFIGURATION ...................................................................................................................... 4

DESCRIPTION OF PIN FUNCTIONS ................................................................................................ 5

FUNCTIONAL DESCRIPTION........................................................................................................ 14

SUPER I/O REGISTERS............................................................................................................. 14

HOST PROCESSOR INTERFACE .............................................................................................14

FLOPPY DISK CONTROLLER................................................................................................... 15

FLOPPY DISK CONTROLLER INTERNAL REGISTERS.............................................................15

COMMAND SET/DESCRIPTIONS.................................................................................................. 39

INSTRUCTION SET ........................................................................................................................ 43

SERIAL PORT (UART).................................................................................................................... 69

INFRARED INTERFACE...................................................................................................................84

FAST IR.......................................................................................................................................... 85

PARALLEL PORT........................................................................................................................... 87

IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES................................................89

EXTENDED CAPABILITIES PARALLEL PORT............................................................................95

AUTO POWER MANAGEMENT.....................................................................................................111

INTEGRATED DRIVE ELECTRONICS INTERFACE..................................................................... 116

HOST FILE REGISTERS .......................................................................................................... 116

TASK FILE REGISTERS...........................................................................................................116

IDE OUTPUT ENABLES ...........................................................................................................117

BIOS BUFFER.......................................................................................................................... 117

GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION...............................................................120

8042 KEYBOARD CONTROLLER AND REAL TIME CLOCK FUNCTIONAL DESCRIPTION...........134

SOFT POWER MANAGEMENT..................................................................................................... 159

SYSTEM MANAGEMENT INTERRUPT (SMI)................................................................................ 162

ACCESS.BUS ............................................................................................................................... 163

CONFIGURATION......................................................................................................................... 169

OPERATIONAL DESCRIPTION..................................................................................................... 216

MAXIMUM GUARANTEED RATINGS....................................................................................... 216

DC ELECTRICAL CHARACTERISTICS.................................................................................... 216

TIMING DIAGRAMS...................................................................................................................... 221

ECP PARALLEL PORT TIMING..................................................................................................... 247

80 Arkay Drive Hauppauge, NY. 11788 (516) 435-6000 FAX (516) 273-3123

- Programmable Baud Rate Generator

- Modem Control Circuitry Including 230K

and 460K Baud

- IrDA, HP-SIR, ASK-IR Support, Fast IR

(4Mbps IrDA), Consumer IR

• IDE Interface

- Relocatable to 480 Different Addresses

- 13 IRQ Options (IRQ Steering through

Chip)

- Two Channel/Four Drive Support

- On-Chip Decode and Select Logic

Compatible with IBM PC/XT® and PC/AT® Embedded Hard Disk Drives

• Serial EEPROM Interface

• Multi-Mode Parallel Port with ChiProtect

- Relocatable to 480 Different Addresses

- 13 IRQ Options

- Four DMA Options

- Enhanced Mode

- Standard Mode:

- IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port

- Enhanced Parallel Port

- (EPP) Compatible - EPP 1.7 and EPP

1.9 (IEEE 1284 Compliant)

- High Speed Mode

- Microsoft and Hewlett Packard Extended Capabilities Port (ECP) Compatible (IEEE 1284 Compliant)

- Incorporates ChiProtect Circuitry for

Protection Against Damage Due to Printer Power-On

- 12 mA Output Drivers

• ISA Host Interface

• 16 Bit Address Qualification

• 160 Pin QFP Package

GENERAL DESCRIPTION

The FDC37C93xFR with Fast IR support incorporates a keyboard interface, real-time clock, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP support, IDE interface, on-chip 24 mA AT bus drivers, game port chip select and two floppy direct drive support, as well as ACCESS.bus, soft power management and SMI support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550. The parallel port, the IDE interface, and the game port select logic are compatible with IBM PC/AT architecture, as well as EPP and ECP. The FDC37C93xFR incorporates sophisticated

power control circuitry (PCC). The PCC supports multiple low power down modes. The FDC37C93xFR provides support for the ISA Plug-and-Play Standard (Version 1.0a) and provides for the recommended functionality to support Windows '95. Through internal configuration registers, each of the FDC37C93xFR's logical device's I/O address, DMA channel and IRQ channel may be programmed. There are 480 I/O address location options, 13 IRQ options, and three DMA channel options for each logical device. The FDC37C93xFR does not require any external filter components and is, therefore, easy to use and offers lower system cost and reduced board area. The FDC37C93xFR is software and register compatible with SMSC's proprietary 82077AA core.

IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business Machines Corporation SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems Corporation

PIN CONFIGURATION

120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

GND DRVDEN0 DRVDEN1

nMTR0

nDS1 nDS0

nMTR1

GND

nDIR

nSTEP

nWDATA

nWGATE

nHDSEL

nINDEX

nTRK0

nWRTPRT

nRDATA

nDSKCHG

MEDIA_ID1 mEDIA_ID0

VCC

CLOCKI

nIDE1_OE

nHDCS0 nHDCS1

IDE1_IRQ nHDCS2/SA13 nHDCS3/SA14

IDE2_IRQ/SA15

nIOROP

nIOWOP

VTR

nPOWER ON

BUTTON_IN

HCLK 16CLK CLK01 CLK02 CLK03

GND

nROMDIR nROMCS RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 GP25 GP24 GP23 GP22 GP21 GP20 GP17 GP16 GP15 VCC GP14 GP13 GP12 GP11 GP10 GND MCLK MDAT KCLK KDAT IOCHRDY TC DRQ3 nDACK3 DRQ2 nDACK2 DRQ1 nDACK1 DRQ0

nDACK0

nDTR2

nCTS2

nRTS2

nDSR2

TXD2

RXD2

nDCD2

nRI2

nDCD1

nRI1

nDTR1

nCTS1

nRTS1

nDSR1

TXD1

RXD1

nSTB

nALF

nERROR

nINIT

nSLCTIN

VCC

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

GND

nACK

BUSYPESLCT

VCC

XTAL2

GND

XTAL1

VBAT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

424344454647484950515253545556575859606162636465666768697071727374757677787980

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

FDC37C93xFR

160 Pin QFP

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

nCS/SA12

IRQ15

IRQ14

IRQ12

IRQ11

IRQ10

IRQ9

VCC

IRQ8/nIRQ8

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ1

nIOR

nIOW

AEN

GND

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

RESET_DRV

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL BUFFER TYPE

PROCESSOR/HOST INTERFACE

72:79 System Data Bus SD[0:7] I/O24 41:52 System Address Bus SA[0:11] I

53 Chip Select/SA12 (Active Low)(Note 1, 4) nCS I 70 Address Enable (DMA master has bus control) AEN I 90 I/O Channel Ready IOCHRDY OD24 80 Reset Drive RESET_DRV IS

67:61,

59:54

Interrupt Requests [1,3:12,14,15] (Polarity control for IRQ8)

IRQ[1,3:12, 14,15]

024/OD24

(Note 0)

82,84,

86,88

DMA Requests DRQ[0:3] O24

81,83,

85,87

DMA Acknowledge nDACK[0:3] I

89 Terminal Count TC I 68 I/O Read nIOR I 69 I/O Write nIOW I 35 High Speed Clock Out 24/48 MHz HCLK O20 36 16 MHz Out 16CLK O8SR 22 14.318 MHz Clock Input CLOCKI ICLK 37 14.318 MHz Clock Output 1 CLKO1 O16SR 38 14.318 MHz Clock Output 2 CLKO2 O8SR 39 14.318 MHz Clock Output 3 CLKO3 O8SR

POWER PINS

21, 60,

101, 125,

139

+5V Supply Voltage VCC

32 Trickle Voltage Input VTR

1, 8, 40,

71, 95,

123, 130

Ground GND

FDD INTERFACE

17 Read Disk Data nRDATA IS 12 Write Gate nWGATE OD48

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL BUFFER TYPE

11 Write Disk Data nWDATA OD48 13 Head Select (1 = side 0) nHDSEL OD48

9 Step Direction (1 = out) nDIR OD48 10 Step Pulse nSTEP OD48 18 Disk Change nDSKCHG IS

5,6 Drive Select Lines nDS[1:0] OD48 7,4 Motor On Lines nMTR[1:0] OD48

16 Write Protected nWPROT IS 15 Track 0 nTR0 IS 14 Index Pulse Input nINDEX IS

3,2 Drive Density Select [1:0] DRVDEN [1:0] OD48

19,20

Media ID inputs. In floppy enhanced mode 2 these inputs are the media ID [1:0] inputs. (Note 4)

MID[1:0] IS

SERIAL PORT 1 INTERFACE

145 Receive Serial Data 1 RXD1 I 146 Transmit Serial Data 1 TXD1 O4 148 Request to Send 1 nRTS1 O4 149 Clear to Send 1 nCTS1 I 150 Data Terminal Ready 1 nDTR1 O4 147 Data Set Ready 1 nDSR1 I 152 Data Carrier Detect 1 nDCD1 I 151 Ring Indicator 1 nRI1 I

SERIAL PORT 2 INTERFACE

155 Receive Serial Data 2 (Note 4) RXD2 I 156 Transmit Serial Data 2 (Note 4) TXD2 O4 158 Request to Send 2 (Note 4) nRTS2 O4 159 Clear to Send 2 (Note 4) nCTS2 I 160 Data Terminal Ready 2 (Note 4) nDTR2 O4 157 Data Set Ready 2 (Note 4) nDSR2 I 154 Data Carrier Detect 2 (Note 4) nDCD2 I 153 Ring Indicator 2 (Note 4) nRI2 I

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL BUFFER TYPE

IDE1 INTERFACE

23 IDE1 Enable (Note 4) nIDE1_OE O4 24 IDE1 Chip Select 0 (Note 4) nHDCS0 O24 25 IDE1 Chip Select 1 (Note 4) nHDCS1 O24 30 IOR Output (Note 4) nIOROP O24 31 IOW Output (Note 4) nIOWOP O24 26 IDE1 Interrupt Request (Note 4) IDE1_IRQ I

IDE2 INTERFACE

27 IDE2 Chip Select 2/SA13 (Note 3, 4) nHDCS2 I/O24 28 IDE2 Chip Select 3/SA14 (Note 3, 4) nHDCS3 I/O24 29 IDE2 Interrupt Request/SA15 (Note 4) IDE2_IRQ I

PARALLEL PORT INTERFACE

138:131 Parallel Port Data Bus PD[0:7] I/O24

140 Printer Select nSLCTIN OD24/O24 141 Initiate Output nINIT OD24/O24 143 Auto Line Feed nALF OD24/O24 144 Strobe Signal nSTB OD24/O24 128 Busy Signal BUSY I 129 Acknowledge Handshake nACK I 127 Paper End PE I 126 Printer Selected SLCT I 142 Error at Printer nERROR I

REAL-TIME CLOCK

122 32 kHz Crystal Input XTAL1 ICLK2 124 32 kHz Crystal Output XTAL2 OCLK2 121 Battery Voltage Vbat

KEYBOARD/MOUSE

91 Keyboard Data KDAT I/OD16P 92 Keyboard Clock KCLK I/OD16P 93 Mouse Data MDAT I/OD16P 94 Mouse Clock MCLK I/OD16P

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL BUFFER TYPE

SOFT POWER MANAGEMENT INTERFACE

33 Power On (Note 4) nPowerOn I/O24 34 Button Input (Note 4) Button_In I/O24

GENERAL PURPOSE I/O

96 GP I/O; IRQ in (Note 4) GP10 I/O4 97 GP I/O; IRQ in (Note 4) GP11 I/O4 98 GP I/O; WD Timer Output /IRRX (Note 4) GP12 I/O4 99 GP I/O; Power Led output /IRTX (Note 4) GP13 I/O24

100 GP I/O; GP Address Decode (Note 4) GP14 I/O4 102 GP I/O; GP Write Strobe (Note 4) GP15 I/O4 103 GP I/O; Joy Read Strobe/JOYCS (Note 4) GP16 I/O4 104 GP I/O; Joy Write Strobe (Note 4) GP17 I/O4 105 GP I/O; IDE2 Output Enable/8042 P20 (Note 4) GP20 I/O4 106 GP I/O; Serial EEPROM Data In/AB_DATA (Note 4) GP21 I/O8 107 GP I/O; Serial EEPROM Data Out/AB_CLK (Note 4) GP22 I/O8 108 GP I/O; Serial EEPROM Clock (Note 4) GP23 I/O4 109 GP I/O; Serial EEPROM Enable (Note 4) GP24 I/O4 110 GP I/O; 8042 P21 (Note 4) GP25 I/O4

BIOS BUFFERS

111:118 ROM Bus (I/O to the SD Bus) (Note 4) RD[0:7] I/O4

119 ROM Chip Select (only used for ROM) (Note 4) nROMCS I 120 ROM Output Enable (DIR) (only used for ROM) (Note 4) nROMDIR I

Note 0: The interrupt request is output on one of the IRQx signals as 024 buffer type. If EPP or

ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts. In this case, the buffer type is OD24. Refer to the configuration section for more information.

Note 1: nCS -This pin is the active low chip select; it must be low for all chip accesses. For 12 bit

addressing, SA0:SA11, this input should be tied to GND. For 16 bit address qualification, address bits SA12:SA15 can be "ORed" together and applied to this pin. If IDE2 is not

used, SA12 can be connected to nCS, pin 27 to SA13, pin 28 to SA14 and pin 29 to SA15 Note 2: nYY - The "n" as the first letter of a signal name indicates an "Active Low" signal Note 3: nHDCS2 and nHDCS3 require a pull-up to ensure a logic high at power-up when used for

IDE2 until the Active Bit is set to 1. Note 4: See Table 1, Multifunction Pins with GPI/O and Other Alternate Functions.

TABLE 1 - DESCRIPTION OF MULTIFUNCTION PINS WITH GPI/O AND OTHER ALTERNATE

FUNCTIONS

No.

Original

Function

Alternate

Function 1

Alternate

Function 2

Alternate

Function 3

Buffer

Type

Default

Index

GPI/O

19 MEDIA_

ID1

GPI/O IR Mode IRR3 I/O8 float GP4 GP40

20 MEDIA_

ID0

GPI/O - - I/O8 float GP4 GP41

23 nIDE1_

GPI/O - - I/O4 high GP4 GP42

24 nHDCS0 GPI/O - - I/O24 high GP4 GP43 25 nHDCS1 GPI/O - - I/O24 high GP4 GP44 26 IDE1_IR

GPI/O - - I/O8 float GP4 GP45

30 nIOROP GPI/O Power LED

Output

WDT I/O24 float GP4 GP46

31 nIOWOP GPI/O nSMI - I/O24 float GP4 GP47 33 nPOWER

-ON

GPI/O - - I/O24 active low

open

collector

output

GP5 GP51

34 BUTTON

_ IN

GPI/O - - I/O24 input GP5 GP50

111 RD0 GPI/O Power LED

Output

- I/O4 RD0

1,4

GP6 GP60

112 RD1 GPI/O WDT - I/O4 RD1

1,4

GP6 GP61

113 RD2 GPI/O 8042 - P12 - I/O4 RD2

1,4

GP6 GP62

114 RD3 GPI/O 8042 - P13 - I/O4 RD3

1,4

GP6 GP63

115 RD4 GPI/O 8042 - P14 - I/O4 RD4

1,4

GP6 GP64

116 RD5 GPI/O 8042 - P15 - I/O4 RD5

1,4

GP6 GP65

117 RD6 GPI/O 8042 - P16 - I/O4 RD6

1,4

GP6 GP66

118 RD7 GPI/O 8042 - P17 - I/O4 RD7

1,4

GP6 GP67

119 nROMCS GPI/O - - I/O8 nROMCS

GP5 GP53

120 nROMOE GPI/O IR Mode IRR3 I/O8 nROMOE

GP5 GP54

153 nRI2 GPI/O - - I/O8 input

GP7 GP70

154 nDCD2 GPI/O - - I/O8 input

GP7 GP71

Pin No.

Original

Function

Alternate

Function 1

Alternate

Function 2

Alternate

Function 3

Buffer

Type

Default

Index

GPI/O

155 RXD2 GPI/O - - I/O8 input

GP7 GP72

156 TXD2 GPI/O - - I/O8 input

2,4

GP7 GP73

157 nDSR2 GPI/O - - I/O8 input

GP7 GP74

158 nRTS2 GPI/O - - I/O8 input

2,4

GP7 GP75

159 nCTS2 GPI/O - - I/O8 input

GP7 GP76

160 nDTR2 GPI/O - - I/O8 input

2,4

GP7 GP77 27 nHDCS2 SA13 - - I/O24 float - 28 nHDCS3 SA14 - - I/O24 float - 29 IDE2_IR

SA15 - - I float - -

53 nCS/

SA12

- - - I input - -

96 GPI/O IRQ in - - I/O4 input GP1 GP10 97 GPI/O IRQ in - - I/O4 input GP1 GP11 98 GPI/O

WDT

Timer

Output/

IRRX

- - I/O4 input GP1 GP12

99 GPI/O

Power LED

Output/

IRTX

- - I/O24 input GP1 GP13

100 GPI/O

Address

Decode

- - I/O4 input GP1 GP14

102 GPI/O

GP Write

Strobe

- - I/O4 input GP1 GP15

103 GPI/O

Joy Read

Strobe

JOYCS - I/O4 input GP1 GP16

104 GPI/O

Joy Write

Strobe

- - I/O4 input GP1 GP17

105 GPI/O

IDE2 Output Enable

8042 P20 - I/O4 input GP2 GP20

106 GPI/O

Serial

EEPROM

Data In

AB_DATA - I/O8

/OD8

(EN1)

input GP2 GP21

107 GPI/O

Serial

EEPROM

Data Out

AB_CLK - I/O8

/OD8

(EN1)

input GP2 GP22

Pin No.

Original

Function

Alternate

Function 1

Alternate

Function 2

Alternate

Function 3

Buffer

Type

Default

Index

GPI/O

108 GPI/O

Serial

EEPROM

Clock

- - I/O4 input GP2 GP23

109 GPI/O

Serial

EEPROM

Enable

- - I/O4 input GP2 GP24

110 GPI/O 8042 P21 - - I/O4 input GP2 GP25

Note 1: At power-up, RD0-RD7, nROMCS and nROMOE function as the XD Bus. To use RD0-RD7

for functions other than the XD Bus, nROMCS must stay high until those pins are finished

being reprogrammed. Note 2: These pins are input (high-z) until programmed for second serial port. Note 3: This is the trickle voltage input pin for the FDC37C93xFR. Note 4: These pins cannot be programmed as open drain pins in their original function. Note 5: No pins in their original function can be programmed as inverted input or inverted output.

BUFFER TYPE DESCRIPTIONS

I Input, TTL compatible. IS Input with Schmitt trigger. I/OD16P Input/Output, 16mA sink, 90uA pull-up. I/O24 Input/Output, 24mA sink, 12mA source. I/O4 Input/Output, 4mA sink, 2mA source. O4 Output, 4mA sink, 2mA source. O8SR Output, 8mA sink, 4mA source with Slew Rate Limiting. O16SR Output, 16mA sink, 8mA source with Slew Rate Limiting. O20 Output, 20mA sink, 10mA source. O24 Output, 24mA sink, 12mA source. OD24 Output, Open Drain, 24mA sink. OD48 Output, Open Drain, 48mA sink. ICLK Clock Input ICLK2 Clock Input OCLK2 Clock Output

FIGURE 1 - FDC37C93xFR BLOCK DIAGRAM

nDSR1, nDCD1, nRI1, nDTR1

TXD1, nCTS1, nRTS1

nINIT, nALF

HOST CPU

MULTI-MODE

PARALLEL

PORT/FDC

MUX

16C550

COMPATIBLE

SERIAL PORT 1

16C550

COMPATIBLE

SERIAL

PORT 2 WITH

INFRARED

IDE

CONFIGURATION

REGISTERS

POWER

MANAGEMENT

INTERFACE

CONTROL BUS

ADDRESS BUS

DATA BUS

nIOR

nIOW

AEN

SA[0:12] (nCS)

SD[O:7]

DRQ[0:3]

nDACK[0:3]

IRQ[1,3-12,14,15]

RESET_DRV

CLOCK

GEN

ICLOCK (14.318)

nINDEX

nTRK0

nDSKCHG

nWRPRT

nWGATE

DENSEL

nDIR

nSTEP

nHDSEL

nDS0,1

nMTR0,1

RDATA

RCLOCK

WDATA

WCLOCK

nWDATAnRDATA

nIDE1_OE

nHDCS0, nHDCS1

TXD2(IRTX), nCTS2, nRTS2 RXD2(IRRX)

nDSR2, nDCD2, nRI2, nDTR2

RXD1

PD0-7

BUSY, SLCT, PE, nERROR, nACK

nSTB, nSLCTIN,

SMC

PROPRIETARY

82077

COMPATIBLE

VERTICAL

FLOPPYDISK

CONTROLLER

CORE

DIGITAL

DATA SEPARATOR WITH WRITE

PRECOM-

PENSATION

IOCHRDY

DECODER

nGPA

nGPCS*

nGPWR*

BIOS

BUFFER

nROMDIR nROMCS RD[0:7]

GENERAL PURPOSE

I/O

GP1[0:7]* GP2[0:5]*

IRRX*, IRTX*

IDE1_IRQ

8042

RTC

KCLK KDATA MCLK MDATA P20*, P21*

XTAL1,2 VBAT

DRVDEN0

DRVDEN1

SERIAL

EEPROM

DATAIN*

DATAOUT*

CLK*, ENABLE*

IDE2

OPTIONAL

nHDCS2,3 IDE2_IRQ

nIOROP

nIOWOP

MID0, MID1

CLKO[1:3]

(14.318)

HCLK 16CLK

*Multi-Function I/O Pin - Optional

SA[13-15]

P12*, P13*, P14*,P15*, P16*, P17*

GP[4[0:7]*, GP5[0:1,3:4]*, GP6[0:7]*, GP7[0:7]*

IRR3*/Mode*

ACCESS.bus

SOFT

POWER

MANAGEMENT

SMI

nPowerOn

Button_In

AB_DATA*

AB_CLK*

VTR

nSMI*

Vcc Vss

FUNCTIONAL DESCRIPTION

SUPER I/O REGISTERS

The address map, shown below in Table 2, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, IDE, serial and parallel ports, Bank 2 of the RTC registers, auxiliary I/O and ACCESS.bus can be moved via the configuration registers. Some addresses are used to access more than one register.

HOST PROCESSOR INTERFACE

The host processor communicates with the FDC37C93xFR through a series of read/write registers. The port addresses for these registers are shown in Table 2. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide except the IDE data register at port 1F0H which is 16 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA.

Table 2 - Super I/O Block Addresses

ADDRESS BLOCK NAME

LOGICAL

DEVICE NOTES

Base+(0-5) and +(7) Floppy Disk 0 Base+(0-7) Serial Port Com 1 4 Base1+(0-7)

Base2+(0-7)

Serial Port Com 2 5

IR Support Fast IR

Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402)

Parallel Port SPP EPP ECP ECP+EPP+SPP

Base1+(0-7), Base2+(0) IDE 1 1 Base1+(0-7), Base2+(0) IDE 2 2 70, 71

Base2+(0,1)

RTC 6

60, 64 KYBD 7 Base1+(0)

Base2+(0)

Aux. I/O 8 GPR

GPW

Base+(0-3) ACCESS.bus 9

Note 1: Refer to the configuration register descriptions for setting the base address

FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection.

The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.

FDC INTERNAL REGISTERS

The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 3 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected.

Table 3 - Status, Data and Control Registers

(Shown with base addresses of 3F0 and 370)

PRIMARY

ADDRESS

SECONDARY

ADDRESS R/W REGISTER

3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7

370 371 372 373 374 374 375 376 377 377

R R/W R/W

R/W

Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Tape Drive Register (TSR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR)

STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state of the FINTR pin and several disk interface

pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0-D7 are held in a high impedance state for a read of address 3F0.

PS/2 Mode

BIT 0 DIRECTION

Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction.

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected.

BIT 2 nINDEX

Active low status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0.

BIT 4 nTRACK 0

Active low status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the STEP output disk interface output pin.

BIT 6 nDRV2

Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

7 6 5 4 3 2 1 0

INT

PENDING

nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR

RESET COND.

0 N/A 0 N/A 0 N/A N/A 0

PS/2 Model 30 Mode

BIT 0 nDIRECTION

Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction.

BIT 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected.

BIT 2 INDEX

Active high status of the INDEX disk interface input.

BIT 3 nHEAD SELECT

Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0.

BIT 4 TRACK 0

Active high status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active and is cleared with a read from the DIR register or with a hardware or software reset.

BIT 6 DMA REQUEST

Active high status of the DRQ output pin.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

7 6 5 4 3 2 1 0

INT

PENDING

DRQ STEP

F/F

TRK0 nHDSEL INDX WP nDIR

RESET COND.

0 0 0 N/A 1 N/A N/A 1

STATUS REGISTER B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state of several disk interface pins in PS/2 and

Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0-D7 are held in a high impedance state for a read of address 3F1.

PS/2 Mode

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

7 6 5 4 3 2 1 0 1 1 DRIVE

SEL0

WDATA

TOGGLE

RDATA

TOGGLE

WGATE MOT

EN1

MOT

EN0

RESET COND.

1 1 0 0 0 0 0 0

PS/2 Model 30 Mode

BIT 0 nDRIVE SELECT 2

Active low status of the DS2 disk interface output.

BIT 1 nDRIVE SELECT 3

Active low status of the DS3 disk interface output.

BIT 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA

Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register.

BIT 4 WRITE DATA

Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface output.

BIT 7 nDRV2

Active low status of the DRV2 disk interface input.

7 6 5 4 3 2 1 0

nDRV2 nDS1 nDS0 WDATA

F/F

RDATA

F/F

WGATE

F/F

nDS3 nDS2

RESET COND.

N/A 1 1 0 0 0 1 1

DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It

also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.

BIT 0 and 1 DRIVE SELECT

These two bits are binary encoded for the four drive selects DS0 -DS3, thereby allowing only one drive to be selected at one time.

BIT 2 nRESET

A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. When this bit is a logic "0" it disables the nDACK and TC inputs, and holds the DRQ and FINTR outputs in a high impedance state. This bit is a logic "0" after a reset and in these modes.

PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 6 MOTOR ENABLE 2

This bit controls the MTR2 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 7 MOTOR ENABLE 3

This bit controls the MTR3 disk interface output. A logic "1" in this bit causes the output to go active.

Table 4 - Drive Activation Values

7 6 5 4 3 2 1 0

MOT

EN3

MOT EN2

MOT

EN1

MOT EN0

DMAEN nRESETDRIVE

SEL1

DRIVE

SEL0

RESET

COND.

0 0 0 0 0 0 0 0

DRIVE DOR VALUE

0 1 2 3

1CH 2DH 4EH 8FH

TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

This register is included for 82077 software compatibility. The robust digital data separator used in the FDC does not require its characteristics modified for tape support. The contents of this register are not used internal to the device. The TDR is unaffected by a software reset. Bits 2-7 are tri-stated when read in this mode.

Table 5 - Tape Select Bits

Table 6 - Internal 2 Drive Decode - Normal

DIGITAL OUTPUT REGISTER

DRIVE SELECT

OUTPUTS (ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 1 0 nBIT 5 nBIT 4 X X 1 X 0 1 0 1 nBIT 5 nBIT 4 X 1 X X 1 0 1 1 nBIT 5 nBIT 4 1 X X X 1 1 1 1 nBIT 5 nBIT 4 0 0 0 0 X X 1 1 nBIT 5 nBIT 4

Table 7 - Internal 2 Drive Decode - Drives 0 and 1 Swapped

DIGITAL OUTPUT REGISTER

DRIVE SELECT

OUTPUTS (ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 0 1 nBIT 4 nBIT 5 X X 1 X 0 1 1 0 nBIT 4 nBIT 5 X 1 X X 1 0 1 1 nBIT 4 nBIT 5 1 X X X 1 1 1 1 nBIT 4 nBIT 5 0 0 0 0 X X 1 1 nBIT 4 nBIT 5

TAPE SEL1 TAPE SEL2

DRIVE

SELECTED

0 0 1 1

0 1 0 1

None

1 2 3

Normal Floppy Mode

Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance.

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state tape sel1 tape sel0

Enhanced Floppy Mode 2 (OS2)

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Media

ID1

Media

ID0

Drive Type ID Floppy Boot Drive tape sel1 tape sel0

For this mode, MEDIA_ID[1:0] pins are gated into bits 6 and 7 of the 3F3 register. These two bits are not affected by a hard or soft reset.

BIT 7 MEDIA ID 1 READ ONLY (Pin 19) (See Table 8)

BIT 6 MEDIA ID 0 READ ONLY (Pin 20) (See Table 9)

BIT 5-4 DRIVE TYPE ID - These bits reflect two of the bits of L0-CRF1. Which two bits these are depends on the last drive selected in the Digital Output Register (3F2). (See Table 10)

Note: L0-CRF1-B5 = Logical Device 0,

Configuration Register F1, Bit 5

BIT 3-2 FLOPPY BOOT DRIVE - These bits

reflect the value of L0-CRF1. Bit 3 = L0-CRF1B7. Bit 2 = L0-CRF1-B6.

BIT 1-0 TAPE DRIVE SELECT (READ/WRITE). Same as in Normal and Enhanced Floppy Mode. 1.

Table 8 - Media ID1

MEDIA ID1

INPUT BIT 7

Pin 19 L0-CRF1-B5

= 0

L0-CRF1-B5

= 1 0 0 1 1 1 0

Table 9 - Media ID0

MEDIA ID0

INPUT BIT 6

Pin 20 CRF1-B4

= 0

CRF1-B4

= 1

0 0 1 1 1 0

Table 10 - Drive Type ID

DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID

BIT 1 BIT 0 BIT 5 BIT 4

0 0 L0-CRF2 - B1 L0-CRF2 - B0 0 1 L0-CRF2 - B3 L0-CRF2 - B2 1 0 L0-CRF2 - B5 L0-CRF2 - B4 1 1 L0-CRF2 - B7 L0-CRF2 - B6

Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.

DATA RATE SELECT REGISTER (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR), not the DSR, for PC/AT and PS/2 Model

30 and Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps.

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 12 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BIT 2 through 4 PRECOMPENSATION SELECT

These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 11 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. This starting track number can be changed by the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER

A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register.

BIT 7 SOFTWARE RESET

This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.

7 6 5 4 3 2 1 0

S/W

RESET

POWER

DOWN

0 PRE-

COMP2

PRE-

COMP1

PRE-

COMP0

DRATE

SEL1

DRATE

SEL0

RESET

COND.

0 0 0 0 0 0 1 0

Table 11 - Precompensation Delays

*2 Mbps data rate is only available if VCC = 5V.

Table 12 - Default Precompensation Delays

*2 Mbps data rate is only available if VCC = 5V.

PRECOMP

432

PRECOMPENSATION

DELAY (nsec)

<2Mbps 2Mbps*

111 001 010 011 100 101 110 000

0.00

41.67

83.34

125.00

166.67

208.33

250.00

Default

20.8

41.7

62.5

83.3

104.2 125

Default

Default: See Table 13

DATA RATE

PRECOMPENSATION

DELAYS

2 Mbps*

1 Mbps 500 Kbps 300 Kbps 250 Kbps

20.8 ns

41.67 ns 125 ns 125 ns 125 ns

Table 13 - Data Rates

DRIVE RATE

DATA RATE DATA RATE DENSEL DRATE(1)

DRT1 DRT0 SEL1 SEL0 MFM FM 1 0

0 0 1 1 1Meg --- 1 1 1 0 0 0 0 500 250 1 0 0 0 0 0 1 300 150 0 0 1 0 0 1 0 250 125 0 1 0

0 1 1 1 1Meg --- 1 1 1 0 1 0 0 500 250 1 0 0 0 1 0 1 500 250 0 0 1 0 1 1 0 250 125 0 1 0

1 0 1 1 1Meg --- 1 1 1 1 0 0 0 500 250 1 0 0 1 0 0 1 2Meg --- 0 0 1 1 0 1 0 250 125 0 1 0

Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format

01 = 3-Mode Drive 10 = 2 Meg Tape

Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.

Table 14 - DRVDEN Mapping

DT1 DT0 DRVDEN1 (1) DRVDEN0 (1) DRIVE TYPE

0 0 DRATE0 DENSEL 4/2/1 MB 3.5"

2/1 MB 5.25" FDDS

2/1.6/1 MB 3.5" (3-MODE) 1 0 DRATE0 DRATE1 0 1 DRATE0 nDENSEL PS/2 1 1 DRATE1 DRATE0

MAIN STATUS REGISTER

Address 3F4 READ ONLY

The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any

time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer.

BIT 0-3 DRV x BUSY

These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates.

BIT 4 COMMAND BUSY

This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte.

BIT 5 NON-DMA

This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a command. This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes.

BIT 6 DIO

Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.

BIT 7 RQM

Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.

7 6 5 4 3 2 1 0

RQM DIO NON

DMA

CMD

BUSY

DRV3 BUSY

DRV2 BUSY

DRV1

BUSY

DRV0 BUSY

DATA REGISTER (FIFO)

Address 3F5 READ/WRITE

All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register.

Data transfers are governed by the RQM and DIO bits in the Main Status Register.

The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 15 gives several examples of the delays with a

FIFO. The data is based upon the following formula:

At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred.

An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.

Table 15 - FIFO Service Delay

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT 2

Mbps* DATA RATE

1 byte 2 bytes 8 bytes

15 bytes

1 x 4 µs - 1.5 µs = 2.5 µs 2 x 4 µs - 1.5 µs = 6.5 µs 8 x 4 µs - 1.5 µs = 30.5 µs 15 x 4 µs - 1.5 µs = 58.5 µs

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT 1

Mbps DATA RATE

1 byte 2 bytes 8 bytes

15 bytes

1 x 8 µs - 1.5 µs = 6.5 µs 2 x 8 µs - 1.5 µs = 14.5 µs 8 x 8 µs - 1.5 µs = 62.5 µs 15 x 8 µs - 1.5 µs = 118.5 µs

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT

500 Kbps DATA RATE

1 byte 2 bytes 8 bytes

15 bytes

1 x 16 µs - 1.5 µs = 14.5 µs 2 x 16 µs - 1.5 µs = 30.5 µs 8 x 16 µs - 1.5 µs = 126.5 µs 15 x 16 µs - 1.5 µs = 238.5 µs

*The 2 Mbps data rate is only available if VCC = 5V.

Threshold # x 1

DATA RATE

x 8

- 1.5 µs = DELAY

DIGITAL INPUT REGISTER (DIR)

Address 3F7 READ ONLY

This register is read-only in all modes.

PC/AT Mode

BIT 0-6 UNDEFINED

The data bus outputs D0 - 6 will remain in a high impedance state during a read of this register.

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable.

PS/2 Mode

BIT 0 nHIGH DENS

This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected.

BIT 1 and 2 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a

software reset and are set to 250 Kbps after a hardware reset.

BIT 3-6 UNDEFINED

Always read as a logic "1"

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable.

7 6 5 4 3 2 1 0

DSK

CHG

RESET COND.

N/A N/A N/A N/A N/A N/A N/A N/A

7 6 5 4 3 2 1 0

DSK

CHG

1 1 1 1 DRATE

SEL1

DRATE

SEL0

nHIGH

nDENS

RESET

COND.

N/A N/A N/A N/A N/A N/A N/A 1

Model 30 Mode

BIT 0-1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BIT 2 NOPREC

This bit reflects the value of NOPREC bit set in the CCR register.

BIT 3 DMAEN

This bit reflects the value of DMAEN bit set in the DOR register bit 3.

BIT 4-6 UNDEFINED

Always read as a logic "0"

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the pin.

7 6 5 4 3 2 1 0

DSK

CHG

0 0 0 DMAEN NOPREC DRATE

SEL1

DRATE

SEL0

RESET COND.

N/A 0 0 0 0 0 1 0

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