Standard Microsystems Corporation FDC37C669 Datasheet

FDC37C669

PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support

FEATURES

5 Volt Operation

Intelligent Auto Power Management

16 Bit Address Qualification (Optional)

2.88MB Super I/O Floppy Disk Controller

- Licensed CMOS 765B Floppy Disk Controller

- Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core

- Supports Two Floppy Drives Directly

- Supports Vertical Recording Format

- 16 Byte Data FIFO

- 100% IBM Compatibility

- Detects All Overrun and Underrun Conditions

- Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption

- DMA Enable Logic

- Data Rate and Drive Control Registers

- Swap Drives A and B

- Non-Burst Mode DMA option

- 48 Base I/O Address, Three DMA Options

Floppy Disk Available on Parallel Port Pins

Enhanced Digital Data Separator

- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates

- Programmable Precompensation Modes

Serial Ports

- Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs

- Supports 230k and 460k Baud

- Programmable Baud Rate Generator

Seven

IRQ and

- Modem Control Circuitry

- Infrared - IrDA (HPSIR) and Amplitude Shift Keyed IR (ASKIR)

- Alternate IR Pins (Optional)

- 96 Base I/O Address and Eight IRQ Options

Multi-Mode Parallel Port with ChiProtect

- Standard Mode

- IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port Enhanced Parallel Port (EPP) Compatible

- EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

- Enhanced Capabilities Port (ECP) Compatible (IEEE 1284 Compliant)

- Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On

- 192 Base I/O Address, Seven IRQ and Three DMA Options

ISA Host Interface

IDE Interface (Optional)

- On-Chip Decode and Select Logic Compatible with IBM PC/XT and PC/AT Embedded Hard Disk Drives

- 48 Base I/O Address and Options

Game Port Select Logic

- 48 Base I/O Addresses

General Purpose Address Decoder

- 16 Byte Block decode

- 48 Base I/O Address Options

100 Pin QFP and TQFP Package

Seven

IRQ

TABLE OF CONTENTS

FEATURES............................................................................................................................................ 1

GENERAL DESCRIPTION..................................................................................................................... 3

PIN CONFIGURATION........................................................................................................................... 4

DESCRIPTION OF PIN FUNCTIONS..................................................................................................... 6

FUNCTIONAL DESCRIPTION............................................................................................................. 17

SUPER I/O REGISTERS.................................................................................................................. 17

HOST PROCESSOR INTERFACE.................................................................................................. 17

FLOPPY DISK CONTROLLER........................................................................................................ 18

FLOPPY DISK CONTROLLER INTERNAL REGISTERS ................................................................ 18

COMMAND SET/DESCRIPTIONS....................................................................................................... 41

INSTRUCTION SET.............................................................................................................................. 45

PARALLEL PORT FLOPPY DISK CONTROLLER................................................................................ 71

SERIAL PORT (UART) ......................................................................................................................... 73

INFRARED INTERFACE........................................................................................................................87

PARALLEL PORT................................................................................................................................ 88

IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES................................................... 90

EXTENDED CAPABILITIES PARALLEL PORT.............................................................................. 96

AUTO POWER MANAGEMENT..........................................................................................................109

INTEGRATED DRIVE ELECTRONICS INTERFACE......................................................................... 114

CONFIGURATION.............................................................................................................................. 118

OPERATIONAL DESCRIPTION......................................................................................................... 137

MAXIMUM GUARANTEED RATINGS........................................................................................... 137

DC ELECTRICAL CHARACTERISTICS....................................................................................... 137

TIMING DIAGRAMS............................................................................................................................ 140

ECP PARALLEL PORT TIMING.....................................................................................................157

GENERAL DESCRIP TION

The SMSC FDC37C669 PC 95 Compatible Super I/O Floppy Disk Controller with Infrared Support utilizes SMSC's proven SuperCell technology for increased product reliability and functionality. The FDC37C669 is PC95 compliant and is optimized for motherboard applications. The FDC37C669 supports both 1 Mbps and 2 Mbps data rates and vertical vertical recording operation at 1 Mbps Data Rate.

The FDC37C669 incorporates SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP support, IDE interface, on-chip 12 mA AT bus drivers, game port chip select and two floppy direct drive support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550. One UART includes additional support for a Serial Infrared Interface, complying with IrDA, HPSIR, and ASKIR

formats (used by Sharp, Apple Newton, and other PDAs). The parallel port, the IDE interface, and the game port select logic are compatible with IBM PC/AT architectures. The FDC37C669 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes.

The FDC37C669 Floppy Disk Controller incorporates Software Configurable Logic (SCL) for ease of use. Use of the SCL feature allows programmable system configuration of key functions such as the FDC, parallel port, and UARTs. The parallel port ChiProtect prevents damage caused by the printer being powered when the FDC37C669 is not powered.

The FDC37C669 does not require any external filter components, and is, therefore easy to use and offers lower system cost and reduced board area. The FDC37C669 is software and register compatible with SMSC's proprietary 82077AA core.

DRVDEN0

nMTR0

nDS1

nDS0

nMTR1

VSS

nDIR

nSTEP

nWDATA

nWGATE

nHDSEL

nINDEX

nTRK0

nWRTPRT

VCC

nRDATA

nDSKCHG

DRVDEN1

IRQ_A

CLK14

DRQ_A

nDACK_A

IRQIN

nIDEEN/IRQ_H

nHDCS0/IRRX2

nHDCS1/IRTX2

nCS

1234567891011121314151617181920212223242526272829

nDSR1

TXD1

RXD1

nSTROBE

nAUTOFD

nERROR

nINIT

nSLCTIN

VCC

PD0

PD1

PD2

PD3

VSS

PD4

PD5

PD6

PD7

nACK

BUSYPESLCT

PWRGD/GAMECS

RESETD7D6D5D4

DRQ_B

8079787776757473727170696867666564636261605958575655545352

nRTS1 nCTS1

nDTR1

nRI1

nDCD1

nRI2

nDCD2

RXD2/IRRX

TXD2/IRTX

nDSR2

nRTS2 nCTS2 nDTR2

DRV2/ADRX/IRQ_B

VSS

nDACK_C

A10

DRQ_C

IOCHRDY

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

PIN CONFIGURATION

FDC37C669

100 PIN QFP

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

D2 D1 D0 VSS AEN nIOW nIOR A9 A8 A7 IRQ_F IRQ_E IRQ_D IRQ_C nDACK_B TC A6 A5 A4 A3

DRVDEN0

262728

47 4849

nHDCS1/IRTX2

nCS

A0A1A2A3A4A5A6

nDACK_B

IRQ_C

IRQ_D

IRQ_E

IRQ_F

A7A8A9

nIOR

nIOW

AEN

VSS

D0D1D2

100

IOCHRDY

DRQ_CNCA10

nDACK_C

VSS

DRV2/ADRX/IRQ_B

nDTR2

nCTS2

nRTS2

nDSR2

TXD2/IRTX

RXD2/IRRX

nDCD2

nRI2

nDCD1

nRI1

nDTR1

nCTS1

nRTS1

nDSR1

TXD1

RXD1

nSTROBE

nAUTOFD

nMTR0

nDS1 nDS0

nMTR1

VSS

nDIR

nSTEP

nWDATA

nWGATE

nHDSEL

nINDEX

nTRK0

nWRTPRT

VCC

nRDATA nDSKCHG DRVDEN1

IRQ_A

CLK14

DRQ_A

nDACK_A

IRQIN

nIDEEN/IRQ_H

nHDCS0/IRRX2

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

24 25

FDC37C669

100 PIN TQFP

nERROR

nINIT

nSLCTIN

VCC

PD0

PD1

PD2

PD3

VSS

PD4

PD5

PD6

PD7

nACK

BUSY

SLCT

PWRGD/GAMECS

RESET

DRQ_B

DESCRIPTION OF PIN FUNCTIONS

QFP/

TQFP

PIN NO.

48-51 53-56

44 nI/O Read nIOR I This active low signal is issued by the host

45 nI/O Write nIOW I This active low signal is issued by the host

46 Address Enable AEN I Active high Address Enable indicates DMA

28-34

41-43,

21,52,99DMA Request

22,36,96nDMA

35 Terminal Count TC I This signal indicates to the chip that DMA

NAME SYMBOL

HOST PROCESSOR INTERFACE

Data Bus 0-7 D0-D7

I/O Address A0-A10 I These host address bits determine the I/O

DRQ_A

A, B, C

Acknowledge A, B, C

DRQ_B DRQ_C

nDACK_A nDACK_B nDACK_C

BUFFER

TYPE

I/O24

O24

The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a highimpedance state when not in the output mode.

microprocessor to indicate a read operation.

microprocessor to indicate a write operation.

operations on the host data bus. Used internally to qualify appropriate address decodes.

address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW. All internal address decodes use the full A0 to A10 address bits.

This active high output is the DMA request for byte transfers of data between the host and the chip. This signal is cleared on the last byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode).

I An active low input acknowledging the

request for a DMA transfer of data between the host and the chip. This input enables the DMA read or write internally.

data transfer is complete. TC is only accepted when nDACK_x is low. In AT and PS/2 model 30 modes, TC is active high and in PS/2 mode, TC is active low.

DESCRIPTION

DESCRIPTION OF PIN FUNCTIONS

QFP/

TQFP

PIN NO.

19,

37-40,

27 Chip Select Input nCS I When enabled, this active low pin serves as

57 Reset RESET IS This active high signal resets the chip and

16 nRead Disk Data nRDATA IS Raw serial bit stream from the disk drive,

10 nWrite

9 nWrite

11 nHead

NAME SYMBOL

Interrupt Request

A, C, D, E, F,

Gate

Data

Select

IRQ_A IRQ_C IRQ_D IRQ_E IRQ_F

FLOPPY DISK INTERFACE

nWGATE

nWDATA

nHDSEL

BUFFER

TYPE

O24

OD24

OD48

DESCRIPTION

The interrupt request from the logical device or IRQIN is output on one of the IRQA-G signals. Refer to the configuration registers for more information.

If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts.

an input for an external decoder circuit which is used to qualify address lines above A10.

must be valid for 500 ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset.

low active. Each falling edge represents a flux transition of the encoded data.

This active low high current driver allows current to flow through the write head. It becomes active just prior to writing to the diskette.

This active low high current driver provides the encoded data to the disk drive. Each falling edge causes a flux transition on the media.

This high current output selects the floppy disk side for reading or writing. A logic "1" on this pin means side 0 will be accessed, while a logic "0" means side 1 will be accessed.

DESCRIPTION OF PIN FUNCTIONS

QFP/

TQFP

PIN NO.

7 Direction

8 nStep Pulse nSTEP

17 Disk Change nDSKCHG IS This input senses that the drive door is open

4,3 nDrive Select

2,5 nMotor On 0,1 nMTR0,1

1 DRVDEN0 DRVDEN0

14 nWrite

13 wTrack 00 nTRK00 IS This active low Schmitt Trigger input senses

12 nIndex nINDEX IS This active low Schmitt Trigger input senses

18 DRVDEN1 DRVDEN 1

88 Receive Data 2 RXD2/IRRX I Receiver serial data input for port 2. IR

NAME SYMBOL

nDIR

Control

nDS0,1

O,1

nWRTPRT IS This active low Schmitt Trigger input senses

Protected

SERIAL PORT INTERFACE

BUFFER

TYPE

OD48

DESCRIPTION

This high current low active output determines the direction of the head movement. A logic "1" on this pin means outward motion, while a logic "0" means inward motion.

This active low high current driver issues a low pulse for each track-to-track movement of the head.

or that the diskette has possibly been changed since the last drive selection. This input is inverted and read via bit 7 of I/O address 3F7H.

Active low open drain outputs select drives 0-1.

These active low open drain outputs select motor drives 0-1.

Indicates the drive and media selected. Refer to configuration registers CR03, CR0B, CR1F.

from the disk drive that a disk is write protected. Any write command is ignored.

from the disk drive that the head is positioned over the outermost track.

from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole.

Indicates the drive and media selected. Refer to configuration registers CR03, CR0B, CR1F.

Receive Data

DESCRIPTION OF PIN FUNCTIONS

QFP/

TQFP

PIN NO.

89 Transmit Data 2 TXD2/IRTX

78 Receive Data 1 RXD1 I Reciever serial data input for port 1. 79 Transmit Data 1 TXD1

81,91 nRequest to

NAME SYMBOL

nRTS1

Send

nRTS2 (SYSOPT)

(System Option)

BUFFER

TYPE

O24

024

DESCRIPTION

Transmit serial data output for port 2. IR transmit data.

Transmit serial data output for port 1. Active low Request to Send outputs for the

Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). Forced inactive during loop mode operation.

At the trailing edge of hardware reset, the nRTS2 input is latched to determine the configuration base address.

0 : INDEX Base I/O Address = 3F0 Hex 1 : INDEX Base I/O Address = 370 Hex

83,93 nData Terminal

Ready

nDTR1

nDTR2

Active low Data Terminal Ready outputs for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). Forced inactive during loop mode operation.

DESCRIPTION OF PIN FUNCTIONS

QFP/

TQFP

PIN NO.

82,92 nClear to Send nCTS1

80,90 nData Set Ready nDSR1

85,87 nData Carrier

NAME SYMBOL

nCTS2

nDSR2

nDCD1

Detect

nDCD2

BUFFER

TYPE

I Active low Clear to Send inputs for the serial

port. Handshake signal which notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS.

I Active low Data Set Ready inputs for the

serial port. Handshake signal which notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR.

I Active low Data Carrier Detect inputs for the

serial port. Handshake signal which notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD.

DESCRIPTION

DESCRIPTION OF PIN FUNCTIONS

QFP/

TQFP

PIN NO.

84,86 nRing Indicator nRI1

73 nPrinter Select

NAME SYMBOL

nRI2

nSLCTIN OD24

Input

BUFFER

TYPE

I Active low Ring Indicator inputs for the

serial port. Handshake signal which notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI.

PARALLEL PORT INTERFACE

This active low output selects the printer. This is the complement of bit 3 of the Printer Control Register.

DESCRIPTION

0P24

74 nInitiate Output nINIT OD24

0P24

76 nAutofeed

Output

nAUTOFD OD24

0P24

Refer to Parallel Port description for use of this pin in ECP and EPP mode.

This output is bit 2 of the printer control register. This is used to initiate the printer when low.

Refer to Parallel Port description for use of this pin in ECP and EPP mode.

This output goes low to cause the printer to automatically feed one line after each line is printed. The nAUTOFD output is the complement of bit 1 of the Printer Control Register.

Refer to Parallel Port description for use of this pin in ECP and EPP mode.

DESCRIPTION OF PIN FUNCTIONS

QFP/

TQFP

PIN NO.

77 nStrobe Output nSTROBE OD24

61 Busy BUSY I This is a status output from the printer, a

62 nAcknowledge nACK I A low active output from the printer

60 Paper End PE I Another status output from the printer, a

59 Printer Selected

75 nError nERROR I A low on this input from the printer indicates

NAME SYMBOL

SLCT I This high active output from the printer

Status

BUFFER

TYPE

0P24

DESCRIPTION

An active low pulse on this output is used to strobe the printer data into the printer. The nSTROBE output is the complement of bit 0 of the Printer Control Register.

Refer to Parallel Port description for use of this pin in ECP and EPP mode.

high indicating that the printer is not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.

indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.

high indicating that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.

indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.

that there is a error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.

QFP/

TQFP

PIN NO.

63-66 68-71

DESCRIPTION OF PIN FUNCTIONS

NAME SYMBOL

Port Data PD0-PD7

BUFFER

TYPE

I/O24

DESCRIPTION

The bi-directional parallel data bus is used to transfer information between CPU and peripherals.

100 IOCHRDY IOCHRDY

24 nIDE Enable

Interrupt Request H

25 nIDE Chip

Select 0

IRRX2

26 nIDE Chip

Select 1

nIDEEN

IRQ_H

nHDCS0

IRRX2 nHDCS1

OD24P

IDE/ALT IR PINS

O24P

(Note 1)

024

OD24

O24P

(Note 1)

O24P

(Note 1)

In EPP mode, this pin is pulled low to extend the read/write command. This pin has an internal pull-up.

This active low signal is active when the IDE is enabled and the I/O address is accessing an IDE register.

The interrupt request from a logical device or IRQIN may be output on the IRQH signal. Refer to the configuration registers for more information.

If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts.

This is the Hard Disk Chip select corresponding to the eight control block addresses.

Alternate IR Receive input This is the Hard Disk Chip select

corresponding to the alternate status register.

IR Transmit 2

20 CLOCK 14 CLK14 ICLK The external connection to a single source

IRTX2

O24P

MISCELLANEOUS

Alternate IR transmit output

14.318 MHz clock.

QFP/

TQFP

PIN NO.

94 Drive 2

DESCRIPTION OF PIN FUNCTIONS

NAME SYMBOL

DRV2

BUFFER

TYPE

DESCRIPTION

In PS/2 mode, this input indicates whether a second drive is connected; DRV2 should be low if a second drive is connected. This status is reflected in a read of Status Register A.

Address X

Interrupt Request B

23 IRQIN I This pin is used to steer an interrupt signal

58 PWRGD

nADRX

IRQ_B

OD24

024

(OD24)

Active low address decode out: used to decode a 1, 8, or 16 byte address block. (An external pull-up is required). Refer to Configuration registers CR03, CR08 and CR09 for more information. This pin has a 30ua internal pull-up. The interrupt request from a logical device or IRQIN may be output on IRQ_B. Refer to the configuration registers for more information.

(If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts.)

from an external device onto one of eight IRQ outputs IRQA-H.

This active high input indicates that the power (VCC) is valid. For device operation, PWRGD must be active. When PWRGD is inactive, all inputs to Mercury are disconnected and put into a low power mode; all outputs are put into high impedance. The contents of all registers are preserved as long as VCC has a valid value. The driver current drain in this mode drops to ISTBY - standby current. This input has an internal 30ua pull-up.

98 I/O Power

nGAMECS

This is the Game Port Chip Select output active low. It will go active when the I/O address, qualified by AEN, matches that selected in Configuration register CR1E.

No Connect

DESCRIPTION OF PIN FUNCTIONS

QFP/

TQFP

PIN NO.

NAME SYMBOL

15,72 Power V

6,47,

Ground GND Ground Supply.

BUFFER

TYPE

DESCRIPTION

Positive Supply Voltage.

67,95

Note 1: Refer to Configuration Register 00 for information on the pull-ups for these pins! Note IDE does not decode for 377, 3F7 Note RI and the Serial interrupt is always active if system power is applied to the chip.

BUFFER TYPE DESCRIPTIONS

BUFFER TYPE

DESCRIPTION

I/O24 Input/Output. 24 mA sink; 12 mA source

O24 Output. 24 mA sink; 12 mA source

OD48 Open drain. 48 mA sink

O4 Output. 4 mA sink; 2 mA source

OD24

OD24P

Output. 24 mA sink Open drain. 24 mA sink; 30µA source

OP24 Output. 24 mA sink; 4 mA source

024P

Output. 24 mA sink; 12 mA source; with 30µA pull-up

OCLK Output to external crystal

ICLK Input to Crystal Oscillator Circuit (CMOS levels)

I Input TTL compatible.

IS Input with Schmitt Trigger.

DRV2(nADRX)(IRQB)

nCS

nIOR

nIOW

AEN

A0-A10

D0-D7

DRQ_A-C

nDACK_A-C

IRQA

IRQ_C-F

RESET

IRQIN

IOCHRDY

5 V

Vcc (2)

HOST CPU

INTERFACE

14.318

CLOCK

Vss (4)

CLOCK

GEN

PWRGD

POWER

MANAGEMENT

ADDRESS BUS

PROPRIETARY

82077 COMPATIBLE

FLOPPYDISK

CONTROLLER

nINDEX nTRK0

nDSKCHG

nWRPRT nWGATE

SMSC

VERTICAL

CORE

nDIR

nSTEP

DRVDEN0 DRVDEN1

DATA BUS

CONFIGURATION

REGISTERS

CONTROL BUS

WDATA

WCLOCK

RCLOCK

RDATA

nDS0,1,2

nMTR0,1,2

DIGITAL

DATA

SEPARATOR

WITH WRITE

PRECOM-

PENSATION

nWDATA nRDATA

MULTI-MODE

PARALLEL PORT/FDC

MUX

GENERAL PURPOSE ADDRESS DECODER

16C550

COMPATIBLE

SERIAL PORT 1

16C550

COMPATIBLE

SERIAL

PORT 2 WITH

INFRARED

IDE

INTERFACE

GAME PORT DECODER

PD0-7

BUSY, SLCT, PE, nERROR, nACK

nSTROBE, nSLCTIN, nINIT, nAUTOFD

ADRX

TXD1, nCTS1, nRTS1 RXD1

nDSR1, nDCD1, nRI, nDTR1

TXD2(IRTX),nCTS2,nRTS2

RXD2(IRRX) nDSR2,nDCD2,nRI2,nDTR2

nIDEEN(IRQH)

nHDCSO(IRRX2)

nHDCS1(IRTX2)

nGAMECS

FIGURE 1 - FDC37C669 BLOCK DIAGRAM

FUNCTIONAL DESCRIPTION

SUPER I/O REGISTERS

The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, IDE, serial and parallel ports can be moved via the configuration registers. Some addresses are used to access more than one register.

Table 1 - FDC37C669 Block Addresses

ADDRESS BLOCK NAME NOTES

3F0, 3F1 or 370, 371 Configuration Write only; Note 1, 2 Base +0,1 Floppy Disk Read only; Disabled at power

Base +[2:5, 7] Floppy Disk Disabled at power up; Note 2 Base +[0:7] Serial Port Com 1 Disabled at power up; Note 2 Base +[0:7] Serial Port Com 2 Disabled at power up; Note 2 Base +[0:3] all modes Base +[4:7] for EPP Base +[400:403] for ECP Base1 +[0:7] Base2 +[6]

Parallel Port Disabled at power up; Note 2

IDE Disabled at power up; Note 2

HOST PROCESSOR INTERFACE

The host processor communicates with the FDC37C669 through a series of read/write registers. The port addresses for these registers are shown in Table 1. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide except the IDE data register at port 1F0H which is 16 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA.

up; Note 2

Note 1: Configuration registers can only be modified in configuration mode, refer to the

configuration register description for more information. Access to status registers A and B of the floppy disk is disabled in configuration mode.

Note 2: The base addresses must be set in the configuration registers before accessing the logical

devices.

FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection.

The FDC37C669 is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.

Table 2 - Status, Data and Control Registers

BASE I/O

ADDRESS

+0 +1 +2 +3 +4 +4 +5 +6 +7 +7

R R/W R/W

R/W

Status Register A Status Register B Digital Output Register Tape Drive Register Main Status Register Data Rate Select Register Data (FIFO) Reserved Digital Input Register Configuration Control Register

FLOPPY DISK CONTROLLER INTERNAL REGISTERS

The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the FDC description assumes the Base I/O Address is 3F0.

SRA SRB DOR

TSR MSR DSR

FIFO

DIR

CCR

For information on the floppy disk on Parallel Port pins, refer to Configuration Register CR4 and Parallel Port Floppy Disk Controller description.

STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state of the FINTR pin and several disk interface pins,

PS/2 Mode

7 6 5 4 3 2 1 0

INT

nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR

PENDING

RESET

0 N/A 0 N/A 0 N/A N/A 0

COND.

in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.

BIT 0 DIRECTION

Active high status indicating the direction of head movement. A logic "1" indicating inward direction a logic "0" outward.

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicating that the disk is write protected.

BIT 2 nINDEX

Active low status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0.

BIT 4 nTRACK 0

Active low status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the STEP output disk interface output pin.

BIT 6 nDRV2

Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

PS/2 Model 30 Mode

PENDING

RESET

COND.

7 6 5 4 3 2 1 0

INT

0 0 0 N/A 1 N/A N/A 1

DRQ STEP

F/F

TRK0 nHDSEL INDX WP nDIR

BIT 0 nDIRECTION

Active low status indicating the direction of head movement. A logic "0" indicating inward direction a logic "1" outward.

BIT 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic "1" indicating that the disk is write protected.

BIT 2 INDEX

Active high status of the INDEX disk interface input.

BIT 3 nHEAD SELECT

Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0.

BIT 4 TRACK 0

Active high status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset.

BIT 6 DMA REQUEST

Active high status of the DRQ output pin.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

STATUS REGISTER B (SRB)

Address F1 READ ONLY

This register is read-only and monitors the state of several disk interface pins, in PS/2 and Model

PS/2 Mode

7 6 5 4 3 2 1 0

RESET

1 1 DRIVE

SEL0

1 1 0 0 0 0 0 0

WDATA

TOGGLE

COND.

30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1.

RDATA

TOGGLE

WGATE MOT

EN1

MOT

EN0

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset, it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

PS/2 Model 30 Mode

nDRV2 nDS1 nDS0 WDATA

RESET

COND.

7 6 5 4 3 2 1 0

F/F

RDATA

F/F

WGATE

F/F

nDS3 nDS2

N/A 1 1 0 0 0 1 1

BIT 0 nDRIVE SELECT 2

Active low status of the DS2 disk interface output.

BIT 1 nDRIVE SELECT 3

Active low status of the DS3 disk interface output.

BIT 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA

Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register.

BIT 4 WRITE DATA

Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface output.

BIT 7 nDRV2

Active low status of the DRV2 disk interface input.

DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It also

7 6 5 4 3 2 1 0

MOT

EN3

RESET

MOT

EN2

MOT

EN1

0 0 0 0 0 0 0 0

COND.

contains the enable for the DMA logic and contains a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.

MOT

EN0

DMAEN nRESET DRIVE

SEL1

DRIVE

SEL0

BIT 0 and 1 DRIVE SELECT

These two bit a are binary encoded for the four drive selects DS0-DS3, thereby allowing only one drive to be selected at one time.

BIT 2 nRESET

A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic "0" will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance state. This bit is a logic "0" after a reset and in these modes.

PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 6 MOTOR ENABLE 2

This bit controls the MTR2 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 7 MOTOR ENABLE 3

This bit controls the MTR3 disk interface output. A logic "1" in this bit causes the output to go active.

Table 3 - Drive Activation Values

DRIVE DOR VALUE

0 1 2 3

1CH 2DH

4EH 8FH

TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

This register is included for 82077 software

Table 4- Tape Select Bits

compatability. The robust digital data separator used in the FDC37C669 does not require its characteristics modified for tape support. The contents of this register are not used internal to the device. The TDR is unaffected by a software reset. Bits 2-7 are tri-stated when read in this mode.

TAPE SEL1 TAPE SEL2

0 0 1 1

0 1 0 1

DRIVE

SELECTED

None

1 2 3

Table 5 - Internal 4 Drive Decode - Normal

DRIVE SELECT OUTPUTS

DIGITAL OUTPUT REGISTER

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS3 nDS2 nDS1 nDS0 nMTR3 nMTR2 nMTR1 nMTR0

X X X 1 0 0 1 1 1 0 nBIT 7 nBIT 6 nBIT 5 nBIT 4 X X 1 X 0 1 1 1 0 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4 X 1 X X 1 0 1 0 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4 1 X X X 1 1 0 1 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4 0 0 0 0 X X 1 1 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Table 6 - Internal 4 Drive Decode - Drives 0 and 1 Swapped

DRIVE SELECT OUTPUTS

DIGITAL OUTPUT REGISTER

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS3 nDS2 nDS1 nDS0 nMTR3 nMTR2 nMTR1 nMTR0

X X X 1 0 0 1 1 0 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5 X X 1 X 0 1 1 1 1 0 nBIT 7 nBIT 6 nBIT 4 nBIT 5 X 1 X X 1 0 1 0 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5 1 X X X 1 1 0 1 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5 0 0 0 0 X X 1 1 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Table 7 - External 2 to 4 Drive Decode - Normal

DRIVE SELECT

DIGITAL OUTPUT REGISTER

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 0 0 1 0 X X 1 X 0 1 0 1 1 0 X 1 X X 1 0 1 0 1 0

1 X X X 1 1 1 1 1 0 X X X 0 0 0 0 0 1 1 X X 0 X 0 1 0 1 1 1 X 0 X X 1 0 1 0 1 1

0 X X X 1 1 1 1 1 1

OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Table 8 - External 2 to 4 Drive Decode - Drives 0 and 1 Swapped

DRIVE SELECT

DIGITAL OUTPUT REGISTER

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 0 1 1 0 X X 1 X 0 1 0 0 1 0 X 1 X X 1 0 1 0 1 0

1 X X X 1 1 1 1 1 0 X X X 0 0 0 0 1 1 1 X X 0 X 0 1 0 0 1 1 X 0 X X 1 0 1 0 1 1

0 X X X 1 1 1 1 1 1

OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Normal Floppy Mode

Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance.

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state tape sel1 tape sel0

Enhanced Floppy Mode 2 (OS2)

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive tape sel1 tape sel0

For this mode, DRATE0 and DRATE1 pins are inputs, and these inputs are gated into bits 6 and 7 of the 3F3 register. These two bits are not affected by a hard or soft reset.

BIT 7 Reserved BIT 6 Reserved BITS 5 and 4 Drive Type ID - These Bits reflect

two of the bits of configuration register 6.

Table 9 - Drive Type ID

Digital Output Register Register 3F3 - Drive Type ID

Bit 1 Bit 0 Bit 5 Bit 4

0 0 CR6 - Bit 1 CR6 - Bit 0 0 1 CR6 - Bit 3 CR6 - Bit 2 1 0 CR6 - Bit 5 CR6 - Bit 4 1 1 CR6 - Bit 7 CR6 - Bit 6

Which two bits depends on the last drive selected in the Digital Output Register (3F2). (See Table 11)

BITS 3 and 2 Floppy Boot Drive - These bits reflect the value of configuration register 7 bits 1, 0. Bit 3 = CR7 Bit DB1. Bit 2 = CR7 Bit DB0.

Bits 1 and 0 - Tape Drive Select (READ/WRITE). Same as in Normal and Enhanced Floppy Mode. 1.

DATA RATE SELECT REGISTER (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and

7 6 5 4 3 2 1 0

S/W

RESET

POWER

0 PRE-

DOWN

0 0 0 0 0 0 1 0

COND.

Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 kbps.

COMP2

PRE-

COMP1

PRE-

COMP0

DRATE

SEL1

DRATE

SEL0

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 13 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset.

BIT 2 through 4 PRECOMPENSATION SELECT

These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 12 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER

A logic "1" written to this bit will put the floppy controller into Manual Low Power mode. The

floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register.

BIT 7 SOFTWARE RESET

This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.

Table 10 - Precompensation Delays

PRECOMP

432 PRECOMPENSATION DELAY

111 001 010 011 100 101 110 000

0.00 ns-DISABLED

41.67 ns

83.34 ns

125.00 ns

166.67 ns

208.33 ns

250.00 ns

Default (See Table 14)

Table 11 - Data Rates

DRIVE RATE DATA RATE DATA RATE DENSEL (1) DRATE (2)

DRT1 DRT0 SEL1 SEL0 MFM FM IDENT=1 IDENT=0 1 2

0 0 1 1 1Meg --- 1 0 1 1 0 0 0 0 500 250 1 0 0 0 0 0 0 1 300 150 0 1 0 1 0 0 1 0 250 125 0 1 1 0

0 1 1 1 1Meg --- 1 0 1 1 0 1 0 0 500 250 1 0 0 0 0 1 0 1 500 250 0 1 0 1 0 1 1 0 250 125 0 1 1 0

1 0 1 1 1Meg --- 1 0 1 1 1 0 0 0 500 250 1 0 0 0 1 0 0 1 2Meg --- 0 1 0 1 1 0 1 0 250 125 0 1 1 0

Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format

01 = 3-Mode Drive 10 = 2 Meg Tape

Note 1: This is for DENSEL in normal mode. Note 2: This is for DRATE0, DRATE1 when Drive Opt are 00.

Table 12 - Default Precompensation Delays

PRECOMPENSATION

DATA RATE

2 Mbps

1 Mbps 500 Kbps 300 Kbps 250 Kbps

*The 2 Mbps data rate is only available if VCC = 5V.

DELAYS

125 ns

41.67 ns 125 ns 125 ns 125 ns

MAIN STATUS REGISTER

Address 3F4 READ ONLY

The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any

7 6 5 4 3 2 1 0

RQM DIO NON

DMA

CMD

BUSY

time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. NO delay is required when reading the MSR after a data transfer.

DRV3 BUSY

DRV2 BUSY

DRV1 BUSY

DRV0 BUSY

BIT 0 - 3 DRV x BUSY

These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates.

BIT 4 COMMAND BUSY

This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte.

BIT 5 NON-DMA

This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a command. This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes.

BIT 6 DIO

Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.

BIT 7 RQM

Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.

DATA REGISTER (FIFO)

Address 3F5 READ/WRITE

All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register.

Data transfers are governed by the RQM and DIO bits in the Main Status Register.

The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 15 gives several examples of the delays with a

Table 13- FIFO Service Delay

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

1 x 4 µs - 1.5 µs = 2.5 µs 2 x 4 µs - 1.5 µs = 6.5 µs 8 x 4 µs - 1.5 µs = 30.5 µs 15 x 4 µs - 1.5 µs = 58.5 µs

FIFO. The data is based upon the following formula:

Threshold # x 1

DATA RATE

At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred.

An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.

MAXIMUM DELAY TO SERVICING

AT 2 Mbps* DATA RATE

-1.5 µs = DELAY

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING

AT 1 Mbps DATA RATE

1 x 8 µs - 1.5 µs = 6.5 µs 2 x 8 µs - 1.5 µs = 14.5 µs 8 x 8 µs - 1.5 µs = 62.5 µs 15 x 8 µs - 1.5 µs = 118.5 µs

MAXIMUM DELAY TO SERVICING

AT 500 Kbps DATA RATE

1 x 16 µs - 1.5 µs = 14.5 µs 2 x 16 µs - 1.5 µs = 30.5 µs 8 x 16 µs - 1.5 µs = 126.5 µs 15 x 16 µs - 1.5 µs = 238.5 µs

*The 2 Mbps data rate is only available if VCC = 5V.

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Standard Microsystems Corporation FDC37C669 Datasheet

Specifications and Main Features

Frequently Asked Questions

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