Standard Microsystems Corporation FDC37B72X Datasheet

FDC37B72x

128 Pin Enhanced Super I/O Controller with

ACPI Support

FEATURES

• 5 Volt Operation

• PC98/99 and ACPI 1.0 Compliant

• Battery Back-up for Wake-Events

• ISA Host Interface

• ISA Plug-and-Play Compatible Register

Set

- 12 IRQ Options

- 15 Serial IRQ Options

- 16 Bit Address Qualification

- Four DMA Options

- 12mA AT Bus Drivers

• BIOS Buffer

• 20 GPI/O Pins

• 32 kHz Standby Clock Output

• Soft Power Management

• ACPI/PME Support

• SCI/SMI Support

- Watchdog timer

- Power Button Override Event

- Either Edge Triggered Interrupts

• Intelligent Auto Power Management

- Shadowed Write-only Registers

- Programmable Wake-up Event Interface

• 8042 Keyboard Controller

- 2K Program ROM

- 256 Bytes Data RAM

- Asynchronous Access to Two Data

Registers and One Status Register

- Supports Interrupt and Polling Access

- 8 Bit Timer/Counter

- Port 92 Support

- Fast Gate A20 and Hardware Keyboard

Reset

• 2.88MB Super I/O Floppy Disk Controller

- Relocatable to 480 Different Addresses

- Licensed CMOS 765B Floppy Disk

Controller

- Advanced Digital Data Separator

- SMSC's Proprietary 82077AA

Compatible Core

- Sophisticated Power Control Circuitry

(PCC) Including Multiple Powerdown Modes for Reduced Power Consumption

- Supports Two Floppy Drives Directly

- Software Write Protect

- FDC on Parallel Port

- Low Power CMOS Design

- Supports Vertical Recording Format

- 16 Byte Data FIFO

- 100% IBM® Compatibility

- Detects All Overrun and Underrun

Conditions

- 24mA Drivers and Schmitt Trigger Inputs

• Enhanced FDC Digital Data Separator

- Low Cost Implementation

- No Filter Components Required

- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,

250 Kbps Data Rates

- Programmable Precompensation

Modes

• Serial Ports

- Relocatable to 480 Different

Addresses

- Two High Speed NS16C550A Compatible UARTs with Send/Receive 16 Byte FIFOs

- Programmable Baud Rate

Generator

- Modem Control Circuitry Including

230K and 460K Baud

- IrDA 1.0, HP-SIR, ASK-IR Support

- Ring Wake Filter

• Multi-Mode Parallel Port with ChiProtect



- Relocatable to 480 Different Addresses

- Standard Mode

- IBM PC/XT®, PC/AT®, and PS/2 Compatible Bidirectional ParallelPort



- Enhanced Mode

- Enhanced Parallel Port (EPP) Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

- High Speed Mode

- Microsoft and Hewlett Packard Extended Capabilities Port (ECP) Compatible (IEEE 1284 Compliant)

- Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On

- 14 mA Output Drivers

• 128 Pin QFP Package

TABLE OF CONTENTS

FEATURES....................................................................................................................................... 1

GENERAL DESCRIPTION................................................................................................................. 5

DESCRIPTION OF PIN FUNCTIONS ................................................................................................ 7

BUFFER TYPE DESCRIPTIONS........................................................................................ 10

GENERAL PURPOSE I/O PINS....................................................................................................... 11

REFERENCE DOCUMENTS ........................................................................................................... 12

FUNCTIONAL DESCRIPTION.........................................................................................................14

SUPER I/O REGISTERS.................................................................................................... 14

HOST PROCESSOR INTERFACE..................................................................................... 14

FLOPPY DISK CONTROLLER ........................................................................................................ 15

FDC INTERNAL REGISTERS.......................................................................................................... 15

COMMAND SET/DESCRIPTIONS................................................................................................... 38

INSTRUCTION SET ........................................................................................................................ 41

DATA TRANSFER COMMANDS........................................................................................ 53

CONTROL COMMANDS.................................................................................................... 62

SERIAL PORT (UART).................................................................................................................... 69

INFRARED INTERFACE.................................................................................................... 85

PARALLEL PORT............................................................................................................................ 86

IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES ....................................... 88

EXTENDED CAPABILITIES PARALLEL PORT................................................................................ 94

OPERATION.....................................................................................................................102

PARALLEL PORT FLOPPY DISK CONTROLLER...........................................................................107

POWER MANAGEMENT ................................................................................................................109

UART POWER MANAGEMENT........................................................................................113

PARALLEL PORT.............................................................................................................113

INTERNAL PWRGOOD....................................................................................................113

32.768 KHZ STANDBY CLOCK OUTPUT...........................................................................114

SERIAL IRQ...................................................................................................................................115

BIOS BUFFER................................................................................................................................120

GENERAL PURPOSE I/O...............................................................................................................121

DESCRIPTION .................................................................................................................121

RUN STATE GPIO DATA REGISTER ACCESS................................................................122

GPIO CONFIGURATION..................................................................................................123

WATCH DOG TIMER.....................................................................................................................126

8042 KEYBOARD CONTROLLER DESCRIPTION..........................................................................128

SOFT POWER MANAGEMENT......................................................................................................136

BUTTON OVERRIDE FEATURE.......................................................................................139

ACPI/PME/SMI FEATURES ............................................................................................................141

ACPI FEATURES..............................................................................................................141

PME SUPPORT................................................................................................................143

ACPI, PME AND SMI REGISTERS ...................................................................................143

EITHER EDGE TRIGGERED INTERRUPTS...................................................................................155

CONFIGURATION..........................................................................................................................158

SYSTEM ELEMENTS .......................................................................................................158

CONFIGURATION SEQUENCE......................................................................................... 10

CONFIGURATION REGISTERS .......................................................................................161

OPERATIONAL DESCRIPTION......................................................................................................204

MAXIMUM GUARANTEED RATINGS*..............................................................................204

DC ELECTRICAL CHARACTERISTICS.............................................................................204

AC TIMING.......................................................................................................................209

CAPACITIVE LOADING....................................................................................................209

ECP PARALLEL PORT TIMING........................................................................................234

80 Arkay Dr. Hauppauge, NY 11788 (516) 435-6000 FAX: (516) 273-3123

GENERAL DESCRIPTION

The FDC37B72x incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP support, on-chip 12 mA AT bus drivers, and two floppy direct drive support, soft power management and SMI support and Intelligent Power Management including PME and SCI/ACPI support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both onchip UARTs are compatible with the NS16C550. The parallel port is compatible with IBM PC/AT architecture, as well as EPP and ECP. The FDC37B72x incorporates sophisticated power control circuitry (PCC) which includes support for keyboard, mouse, modem ring, power button support and other wake-up events. The PCC supports multiple low power down modes.

The FDC37B72x provides features for compliance with the “Advanced Configuration and Power Interface Specification” (ACPI).

These features include support of both legacy and ACPI power management models through the selection of SMI or SCI. It implements a power button override event (4 second button hold to turn off the system) and either edge triggered interrupts.

The FDC37B72x provides support for the ISA Plug-and-Play Standard (Version 1.0a) and provides for the recommended functionality to support Windows '95/’98 and PC98/PC99. Through internal configuration registers, each of the FDC37B72x's logical device's I/O address, DMA channel and IRQ channel may be programmed. There are 480 I/O address location options, 12 IRQ pin options or Serial IRQ option, and four DMA channel options for each logical device.

The FDC37B72x Floppy Disk Controller and data separator do not require any external filter components and are therefore easy to use, offer lower system cost and reduced board area. The FDC is software and register compatible with SMSC's proprietary 82077AA core.

IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business Machines Corporation SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems Corporation

PD7

12345678910111213141516171819202122232425262728293031333435363738

DRVDEN0

DRVDEN1/GP52/IRQ8/nSMI

nMTR0

nDS1/GP17

nDS0

nMTR1/GP16

VSS

nDIR

nSTEP

nWDATA

nWGATE

nHDSEL

nINDEX

nTRK0

nWRTPRT

nRDATA

nDSKCHG

CLK32OUT

nPOWERON

BUTTON_IN

nPME/SCI/IRQ9

CLOCKI

SA9

SA0

SA1

SA2

SA4

SA6

SA7

SA8

SA3

SA5

SA10

SA11

SA12

SA13

SA14

SA15

PD0

nSLCTIN

nINIT

VCC

nROMOE/IRQ12/GP54/EETI

nROMCS/IRQ11/GP53/EETI

RD7/IRQ10/GP67

RD6/IRQ8/GP66

RD5/IRQ7/GP65

RD4/IRQ6/GP64/P17

RD3/IRQ5/GP63/WDT

RD2/IRQ4/GP62/nRING

RD1/IRQ3/GP61/LED

RD0/IRQ1/GP60/nSMI

KCLK

KDAT

VTR

XTAL2

AVSS

XTAL1

GP15/IRTX2

VBAT

GP14/IRRX2

GP13/LED

GP12/WDT/P17/EETI

GP11/nRING/EETI

GP10/nSMI

A20M

KBDRST

VSS

MCLK

MDAT

PD6

PD5

PD4

PD3

PD2

PD1

102

101

100

VSS

SLCT

BUSY nACK

nERROR

nALF

nSTROBE

RXD1

TXD1

nDSR1

nRTS1/SYSOP

nCTS1 nDTR1

nRI1

nDCD1

nRI2 VCC

nDCD2

RXD2/IRRX

TXD2/IRTX

nDSR2

nRTS2

nCTS2

nDTR2

103 104 105 106

107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

FDC37B72x

128 Pin QFP

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39

IOCHRDY TC VCC DRQ3 nDACK3 DRQ2 nDACK2 DRQ1 nDACK1 DRQ0 nDACK0 RESET_DRV SD7 SD6 SD5 SD4 VSS SD3 SD2 SD1 SD0 AEN nIOW nIOR SER_IRQ/IRQ15 PCI_CLK/IRQ14/GP50

FIGURE 1 - FDC37B72x PIN CONFIGURATION

DESCRIPTION OF PIN FUNCTIONS

TABLE 1 - DESCRIPTION OF PIN FUNCTIONS

No./QFP NAME TOTAL SYMBOL BUFFER TYPE

PROCESSOR/HOST INTERFACE (40)

44-47,

49-52 23-38 16-bit System Address Bus 16 SA[0:15] I

43 Address Enable 1 AEN I 64 I/O Channel Ready 1 IOCHRDY OD12 53 ISA Reset Drive 1 RESET_DRV IS 40 Serial IRQ/IRQ15 1 SER_IRQ IO12 39 PCI Clock/IRQ14/GP50 1 PCI_CLK IO12 55 DMA Request 0 1 DRQ0 O12 57 DMA Request 1 1 DRQ1 O12 59 DMA Request 2 1 DRQ2 O12 54 DMA Acknowledge 0 1 nDACK0 I 56 DMA Acknowledge 1 1 nDACK1 I 58 DMA Acknowledge 2 1 nDACK2 I 61 DMA Request 3 1 DRQ3 O12 60 DMA Acknowledge 3 1 nDACK3 I 63 Terminal Count 1 TC I 41 I/O Read 1 nIOR I 42 I/O Write 1 nIOW I

22 14.318MHz Clock Input 1 CLOCKI ICLK 66 32.768kHz Crystal Input 1 XTAL1 ICLK 68 32.768kHz Crystal Driver 1 XTAL2 OCLK2 18 32.768kHz Clock Out 1 CLK32OUT O8

62, 93,

121

7, 48,

74, 104

67 Analog Ground 1 AVSS 69 Trickle Supply Voltage 1 VTR 65 Battery Voltage 1 VBAT

19 Power On 1 nPOWERON OD24 20 Button In 1 BUTTON_IN I 21 Power Management Event/SCI/IRQ9 1 nPME O12

16 Read Disk Data 1 nRDATA IS 11 Write Gate 1 nWGATE O24

System Data Bus 8 SD[0:7] IO12

CLOCKS (4)

POWER PINS (10)

+5V Supply Voltage 3 VCC Digital Ground 4 VSS

POWER MANAGEMENT (3)

FDD INTERFACE (16)

No./QFP NAME TOTAL SYMBOL BUFFER TYPE

10 Write Disk Data 1 nWDATA O24 12 Head Select 1 nHDSEL O24

8 Step Direction 1 nDIR O24 9 Step Pulse 1 nSTEP O24

17 Disk Change 1 nDSKCHG IS

5 Drive Select 0 1 nDS0 O24 6 Drive Select 1/GP17 1 nDS1 IO24 3 Motor On 0 1 nMTR0 O24

4 Motor On 1/GP16 1 nMTR1 IO24 15 Write Protected 1 nWRTPRT IS 14 Track 0 1 nTRKO IS 13 Index Pulse Input 1 nINDEX IS

1 Drive Density Select 0 1 DRVDEN0 O24

2 Drive Density Select 1/GP52/IRQ8/nSMI 1 DRVDEN1 IO24

GENERAL PURPOSE I/O (6)

77 General Purpose 10/nSMI 1 GP10 IO12 78 General Purpose 11/nRING/EETI (Note 4) 1 GP11 IO4 79 General Purpose 12/WDT/P17/P12/EETI

1 GP12 IO4

(Note 4) 80 General Purpose 13/LED Driver 1 GP13 IO24 81 General Purpose 14/Infrared Rx 1 GP14 IO4 82 General Purpose 15/Infrared Tx (Note 3) 1 GP15 IO24

BIOS INTERFACE (10)

83 ROM Bus 0/IRQ1/GP60/nSMI 1 RD0 IO12 84 ROM Bus 1/IRQ3/GP61/LED 1 RD1 IO24 85 ROM Bus 2/IRQ4/GP62/nRING 1 RD2 IO12 86 ROM Bus 3/IRQ5/GP63/WDT 1 RD3 IO12 87 ROM Bus 4/IRQ6/GP64/P17/P12 1 RD4 IO12 88 ROM Bus 5/IRQ7/GP65 1 RD5 IO12 89 ROM Bus 6/IRQ8/GP66 1 RD6 IO12 90 ROM Bus 7/IRQ10/GP67 1 RD7 IO12 91 nROMCS/IRQ11/GP53/EETI (Note 4) 1 nROMCS IO12 92 nROMOE/IRQ12/GP54/EETI (Note 4) 1 nROMOE IO12

SERIAL PORT 1 INTERFACE (8)

112 Receive Serial Data 1 1 RXD1 I 113 Transmit Serial Data 1 1 TXD1 O4 115 Request to Send 1 1 nRTS1/

IO4

SYSOP 116 Clear to Send 1 1 nCTS1 I 117 Data Terminal Ready 1 1 nDTR1 O4 114 Data Set Ready 1 1 nDSR1 I 119 Data Carrier Detect 1 1 nDCD1 I 118 Ring Indicator 1 1 nRI1 I

No./QFP NAME TOTAL SYMBOL BUFFER TYPE

SERIAL PORT 2 INTERFACE (8)

123 Receive Serial Data 2/Infrared Rx 1 RXD2/IRRX I 124 Transmit Serial Data 2/Infrared Tx (Note 3) 1 TXD2/IRTX O24 126 Request to Send 2 1 nRTS2 O4 127 Clear to Send 2 1 nCTS2 I 128 Data Terminal Ready 1 nDTR2 O4 125 Data Set Ready 2 1 nDSR2 I 122 Data Carrier Detect 2 1 nDCD2 I 120 Ring Indicator 2 1 nRI2 I

PARALLEL PORT INTERFACE (17)

96-103 Parallel Port Data Bus 8 PD[0:7] IOP14

95 Printer Select 1 nSLCTIN OP14

94 Initiate Output 1 nINIT OP14 110 Auto Line Feed 1 nALF OP14 111 Strobe Signal 1 nSTROBE OP14 107 Busy Signal 1 BUSY I 108 Acknowledge Handshake 1 nACK I 106 Paper End 1 PE I 105 Printer Selected 1 SLCT I 109 Error at Printer 1 nERROR I

KEYBOARD/MOUSE INTERFACE (6)

70 Keyboard Data 1 KDAT IOD16

71 Keyboard Clock 1 KCLK IOD16

72 Mouse Data 1 MDAT IOD16

73 Mouse Clock 1 MCLK IOD16

75 Keyboard Reset 1 KBDRST

(Note 2)

76 Gate A20 1 A20M O4

Note 1: The “n” as the first letter of a signal name indicates an “Active Low” signal. Note 2: KBDRST is active low. Note 3: This pin defaults to an output and low. When configured as IRTX (or IRTX2), this pin is low

when the IR block is not transmitting.

Note 4: EETI is the Either Edge Triggered Interrupt Input function.

BUFFER TYPE DESCRIPTIONS

SYMBOL DESCRIPTION

I Input, TTL compatible. IS Input with Schmitt trigger. ICLK Clock Input. OCLK2 Clock Output, 2mA sink, 2mA source. IO4 Input/Output, 4mA sink, 2mA source. IOP4 Input/Output, 4mA sink, 2mA source. Backdrive Protected. O4 Output, 4mA sink, 2mA source. O8 Output, 8mA sink, 4mA source. IO12 Input/Output, 12mA sink, 6mA source. O12 Output, 12mA sink, 6mA source. OP12 Output, 12mA sink, 6mA source. Backdrive Protected. OD12 Output, Open Drain, 12 mA sink. IOP14 Input/Output, 14mA sink, 14mA source. Backdrive Protected. OD14 Output, Open Drain, 14mA sink. OP14 Output, 14mA sink, 14mA source. Backdrive Protected. IOD16 Input/Output, Open Drain, 16mA sink O24 Output, 24mA sink, 12mA source. OD24 Output, Open Drain, 24mA sink.

TABLE 2 - BUFFER TYPES

GENERAL PURPOSE I/O PINS

TABLE 3 - GENERAL PURPOSE I/O PIN FUNCTIONS

PIN NO.

QFP

77 GPIO nSMI - - IOP4/(OP12/ 78 GPIO nRING EETI

79 GPIO WDT P17/P12 80 GPIO LED - - IOP4/O24 GP1 GP13 81 GPIO IRRX2 - - IOP4/I GP1 GP14 82 GPIO IRTX2 - - IOP4/O24 GP1 GP15

4 nMTR1 GPIO - - (O24/OD24)/ 6 nDS1 GPIO - - (O24/OD24)/

39 PCI_CLK IRQ14 GPIO - CLKIN/(O12/

2 DRVDEN1 GPIO IRQ8 nSMI (O24/OD24)

91 nROMCS 92 nROMOE 83 RD0

84 RD1

85 RD2 86 RD3

87 RD4

88 RD5 89 RD6 90 RD7

Note 1: Either Edge Triggered Interrupt Inputs. Note 2: At power-up, RD0-7, nROMCS and nROMOE function as the XD Bus. To use RD0-7 for

Note 3: These pins cannot be programmed as open drain pins in their original function. Note 4: The function of P17 or P12 is selected via the P17/P12 select bit in the Ring Filter Select

DEFAULT

FUNCTION

ALTERNATE FUNCTION 1

ALTERNATE FUNCTION 2

ALTERNATE FUNCTION 3

BUFFER

TYPE

INDEX

REG. GPIO

GP1 GP10

- IOP4/I/I GP1 GP11

EETI

OD12)

IOP4/O4/IO4/I GP1 GP12

GP1 GP16

IOP4

GP1 GP17

IOP4

GP5 GP50

OD12)/IOP4

GP5 GP52 /IOP4/ (OP12/OD12)/

IRQ11 GPIO EETI

IRQ12 GPIO EETI

2,3

IRQ1 GPIO nSMI IO12/(O12/

(OP12/OD12) IO12/(O12/ OD12)/IOP4/I IO12/(O12/ OD12)/IOP4/I

GP5 GP53

GP5 GP54

GP6 GP60 OD12)/IOP4/

2,3

IRQ3 GPIO LED IO12/(O12/

(OP12/OD12)

GP6 GP61 OD12)/IOP4/

2,3

IRQ4 GPIO nRING IO12/(O12/ IRQ5 GPIO WDT IO12/(O12/

O24

GP6 GP62 OD12)/IOP4/I

GP6 GP63 OD12)/IOP4/

2,3

IRQ6 GPIO P17/P12

O4 IO12/(O12/

GP6 GP64 OD12)/IOP4/

2,3

IRQ7 GPIO - IO12/(O12/ IRQ8 GPIO - IO12/(OP12/ IRQ10 GPIO - IO12/(O12/

IO4

GP6 GP65 OD12)/IOP4

GP6 GP66 OD12)/IOP4

GP6 GP67 OD12)/IOP4

alternate functions, nROMCS must stay high until those pins are finished being programmed.

Note 5: Buffer types per function are separated by a forward slash “/”. Multiple buffer types per

function are separated by a forward slash “/” and enclosed in parentheses; e.g., IRQ outputs can be open drain or push-pull and are shown as “(O12/OD12)”.

REFERENCE DOCUMENTS

§ IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.

§ Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook.

§ PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997.

nPowerOn

Button_In

SER_IRQ

PCI_CLK

nIOR

nIOW

SA[0:15]

SD[O:7]

DRQ[0:3]

nDACK[0:3]

IRQ[1,3-12,14]

RESET_DRV

IOCHRDY

nPME/SCI

SOFT

POWER

MANAGEMENT

POWER

MANAGEMENT

SERIAL

IRQ

AEN

HOST

CPU

INTERFACE

PME/ ACPI

nSMI*

nSMI

ADDRESS BUS

SMSC

PROPRIETARY

82077

COMPATIBLE

VERTICAL

FLOPPYDISK

CONTROLLER

CORE

DATA BUS

CONFIGURATION

REGISTERS

CONTROL BUS

WDATA

WCLOCK

RCLOCK

RDATA

BIOS

BUFFER

nROMOE* nROMCS* RD[0:7]*

DIGITAL

DATA SEPARATOR WITH WRITE

PRECOM-

PENSATION

MULTI-MODE

PARALLEL PORT/FDC

MUX

GENERAL PURPOSE

I/O

16C550

COMPATIBLE

SERIAL PORT 1

16C550

COMPATIBLE

SERIAL

PORT 2 WITH

INFRARED

8042

PD0-7

BUSY, SLCT, PE, nERROR, nACK nSTB, nSLCTIN,

nINIT, nALF

GP1[0:7]* GP5[0,2:4]* GP6[0:7]*

TXD1

RXD1

nDSR1, nDCD1, nRI1, nDTR1

nCTS1, nRTS1

IRTX IRRX

TXD2(IRTX)

RXD2(IRRX)

nDSR2, nDCD2, nRI2, nDTR2

nCTS2, nRTS2

KCLK KDATA

MCLK MDATA P20, P21 P17/P12*

VCC

XTAL1 XTAL2

CLK32OUT

CLOCKI (14.318)

DENSEL

nINDEX nTRK0

nDSKCHG

nWRPRT

VBAT

VTR

VSS

nWGATE

nDIR

nSTEP

nHDSEL

nDS0,1

nMTR0,1

DRVDEN0 DRVDEN1

nWDATA nRDATA

*Multi-Function I/O Pin - Optional

CLOCK

GEN

FIGURE 2 - FDC37B72x BLOCK DIAGRAM

FUNCTIONAL DESCRIPTION

SUPER I/O REGISTERS

The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports can be moved via the configuration registers. Some addresses are used to access more than one register.

TABLE 4 - SUPER I/O BLOCK ADDRESSES

ADDRESS BLOCK NAME

Base+(0-5) and +(7) Floppy Disk 0

Parallel Port Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) Base+(0-7) Serial Port Com 1 4 Base+(0-7) Serial Port Com 2 5 IR Support 60, 64 KYBD 7 Base + (0-17h) ACPI, PME, SMI A Base + (0-1) Configuration

Note 1: Refer to the configuration register descriptions for setting the base address

SPP

EPP

ECP

ECP+EPP+SPP

HOST PROCESSOR INTERFACE

The host processor communicates with the FDC37B72x through a series of read/write registers. The port addresses for these registers are shown in Table 1. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA.

LOGICAL

DEVICE NOTES

FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection.

TABLE 5 - STATUS, DATA AND CONTROL REGISTERS

(Shown with base addresses of 3F0 and 370)

PRIMARY

ADDRESS

3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7

SECONDARY

ADDRESS R/W REGISTER

370 371 372 373 374 374 375 376 377 377

The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.

FDC INTERNAL REGISTERS

The Floppy Disk Controller contains eight internal registers that facilitate the interfacing between the host microprocessor and the disk drive. TABLE 5 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected.

Status Register A (SRA)

Status Register B (SRB) R/W R/W

R/W

Digital Output Register (DOR)

Tape Drive Register (TSR)

Main Status Register (MSR)

Data Rate Select Register (DSR)

Data (FIFO)

Reserved

Digital Input Register (DIR)

Configuration Control Register (CCR)

STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state of the FINTR pin and several disk interface pins in PS/2 and Model 30 modes. The SRA can

7 6 5 4 3 2 1 0

INT

nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR

PENDING

RESET

0 1 0 N/A 0 N/A N/A 0

COND.

be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.

PS/2 Mode

BIT 0 DIRECTION

Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction.

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. (See also Force Write Protect Function)

BIT 2 nINDEX

Active low status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0.

BIT 4 nTRACK 0

Active low status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the STEP output disk interface output pin.

BIT 6 nDRV2

Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed. Note: This function is not

supported in this chip. (Always 1, indicating 1 drive)

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

PS/2 Model 30 Mode

RESET COND.

7 6 5 4 3 2 1 0

INT

PENDING

0 0 0 N/A 1 N/A N/A 1

DRQ STEP

F/F

TRK0 nHDSEL INDX WP nDIR

BIT 0 nDIRECTION

Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction.

BIT 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. (See also Force Write Protect Function)

BIT 2 INDEX

Active high status of the INDEX disk interface input.

BIT 3 nHEAD SELECT

Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0.

BIT 4 TRACK 0

Active high status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset.

BIT 6 DMA REQUEST

Active high status of the DRQ output pin.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

STATUS REGISTER B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any

7 6 5 4 3 2 1 0

RESET

1 1 DRIVE

SEL0

1 1 0 0 0 0 0 0

WDATA

TOGGLE

COND.

time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1.

PS/2 Mode

RDATA

TOGGLE

WGATE MOT

EN1

MOT

EN0

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

PS/2 Model 30 Mode

nDRV2 nDS1 nDS0 WDATA

RESET COND.

7 6 5 4 3 2 1 0

F/F

RDATA

F/F

WGATE

F/F

nDS3 nDS2

N/A 1 1 0 0 0 1 1

BIT 0 nDRIVE SELECT 2

The DS2 disk interface is not supported. (Always 1)

BIT 1 nDRIVE SELECT 3

The DS3 disk interface is not supported. (Always 1)

BIT 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA

Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register.

BIT 4 WRITE DATA

Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface output.

BIT 7 nDRV2

Active low status of the DRV2 disk interface input, this is not supported. (Always 1).

DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It also

7 6 5 4 3 2 1 0

MOT

EN3

RESET

MOT

EN2

MOT

EN1

0 0 0 0 0 0 0 0

COND.

contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.

MOT

EN0

DMAEN nRESETDRIVE

SEL1

DRIVE

SEL0

BIT 0 and 1 DRIVE SELECT

These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time.

BIT 2 nRESET

A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic "0" will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance state. This bit is a logic "0" after a reset and in these modes.

TABLE 6 - DRIVE ACTIVATION VALUES

PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 6 MOTOR ENABLE 2

The MTR2 disk interface output is not. (Always

BIT 7 MOTOR ENABLE 3

The MTR3 disk interface output is not. (Always

DRIVE DOR VALUE

0 1

1CH 2DH

TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

TABLE 7 - TAPE SELECT BITS

TAPE SEL1

(TDR.1)

0 0 1 1

The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine

TAPE SEL0

(TDR.0)

0 1 0 1

the tape drive number. TABLE 7 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset.

DRIVE

SELECTED

None

1 2 3

TABLE 8 - INTERNAL 2 DRIVE DECODE - NORMAL

DIGITAL OUTPUT REGISTER

DRIVE SELECT

OUTPUTS (ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 1 0 nBIT 5 nBIT 4 X X 1 X 0 1 0 1 nBIT 5 nBIT 4 X 1 X X 1 0 1 1 nBIT 5 nBIT 4

1 X X X 1 1 1 1 nBIT 5 nBIT 4 0 0 0 0 X X 1 1 nBIT 5 nBIT 4

TABLE 9 - INTERNAL 2 DRIVE DECODE - DRIVES 0 AND 1 SWAPPED

DIGITAL OUTPUT REGISTER

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 0 1 nBIT 4 nBIT 5 X X 1 X 0 1 1 0 nBIT 4 nBIT 5 X 1 X X 1 0 1 1 nBIT 4 nBIT 5

1 X X X 1 1 1 1 nBIT 4 nBIT 5 0 0 0 0 X X 1 1 nBIT 4 nBIT 5

Normal Floppy Mode

Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance.

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state tape sel1 tape sel0

Enhanced Floppy Mode 2 (OS2)

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive tape sel1 tape sel0

TABLE 10 - DRIVE TYPE ID

DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID

Bit 1 Bit 0 Bit 5 Bit 4

0 0 L0-CRF2 - B1 L0-CRF2 - B0 0 1 L0-CRF2 - B3 L0-CRF2 - B2 1 0 L0-CRF2 - B5 L0-CRF2 - B4 1 1 L0-CRF2 - B7 L0-CRF2 - B6

Note:L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.

DATA RATE SELECT REGISTER (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and

7 6 5 4 3 2 1 0

S/W

RESET

POWER

0 PRE-

DOWN

0 0 0 0 0 0 1 0

COND.

Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps.

COMP2

PRE-

COMP1

PRE-

COMP0

DRATE

SEL1

DRATE

SEL0

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BIT 2 through 4 PRECOMPENSATION SELECT

These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 10 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER

A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data mode after a software reset or access to the Data Register or Main Status Register.

BIT 7 SOFTWARE RESET

This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.

Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, LD8:CRC2[7:0]. separator circuits will be turned off. The controller will come out of manual low power.

TABLE 11 - PRECOMPENSATION DELAYS

PRECOMP

432

PRECOMPENSATION

DELAY (nsec)

<2Mbps 2Mbps 111 001 010 011 100 101 110 000

0.00

41.67

83.34

125.00

166.67

208.33

250.00

Default

20.8

41.7

62.5

83.3

104.2 125

Default

Default: See Table 11

TABLE 12 - DATA RATES

DRIVE RATE DATA RATE DATA RATE

DRATE(1)

DENSEL

DRT1 DRT0 SEL1 SEL0 MFM FM 1 0

0 0 1 1 1Meg --- 1 1 1 0 0 0 0 500 250 1 0 0 0 0 0 1 300 150 0 0 1 0 0 1 0 250 125 0 1 0

0 1 1 1 1Meg --- 1 1 1 0 1 0 0 500 250 1 0 0 0 1 0 1 500 250 0 0 1 0 1 1 0 250 125 0 1 0

1 0 1 1 1Meg --- 1 1 1 1 0 0 0 500 250 1 0 0 1 0 0 1 2Meg --- 0 0 1 1 0 1 0 250 125 0 1 0

Drive Rate Table (Recommended)00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format

01 = 3-Mode Drive 10 = 2 Meg Tape

Note 1:The DRATE and DENSEL values are mapped onto the DRVDEN pins.

TABLE 13 - DRVDEN MAPPING

DT1 DT0 DRVDEN1 (1) DRVDEN0 (1) DRIVE TYPE

0 0 DRATE0 DENSEL 4/2/1 MB 3.5"

2/1 MB 5.25" FDDS

2/1.6/1 MB 3.5" (3-MODE) 1 0 DRATE0 DRATE1 0 1 DRATE0 nDENSEL PS/2 1 1 DRATE1 DRATE0

TABLE 14 - DEFAULT PRECOMPENSATION DELAYS

PRECOMPENSATION

DATA RATE

2 Mbps

1 Mbps 500 Kbps 300 Kbps 250 Kbps

DELAYS

20.8 ns

41.67 ns 125 ns 125 ns 125 ns

MAIN STATUS REGISTER

Address 3F4 READ ONLY

The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any

7 6 5 4 3 2 1 0

RQM DIO

NON DMA

CMD

BUSY Reserved Reserved

time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer.

DRV1 BUSY

DRV0 BUSY

BIT 0 - 1 DRV x BUSY

These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates.

BIT 4 COMMAND BUSY

This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte.

BIT 5 NON-DMA

This mode is selected in the SPECIFY command and will be set to a 1 during the execution phase of a command. This is for polled data transfers and helps differentiate between the data transfer phase and the reading of result bytes.

BIT 6 DIO

Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.

BIT 7 RQM

Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.

DATA REGISTER (FIFO)

Address 3F5 READ/WRITE

All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register.

Data transfers are governed by the RQM and DIO bits in the Main Status Register.

The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 14 gives several examples of the delays with a FIFO. The data is based upon the following formula:

Threshold # x 1

DATA RATE

x 8 - 1.5 s = DELAY

At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred.

An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by

TABLE 15 - FIFO SERVICE DELAY

FIFO THRESHOLD

MAXIMUM DELAY TO SERVICING

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

1 x 4 µs - 1.5 µs = 2.5 µs 2 x 4 µs - 1.5 µs = 6.5 µs 8 x 4 µs - 1.5 µs = 30.5 µs 15 x 4 µs - 1.5 µs = 58.5 µs

generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.

AT 2 Mbps DATA RATE

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING

AT 1 Mbps DATA RATE

1 x 8 µs - 1.5 µs = 6.5 µs 2 x 8 µs - 1.5 µs = 14.5 µs 8 x 8 µs - 1.5 µs = 62.5 µs 15 x 8 µs - 1.5 µs = 118.5 µs

MAXIMUM DELAY TO SERVICING

AT 500 Kbps DATA RATE

1 x 16 µs - 1.5 µs = 14.5 µs 2 x 16 µs - 1.5 µs = 30.5 µs 8 x 16 µs - 1.5 µs = 126.5 µs 15 x 16 µs - 1.5 µs = 238.5 µs

DIGITAL INPUT REGISTER (DIR)

Address 3F7 READ ONLY

This register is read-only in all modes.

PC-AT Mode

7 6 5 4 3 2 1 0

DSK

CHG

RESET

N/A N/A N/A N/A N/A N/A N/A N/A

COND.

BIT 0 - 6 UNDEFINED

The data bus outputs D0 - 6 will remain in a high impedance state during a read of this register.

7 6 5 4 3 2 1 0

DSK

1 1 1 1 DRATE

CHG

RESET

N/A N/A N/A N/A N/A N/A N/A 1

COND.

BIT 0 nHIGH DENS

This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected.

BITS 1 - 2 DATA RATE SELECT

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]).

PS/2 Mode

SEL1

DRATE

SEL0

nHIGH

nDENS

BITS 3 - 6 UNDEFINED

Always read as a logic "1"

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]).

Model 30 Mode

RESET

COND.

7 6 5 4 3 2 1 0

DSK

CHG

N/A 0 0 0 0 0 1 0

0 0 0 DMAEN NOPREC DRATE

SEL1

DRATE

SEL0

BITS 0 - 1 DATA RATE SELECT

BIT 2 NOPREC

This bit reflects the value of NOPREC bit set in the CCR register.

BIT 3 DMAEN

This bit reflects the value of DMAEN bit set in the DOR register bit 3.

BITS 4 - 6 UNDEFINED

Always read as a logic "0"

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]).

CONFIGURATION CONTROL REGISTER (CCR)

Address 3F7 WRITE ONLY

PC/AT and PS/2 Modes

7 6 5 4 3 2 1 0

RESET

N/A N/A N/A N/A N/A N/A 1 0

COND.

DRATE

SEL1

DRATE

SEL0

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 11 for the appropriate values.

7 6 5 4 3 2 1 0

RESET

N/A N/A N/A N/A N/A N/A 1 0

COND.

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 11 for the appropriate values.

BIT 2 NO PRECOMPENSATION

This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset.

BIT 2 - 7 RESERVED

Should be set to a logical "0"

PS/2 Model 30 Mode

NOPREC DRATE

SEL1

DRATE

SEL0

BIT 3 - 7 RESERVED

Should be set to a logical "0" Table 12 shows the state of the DENSEL pin.

The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets.

STATUS REGISTER ENCODING

During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed.

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