Sony E01X23A41, ICX423AL User Manual

ICX423AL

Diagonal 11mm (Type 2/3) CCD Image Sensor for CCIR B/W Video Cameras

	Description	20 pin DIP (Ceramic)
	The ICX423AL is an interline CCD solid-state image
	sensor suitable for CCIR B/W video cameras with a
	diagonal 11mm (Type 2/3) system. Compared with the
	current product ICX083AL, basic characteristics such
	as sensitivity and smear are improved drastically and
	high saturation characteristics are realized.
	This chip features a field period readout system and
	an electronic shutter with variable charge-storage
	time. This chip is compatible with the pins of the
	ICX083AL and has the same drive conditions.			Pin 1
	Features			2
	• High sensitivity (+3.0dB compared with the ICX083AL)	V
	• Low smear (–10.0dB compared with the ICX083AL)
	• High saturation signal (+2.0dB compared with the ICX083AL)
	• High resolution and Low dark current	3		12
	• Excellent antiblooming characteristics		H	40
		Pin 11
	• Continuous variable-speed shutter

	Optical black position
Device Structure	(Top View)
• Interline CCD image sensor
• Optical size:	Diagonal 11mm (Type 2/3)
• Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels
• Total number of pixels:	795 (H) × 596 (V) approx. 470K pixels
• Chip size:	10.25mm (H) × 8.5mm (V)
• Unit cell size:	11.6µm (H) × 11.2µm (V)
• Optical black:	Horizontal (H) direction: Front 3 pixels, rear 40 pixels
	Vertical (V) direction: Front 12 pixels, rear 2 pixels
• Number of dummy bits:	Horizontal 22
	Vertical 1 (even fields only)
• Substrate material:	Silicon

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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E01X23A41

ICX423AL

USE RESTRICTION NOTICE (December 1, 2003 ver.)

This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify this Notice which will be available to you in the latest specifications book for the Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor. You should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice when you consider using the Products.

Use Restrictions

•The Products are intended for incorporation into such general electronic equipment as office products, communication products, measurement products, and home electronics products in accordance with the terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time.

•You should not use the Products for critical applications which may pose a lifeor injurythreatening risk or are highly likely to cause significant property damage in the event of failure of the Products. You should consult your Sony sales representative beforehand when you consider using the Products for such critical applications. In addition, you should not use the Products in weapon or military equipment.

•Sony disclaims and does not assume any liability and damages arising out of misuse, improper use, modification, use of the Products for the above-mentioned critical applications, weapon and military equipment, or any deviation from the requirements set forth in this specifications book.

Design for Safety

•Sony is making continuous efforts to further improve the quality and reliability of the Products; however, failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to ensure the safe design of your products such as component redundancy, anti-conflagration features, and features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social damage as a result of such failure.

Export Control

•If the Products are controlled items under the export control laws or regulations of various countries, approval may be required for the export of the Products under the said laws or regulations. You should be responsible for compliance with the said laws or regulations.

No License Implied

•The technical information shown in this specifications book is for your reference purposes only. The availability of this specifications book shall not be construed as giving any indication that Sony and its licensors will license any intellectual property rights in such information by any implication or otherwise. Sony will not assume responsibility for any problems in connection with your use of such information or for any infringement of third-party rights due to the same. It is therefore your sole legal and financial responsibility to resolve any such problems and infringement.

Governing Law

•This Notice shall be governed by and construed in accordance with the laws of Japan, without reference to principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating to this Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the court of first instance.

Other Applicable Terms and Conditions

•The terms and conditions in the Sony additional specifications, which will be made available to you when you order the Products, shall also be applicable to your use of the Products as well as to this specifications book. You should review those terms and conditions when you consider purchasing and/or using the Products.

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ICX423AL

Block Diagram and Pin Configuration

(Top view)

VL	7
GND	9
VDD	10
VOUT	11
VGG	12
VSS	13

Output Unit

Vertical Register

GND 14

Horizontal Register

15	16	17	18	19
RD	RG	VL Hφ1		Hφ2
			Note)	: Photo sensor

	1	Vφ4
	2	Vφ3
	3	Vφ2
	4	SUB
Note)	5	GND
	6	Vφ1

20

HIS

Pin Description

Pin No.	Symbol	Description	Pin No.	Symbol	Description
1	Vφ4	Vertical register transfer clock	11	VOUT	Signal output
2	Vφ3	Vertical register transfer clock	12	VGG	Output amplifier gate bias
3	Vφ2	Vertical register transfer clock	13	VSS	Output amplifier source
4	SUB	Substrate (overflow drain)	14	GND	GND
5	GND	GND	15	RD	Reset drain
6	Vφ1	Vertical register transfer clock	16	RG	Reset gate clock
7	VL	Protective transistor bias	17	VL	Protective transistor bias
8	NC		18	Hφ1	Horizontal register transfer clock
9	GND	GND	19	Hφ2	Horizontal register transfer clock
10	VDD	Output amplifier drain power	20	HIS	Horizontal register input source bias

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				ICX423AL
Absolute Maximum Ratings
	Item	Ratings	Unit	Remarks
Substrate voltage SUB – GND		–0.3 to +55	V
Supply voltage	HIS, VDD, RD, VOUT, VSS – GND	–0.3 to +20	V
	HIS, VDD, RD, VOUT, VSS – SUB	–55 to +10	V
Vertical clock input	Vertical clock input pins – GND	–15 to +20	V
voltage	Vertical clock input pins – SUB	to +10	V
Voltage difference between vertical clock input pins		to +15	V	1
Voltage difference between horizontal clock input pins		to +17	V
Hφ1, Hφ2 – Vφ4		–17 to +17	V
Hφ1, Hφ2, RG, VGG – GND		–10 to +15	V
Hφ1, Hφ2, RG, VGG – SUB		–55 to +10	V
VL – SUB		–65 to +0.3	V
Vφ1, Vφ3, HIS, VDD, RD, VOUT – VL		–0.3 to +30	V
RG – VL		–0.3 to +24	V
Vφ2, Vφ4, VGG, VSS, Hφ1, Hφ2 – VL		–0.3 to +20	V
Storage temperature		–30 to +80	°C
Operating temperature		–10 to +60	°C

1 27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Bias Conditions

Item	Symbol	Min.	Typ.	Max.	Unit	Remarks
Output amplifier drain voltage	VDD	14.7	15.0	15.3	V
Reset drain voltage	VRD	14.7	15.0	15.3	V	VRD = VDD
Output amplifier gate voltage	VGG	3.8	4.2	4.6	V
Output amplifier source	VSS	Ground with 750Ω resistor				±5%
Substrate voltage adjustment range	VSUB	9		19	V	2
Substrate voltage adjustment precision	∆VSUB	–3		+3	%
Reset gate clock voltage adjustment range	VRGL	0		3.0	V	2
Reset gate clock voltage adjustment precision	∆VRGL	–3		+3	%
Protective transistor bias	VL	–11	–10.5	–10	V	3
Horizontal register input source bias	VHIS	14.7	15.0	15.3	V	VHIS = VDD

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ICX423AL

DC Characteristics

Item	Symbol	Min.	Typ.	Max.	Unit	Remarks
Output amplifier drain current	IDD		6		mA
Input current	IIN1			1	µA	4
Input current	IIN2			10	µA	5

2 Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value

The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. The adjustment precision is ±3%.

VSUB code — one character indication
VRGL code — one character indication									↑	↑
							VRGL code			VSUB code
"Code" and optimal setting correspond to each other as follows.
VRGL code	1	2	3	4	5	6	7
Optimal setting	0	0.5	1.0	1.5	2.0	2.5	3.0
VSUB code	D	E	f	G	h	J	K	L	m	N	P	Q	R	S	T	U	V	W	X	Y	Z
Optimal setting	9.0	9.5	10.0	10.5	11.0	11.5	12.0	12.5	13.0	13.5	14.0	14.5	15.0	15.5	16.0	16.5	17.0	17.5	18.0	18.5	19.0

3

4

5

<Example> "5K" → VRGL = 2.0V

VSUB = 12.0V

This must no exceed the VVL voltage of the vertical clock waveform.

1)Current to each pin when 20V is applied to VDD, RD, VOUT, VSS, HIS and SUB pins, while pins that are not tested are grounded.

2)Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are not tested are grounded. However, 20V is applied to SUB pin.

3)Current to each pin when 15V is applied sequentially to Hφ1, Hφ2, RG and VGG pins, while pins that are not tested are grounded. However, 15V is applied to SUB pin.

4)Current to VL pin when 30V is applied to Vφ1, Vφ3, HIS, VDD, RD and VOUT pins or when, 24V is applied to RG pin or when, 20V is applied to Vφ2, Vφ4, VGG, VSS, Hφ1 and Hφ2 pins, while VL pin is grounded.

However, GND and SUB pins are left open.

Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.

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ICX423AL

Clock Voltage Conditions

Item	Symbol	Min.	Typ.	Max.	Unit	Waveform	Remarks
						diagram
Readout clock voltage	VVT	14.5	15.0	15.5	V	1
	VVH1, VVH2,	–0.6		0	V	2	VVH = (VVH1 + VVH2)/2
	VVH3, VVH4
	VVL1, VVL2,		–9.6		V	2	VVL = (VVL3 + VVL4)/2
	VVL3, VVL4
	VφV	8.9			V	2	VφV = VVHn – VVLn (n = 1 to 4)
Vertical transfer clock	| VVH1 – VVH2 |			0.2	V	2
	VVH3 – VVH	–0.5		0	V	2
voltage
	VVH4 – VVH	–0.5		0	V	2
	VVHH			0.8	V	2	High-level coupling
	VVHL			1.0	V	2	High-level coupling
	VVLH			0.8	V	2	Low-level coupling
	VVLL			0.8	V	2	Low-level coupling
Horizontal transfer	VφH	6.0		8.0	V	3
clock voltage	VHL	–3.5		–3.0	V	3
Reset gata clock	VφRG	6.0		13.0	V	3	1
voltage	VRGL	0		3.0	V	3
Substrate clock voltage	VφSUB	27.0		32.0	V	4

1 The reset gate clock voltage need not be adjusted when the reset gate clock is driven when the specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image sensor has not significance.

Item	Symbol	Min.	Typ.	Max.	Unit	Waveform	Remarks
						diagram
Reset gate clock	VRGL	–0.2	0	0.2	V	3
voltage
	VφRG	8.5	9.0	9.5	V	3

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