SMC Networks ARM PL241, ARM AHB SRAM-NOR User Manual

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PrimeCell® AHB SRAM/NOR

Memory Controller (PL241)

Revision: r0p1

Technical Reference Manual

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

PrimeCell AHB SRAM/NOR Memory Controller (PL241)

Technical Reference Manual

Copyright © 2006 ARM Limited. All rights reserved.

Release Information

The following changes have been made to this book.

 

 

 

 

Change History

 

 

 

 

Date

Issue

Confidentiality

Change

 

 

 

 

 

17

March 2006

A

Non-Confidential

First release for r0p0.

 

 

 

 

 

20

December 2006

B

Non-Confidential

Updated for r0p1.

 

 

 

 

 

Proprietary Notice

Words and logos marked with ® orare registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential.The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Web Address

http://www.arm.com

ii

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

Contents

PrimeCell AHB SRAM/NOR Memory Controller

(PL241) Technical Reference Manual

Preface

 

 

About this manual ..........................................................................................

x

 

 

Feedback .....................................................................................................

xiv

Chapter 1

Introduction

 

 

1.1

About the AHB MC ......................................................................................

1-2

 

1.2

Supported devices ......................................................................................

1-5

Chapter 2

Functional Overview

 

 

2.1

Functional description .................................................................................

2-2

 

2.2

SMC ............................................................................................................

2-4

 

2.3

Functional operation ...................................................................................

2-7

 

2.4

SMC functional operation ..........................................................................

2-15

Chapter 3

Programmer’s Model

 

 

3.1

About the programmer’s model ...................................................................

3-2

 

3.2

Register summary .......................................................................................

3-3

 

3.3

Register descriptions ..................................................................................

3-6

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

iii

Contents

Chapter 4

Programmer’s Model for Test

 

 

4.1

SMC integration test registers ....................................................................

4-2

Chapter 5

Device Driver Requirements

 

 

5.1

Memory initialization ...................................................................................

5-2

Appendix A

Signal Descriptions

 

 

A.1

About the signals list ...................................................................................

A-2

 

A.2

Clocks and resets .......................................................................................

A-3

 

A.3

AHB signals ................................................................................................

A-4

 

A.4

SMC memory interface signals ...................................................................

A-5

 

A.5

SMC miscellaneous signals ........................................................................

A-6

 

A.6

Low-power interface ...................................................................................

A-7

 

A.7

Configuration signal ....................................................................................

A-8

 

A.8

Scan chains ................................................................................................

A-9

Glossary

iv

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

List of Tables

PrimeCell AHB SRAM/NOR Memory Controller

(PL241) Technical Reference Manual

 

Change History .............................................................................................................

ii

Table 2-1

Static memory clocking options ...............................................................................

2-12

Table 2-2

Asynchronous read opmode chip register settings .................................................

2-28

Table 2-3

Asynchronous read SRAM cycles register settings .................................................

2-28

Table 2-4

Asynchronous read in multiplexed-mode opmode chip register settings ................

2-29

Table 2-5

Asynchronous read in multiplexed-mode SRAM cycles register settings ...............

2-29

Table 2-6

Asynchronous write opmode chip register settings .................................................

2-30

Table 2-7

Asynchronous write SRAM cycles register settings ................................................

2-30

Table 2-8

Asynchronous write in multiplexed-mode opmode chip register settings ................

2-31

Table 2-9

Asynchronous write in multiplexed-mode SRAM cycles register settings ...............

2-31

Table 2-10

Page read opmode chip register settings ................................................................

2-31

Table 2-11

Page read SRAM cycles register settings ...............................................................

2-31

Table 2-12

Synchronous burst read opmode chip register settings ..........................................

2-32

Table 2-13

Synchronous burst read SRAM cycles register settings .........................................

2-32

Table 2-14

Synchronous burst read in multiplexed-mode opmode chip register settings .........

2-34

Table 2-15

Synchronous burst read in multiplexed-mode read SRAM cycles register settings

2-34

Table 2-16

Synchronous burst write opmode chip register settings ..........................................

2-35

Table 2-17

Synchronous burst write SRAM cycles register settings .........................................

2-35

Table 2-18

Synchronous burst write in multiplexed-mode opmode chip register settings .........

2-36

Table 2-19

Synchronous burst write in multiplexed-mode SRAM cycles register settings ........

2-36

Table 2-20

Synchronous read and asynchronous write opmode chip register settings ............

2-37

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

v

List of Tables

Table 2-21

Synchronous read and asynchronous write opmode chip register settings ............

2-37

Table 3-1

Register summary .....................................................................................................

3-4

Table 3-2

smc_memc_status Register bit assignments ...........................................................

3-6

Table 3-3

smc_memif_cfg Register bit assignments ................................................................

3-7

Table 3-4

smc_memc_cfg_set Register bit assignments .........................................................

3-9

Table 3-5

smc_memc_cfg_clr Register bit assignments ..........................................................

3-9

Table 3-6

smc_direct_cmd Register bit assignments .............................................................

3-10

Table 3-7

smc_set_cycles Register bit assignments ..............................................................

3-11

Table 3-8

smc_set_opmode Register bit assignments ...........................................................

3-13

Table 3-9

smc_refresh_period_0 Register bit assignments ....................................................

3-15

Table 3-10

smc_sram_cycles Register bit assignments ...........................................................

3-16

Table 3-11

smc_opmode Register bit assignments ..................................................................

3-17

Table 3-12

smc_user_status Register bit assignments ............................................................

3-18

Table 3-13

smc_user_config Register bit assignments ............................................................

3-19

Table 3-14

smc_periph_id Register bit assignments ................................................................

3-19

Table 3-15

smc_periph_id_0 Register bit assignments ............................................................

3-20

Table 3-16

smc_periph_id_1 Register bit assignments ............................................................

3-21

Table 3-17

smc_periph_id_2 Register bit assignments ............................................................

3-21

Table 3-18

smc_periph_id_3 Register bit assignments ............................................................

3-21

Table 3-19

smc_pcell_id Register bit assignments ...................................................................

3-22

Table 3-20

smc_pcell_id_0 Register bit assignments ...............................................................

3-23

Table 3-21

smc_pcell_id_1 Register bit assignments ...............................................................

3-23

Table 3-22

smc_pcell_id_2 Register bit assignments ...............................................................

3-24

Table 3-23

smc_pcell_id_3 Register bit assignments ...............................................................

3-24

Table 4-1

SMC test register summary ......................................................................................

4-2

Table 4-2

smc_int_cfg Register bit assignments ......................................................................

4-3

Table 4-3

smc_int_inputs Register bit assignments .................................................................

4-3

Table 4-4

smc_int_outputs Register bit assignments ...............................................................

4-4

Table A-1

Clocks and resets .....................................................................................................

A-3

Table A-2

AHB signals ..............................................................................................................

A-4

Table A-3

SMC memory interface signals .................................................................................

A-5

Table A-4

SMC miscellaneous signals ......................................................................................

A-6

Table A-5

Low-power interface signals .....................................................................................

A-7

Table A-6

Configuration signal ..................................................................................................

A-8

Table A-7

Scan chain signals ....................................................................................................

A-9

vi

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

List of Figures

PrimeCell AHB SRAM/NOR Memory Controller

(PL241) Technical Reference Manual

 

Key to timing diagram conventions .............................................................................

xii

Figure 1-1

AHB MC (PL241) configuration .................................................................................

1-2

Figure 2-1

AHB MC (PL241) configuration .................................................................................

2-2

Figure 2-2

AHB MC (PL241) clock domains ...............................................................................

2-3

Figure 2-3

SMC block diagram ...................................................................................................

2-4

Figure 2-4

SMC SRAM pad interface external connections .......................................................

2-6

Figure 2-5

Big-endian implementation ......................................................................................

2-10

Figure 2-6

AHBC memory map ................................................................................................

2-11

Figure 2-7

Request to enter low-power mode ..........................................................................

2-13

Figure 2-8

AHB domain denying a low-power request .............................................................

2-13

Figure 2-9

Accepting requests ..................................................................................................

2-14

Figure 2-10

SMC aclk domain FSM ...........................................................................................

2-15

Figure 2-11

Chip configuration registers ....................................................................................

2-23

Figure 2-12

Device pin mechanism ............................................................................................

2-25

Figure 2-13

Software mechanism ...............................................................................................

2-26

Figure 2-14

Asynchronous read .................................................................................................

2-29

Figure 2-15

Asynchronous read in multiplexed-mode ................................................................

2-29

Figure 2-16

Asynchronous write .................................................................................................

2-30

Figure 2-17

Asynchronous write in multiplexed-mode ................................................................

2-31

Figure 2-18

Page read ................................................................................................................

2-32

Figure 2-19

Synchronous burst read ..........................................................................................

2-33

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

vii

List of Figures

Figure 2-20

Synchronous burst read in multiplexed-mode ........................................................

2-34

Figure 2-21

Synchronous burst write .........................................................................................

2-35

Figure 2-22

Synchronous burst write in multiplexed-mode ........................................................

2-36

Figure 2-23

Synchronous read and asynchronous write ............................................................

2-38

Figure 3-1

SMC register map .....................................................................................................

3-2

Figure 3-2

SMC configuration register map ...............................................................................

3-3

Figure 3-3

SMC chip configuration register map ........................................................................

3-3

Figure 3-4

SMC user configuration register map .......................................................................

3-4

Figure 3-5

SMC peripheral and PrimeCell identification configuration register map ..................

3-4

Figure 3-6

smc_memc_status Register bit assignments ...........................................................

3-6

Figure 3-7

smc_memif_cfg Register bit assignments ................................................................

3-7

Figure 3-8

smc_memc_cfg_set Register bit assignments .........................................................

3-8

Figure 3-9

smc_memc_cfg_clr Register bit assignments ..........................................................

3-9

Figure 3-10

smc_direct_cmd Register bit assignments .............................................................

3-10

Figure 3-11

smc_set_cycles Register bit assignments ..............................................................

3-11

Figure 3-12

smc_set_opmode Register bit assignments ...........................................................

3-12

Figure 3-13

smc_refresh_period_0 Register bit assignments ....................................................

3-15

Figure 3-14

smc_sram_cycles Register bit assignments ...........................................................

3-15

Figure 3-15

smc_opmode Register bit assignments ..................................................................

3-16

Figure 3-16

smc_user_status Register bit assignments ............................................................

3-18

Figure 3-17

smc_user_config Register bit assignments ............................................................

3-19

Figure 3-18

smc_periph_id Register bit assignments ................................................................

3-20

Figure 3-19

smc_pcell_id Register bit assignments ...................................................................

3-22

Figure 4-1

SMC integration test register map ............................................................................

4-2

Figure 4-2

smc_int_cfg Register bit assignments ......................................................................

4-2

Figure 4-3

smc_int_inputs Register bit assignments .................................................................

4-3

Figure 4-4

smc_int_outputs Register bit assignments ...............................................................

4-4

Figure 5-1

SMC and memory initialization sheet 1 of 3 .............................................................

5-3

Figure 5-2

SMC and memory initialization sheet 2 of 3 .............................................................

5-4

Figure 5-3

SMC and memory initialization sheet 3 of 3 .............................................................

5-5

Figure A-1

AHB MC PL241 grouping of signals .........................................................................

A-2

viii

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

Preface

This preface introduces the PrimeCell AHB SRAM/NOR Memory Controller (MC) (PL241) Technical Reference Manual. It contains the following sections:

About this manual on page x

Feedback on page xiv.

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

ix

Preface

About this manual

This is the Technical Reference Manual(TRM) for the PrimeCell AHB SRAM/NOR Memory Controller.

Product revision status

The rnpn identifier indicates the revision status of the product described in this manual,

where:

 

rn

Identifies the major revision of the product.

pn

Identifies the minor revision or modification status of the product.

Intended audience

This manual is written for system designers, system integrators, and verification engineers who are designing a System-on-Chip (SoC) device that uses the AHB MC. The manual describes the external functionality of the AHB MC.

Using this manual

This manual is organized into the following chapters:

Chapter 1 Introduction

Read this chapter for a high-levelview of the AHB MC and a description of its features.

Chapter 2 Functional Overview

Read this chapter for a description of the major components of the AHB

MC and how they operate.

Chapter 3 Programmer’s Model

Read this chapter for a description of the AHB MC registers.

Chapter 4 Programmer’s Model for Test

Read this chapter for a description of the additional logic for integration testing.

Chapter 5 Device Driver Requirements

Read this chapter for a description of device driver requirements for the

Static Memory Controller (SMC).

x

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B