2
Data Sheet
512 Kbit / 1 Mbit Multi-Purpose Flash
SST39SF512 / SST39SF010
©2001 Silicon Storage Technology, Inc. S71149-03-000 4/01 394
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. T he data bus is latche d on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST3 9SF512/0 10 is contr olled
by CE# and OE#, both have to be low for the syste m to
obtain data from the outputs. CE# is used for device selec-
tion. When CE# is high, the chip is desele cted and only
standby power is consumed. OE# is the output control and
is used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for fur ther details
(Figure 4).
Byte-Program Operation
The SST39SF512/010 are programmed on a byte-by-byte
basis. The Program ope ration c on si sts of thr e e s te ps. Th e
first step i s t he th ree- b yte -loa d se quen ce for Soft w are D ata
Protection. The second step is to load byte ad dress and
byte data. During the Byte-Program operation, the
addresses are latched on the falling edge of ei ther CE# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either CE# or WE#, whichever occurs first. The
third step is the internal Program operatio n which is initi-
ated after the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once initiated, will
be completed, within 30 µs. Se e Figures 5 and 6 for WE#
and CE# controlled Program operation timing diagrams
and Figure 15 for flowchar ts. During the Program ope ra-
tion, the only valid reads are Dat a# Polling and Toggle Bit.
During the inte rnal Program operat ion, the host is fre e to
perform additional tasks. Any commands written during the
internal Program operation will be ignored.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device o n a sector-by-sector basis. The sector architecture
is based on unifor m sector size of 4 KByte. The S ector-
Erase operation is initiated by executing a six-byte-com-
mand load sequence for Software Data Protection with
Sector-Erase com mand (30 H) and sec tor addre ss (SA) in
the last bus cycle. The sector address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H)
is latched on the rising ed ge of the six th WE# pulse. Th e
internal Era se operation begin s after t he sixth W E# puls e.
The end of Erase can be deter mined using either Data #
Polling or Toggle Bit methods. See Figure 9 for timing
waveforms. Any commands written during the Sector-
Erase operation will be ignored.
Chip-Erase Operation
The SST39SF512/010 provide Chip-Erase operation,
which allows the user to erase the en tire memor y array to
the “1s” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The Erase operation begins wi th the ri s ing
edge of the sixth WE# or CE#, whichever occurs first. Dur-
ing the Erase operation, the only valid read is Toggle Bit or
Data# Polling. See Table 4 for the command sequence,
Figure 10 for timing diagram, and Figure 18 for the flow-
chart. Any commands written during the Chip-Erase opera-
tion will be ignored.
Write Operation Status Detection
The SST39SF512/010 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the syste m Write cycle time. The soft-
ware detection includes two status bits: Data# Polling
(DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection
mode is enabled after the r ising edge of WE#, which ini-
tiates the program or erase cycle.
The actual comple tion of the nonvolatile wr ite is as ynchr o-
nous with the system ; therefore, either a Data# Polling or
Tog gle Bit read may be simultaneous with th e completio n
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
7
or DQ
6
. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If bo th reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Data# Polling (DQ
7
)
When the SST39S F512/010 are in the inter nal Program
operation, any attemp t to read DQ
7
will produce the com-
plement of the true da ta. Once the Program operation is
completed, D Q
7
will produce true data. The device is then
ready for the next operation. Dur ing inter nal Erase ope ra-
tion, any attempt to read DQ
7
will produce a ‘0’. Once the
internal Erase operation is compl eted, DQ
7
will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program Operation. For sector or
Chip-Erase, the Data# Polling is valid after the r ising edge
of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling
timing diagram and Figure 16 for a flowchart.