Silicon Storage Technology Inc SST39SF020A-70-4I-UH, SST39SF020A-70-4I-PH, SST39SF020A-70-4I-NH, SST39SF020A-70-4C-WH, SST39SF020A-70-4C-UH Datasheet

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1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

FEATURES:

Organized as 128K x8 / 256K x8 / 512K x8

Single 5.0V Read and Write Operations

Superior Reliability

Endurance: 100,000 Cycles (typical)

Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 10 mA (typical)

Standby Current: 30 µA (typical)

Sector-Erase Capability

Uniform 4 KByte sectors

Fast Read Access Time:

45 and 70 ns

Latched Address and Data

Preliminary Specification

Fast Erase and Byte-Program:

Sector-Erase Time: 18 ms (typical)

Chip-Erase Time: 70 ms (typical)

Byte-Program Time: 14 µs (typical)

Chip Rewrite Time:

2 seconds (typical) for SST39SF010A

4 seconds (typical) for SST39SF020A

8 seconds (typical) for SST39SF040

Automatic Write Timing

Internal VPP Generation

End-of-Write Detection

Toggle Bit

Data# Polling

TTL I/O Compatibility

JEDEC Standard

Flash EEPROM Pinouts and command sets

Packages Available

32-pin PLCC

32-pin TSOP (8mm x 14mm)

32-pin PDIP

PRODUCT DESCRIPTION

The SST39SF010A/020A/040 are CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF010A/020A/040 devices write (Program or Erase) with a 5.0V power supply. The SST39SF010A/020A/040 devices conform to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST39SF010A/020A/040 devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST39SF010A/020A/040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a

function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST39SF010A/020A/040 are offered in 32-pin PLCC and 32-pin TSOP packages. A 600 mil, 32-pin PDIP is also available. See Figures 1, 2, and 3 for pinouts.

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE#

©2001 Silicon Storage Technology, Inc.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

S71147-02-000 5/01

398

MPF is a trademark of Silicon Storage Technology, Inc.

 

 

These specifications are subject to change without notice.

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Preliminary Specification

Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the SectorErase operation will be ignored.

Read

The Read operation of the SST39SF010A/020A/040 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram (Figure 4) for further details.

Byte-Program Operation

The SST39SF010A/020A/040 are programmed on a byte- by-byte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased.The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte-com- mand load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data#

Chip-Erase Operation

The SST39SF010A/020A/040 provide Chip-Erase operation, which allows the user to erase the entire memory array to the “1s” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the ChipErase operation will be ignored.

Write Operation Status Detection

The SST39SF010A/020A/040 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST39SF010A/020A/040 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sec-

©2001 Silicon Storage Technology, Inc.

S71147-02-000 5/01 398

2

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Preliminary Specification

toror Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sectoror ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart.

Data Protection

The SST39SF010A/020A/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39SF010A/020A/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six byte load sequence. The SST39SF010A/ 020A/040 devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC.

Product Identification

The product identification mode identifies the device as the SST39SF040, SST39SF010A, or SST39SF020A and manufacturer as SST. This mode may be accessed by software operations. Users may wish to use the software product identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 11 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart.

TABLE 1: PRODUCT IDENTIFICATION

 

Address

Data

 

 

 

Manufacturer’s ID

0000H

BFH

 

 

 

Device ID

 

 

SST39SF010A

0001H

B5H

SST39SF020A

0001H

B6H

SST39SF040

0001H

B7H

 

 

 

T1.2 398

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform and Figure 17 for a flowchart.

©2001 Silicon Storage Technology, Inc.

S71147-02-000 5/01 398

3

Silicon Storage Technology Inc SST39SF020A-70-4I-UH, SST39SF020A-70-4I-PH, SST39SF020A-70-4I-NH, SST39SF020A-70-4C-WH, SST39SF020A-70-4C-UH Datasheet

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Preliminary Specification

FUNCTIONAL BLOCK DIAGRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SuperFlash

 

 

 

 

 

 

 

 

 

 

X-Decoder

 

 

 

 

Memory Address

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Buffers & Latches

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y-Decoder

 

CE#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE#

 

 

 

Control Logic

 

 

 

 

I/O Buffers and Data Latches

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ7 - DQ0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

398 ILL B1.2

 

 

 

 

SST39SF040

A12

 

A15

 

A16

 

A18

V

 

WE#

A17

 

 

 

 

 

 

 

 

 

 

 

 

 

DD

 

 

 

 

 

 

 

 

 

SST39SF020A

A12

 

A15

 

A16

 

NC

V

 

WE#

A17

 

 

 

 

 

 

 

 

 

 

 

 

 

DD

 

 

 

 

 

 

 

 

 

SST39SF010A

A12

 

A15

 

A16

 

NC

V

 

WE#

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

DD

 

 

 

 

 

SST39SF040 SST39SF020A

SST39SF010A

 

4

3

2

1

 

32

31

30

 

 

 

 

 

 

 

 

A7

A7

A7

 

5

 

 

 

 

 

 

 

 

 

 

 

 

29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

A6

A6

A6

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

A5

A5

A5

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

A4

A4

A4

 

8

 

 

32-pin PLCC

A3

A3

A3

 

9

 

 

25

 

 

 

 

 

Top View

 

 

 

A2

A2

A2

 

10

 

 

 

 

 

 

 

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23

A1

A1

A1

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22

A0

A0

A0

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

DQ0

DQ0

DQ0

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SST39SF010A

 

14

15

16

17

18

19

 

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ1

 

DQ2

 

V

 

DQ3

DQ4

 

DQ5

DQ6

 

 

 

 

 

 

 

 

 

SS

 

 

 

 

 

 

 

 

 

SST39SF010A SST39SF020A SST39SF040

A14

A14

A14

A13

A13

A13

A8

A8

A8

A9

A9

A9

A11

A11

A11

OE#

OE#

OE#

A10

A10

A10

CE#

CE#

CE#

DQ7

DQ7

DQ7

398 ILL F02.3

SST39SF020A

DQ1

DQ2

V

DQ3

DQ4

DQ5

DQ6

 

 

 

SS

 

 

 

 

SST39SF040

DQ1

DQ2

V

DQ3

DQ4

DQ5

DQ6

 

 

 

SS

 

 

 

 

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC

©2001 Silicon Storage Technology, Inc.

S71147-02-000 5/01 398

4

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Preliminary Specification

SST39SF040

SST39SF020A

SST39SF010A

 

A11

A11

A11

 

 

1

 

A9

A9

A9

 

2

 

A8

A8

A8

 

3

 

A13

A13

A13

 

4

 

A14

A14

A14

 

5

Standard Pinout

A17

A17

NC

 

6

WE#

WE#

WE#

 

7

Top View

VDD

VDD

VDD

 

8

 

 

 

A18

NC

NC

 

9

Die Up

A16

A16

A16

 

 

10

A15

A15

A15

 

 

11

 

A12

A12

A12

 

 

12

 

A7

A7

A7

 

 

13

 

A6

A6

A6

 

 

14

 

A5

A5

A5

 

 

15

 

A4

A4

A4

 

 

16

 

 

 

 

 

 

 

 

 

 

 

SST39SF010A SST39SF020A SST39SF040

32

 

 

OE#

OE#

OE#

31

 

 

A10

A10

A10

30

 

 

CE#

CE#

CE#

29

 

 

DQ7

DQ7

DQ7

28

 

 

DQ6

DQ6

DQ6

27

 

 

DQ5

DQ5

DQ5

26

 

 

DQ4

DQ4

DQ4

25

 

 

DQ3

DQ3

DQ3

24

 

 

VSS

VSS

VSS

 

 

23

 

 

DQ2

DQ2

DQ2

22

 

 

DQ1

DQ1

DQ1

21

 

 

DQ0

DQ0

DQ0

20

 

 

A0

A0

A0

19

 

 

A1

A1

A1

18

 

 

A2

A2

A2

17

 

 

A3

A3

A3

 

 

 

 

 

 

389 ILL F01.1

FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)

SST39SF040

SST39SF020A

SST39SF010A

 

SST39SF010A

SST39SF020A

SST39SF040

A18

NC

NC

1

 

32

VDD

VDD

VDD

A16

A16

A16

2

 

31

WE#

WE#

WE#

A15

A15

A15

3

 

30

NC

A17

A17

A12

A12

A12

4

 

29

A14

A14

A14

A7

A7

A7

5

32-pin

28

A13

A13

A13

A6

A6

A6

6

27

A8

A8

A8

 

A5

A5

A5

7

PDIP

26

A9

A9

A9

A4

A4

A4

8

Top View

25

A11

A11

A11

A3

A3

A3

9

 

24

OE#

OE#

OE#

A2

A2

A2

10

 

23

A10

A10

A10

A1

A1

A1

11

 

22

CE#

CE#

CE#

A0

A0

A0

12

 

21

DQ7

DQ7

DQ7

DQ0

DQ0

DQ0

13

 

20

DQ6

DQ6

DQ6

DQ1

DQ1

DQ1

14

 

19

DQ5

DQ5

DQ5

DQ2

DQ2

DQ2

15

 

18

DQ4

DQ4

DQ4

VSS

VSS

VSS

16

 

17

DQ3

DQ3

DQ3

398 ILL F02a.2

FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP

©2001 Silicon Storage Technology, Inc.

S71147-02-000 5/01 398

5

 

 

 

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

 

 

 

SST39SF010A / SST39SF020A / SST39SF040

 

 

 

 

 

 

 

Preliminary Specification

TABLE

2: PIN DESCRIPTION

 

 

 

 

 

Symbol

 

Pin Name

Functions

 

 

 

 

AMS1-A0

 

Address Inputs

To provide memory addresses.

 

 

 

During Sector-Erase AMS-A12 address lines will select the sector.

DQ7-DQ0

 

Data Input/output

To output data during Read cycles and receive input data during Write cycles.

 

 

 

Data is internally latched during a Write cycle.

 

 

 

The outputs are in tri-state when OE# or CE# is high.

CE#

 

Chip Enable

To activate the device when CE# is low.

OE#

 

Output Enable

To gate the data output buffers.

WE#

 

Write Enable

To control the Write operations.

VDD

 

Power Supply

To provide 5.0V supply (±10%)

VSS

 

Ground

 

NC

 

No Connection

Unconnected pins.

 

 

 

 

 

 

 

T2.1 398

1.AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

TABLE 3: OPERATION MODES SELECTION

Mode

CE#

OE#

WE#

DQ

Address

 

 

 

 

 

 

Read

VIL

VIL

VIH

DOUT

AIN

Program

VIL

VIH

VIL

DIN

AIN

Erase

VIL

VIH

VIL

X1

Sector address,

 

 

 

 

 

XXH for Chip-Erase

Standby

VIH

X

X

High Z

X

Write Inhibit

X

VIL

X

High Z/ DOUT

X

 

X

X

VIH

High Z/ DOUT

X

Product Identification

 

 

 

 

 

Software Mode

VIL

VIL

VIH

 

See Table 4

T3.3 398

1. X can be VIL or VIH, but no other value.

©2001 Silicon Storage Technology, Inc.

S71147-02-000 5/01 398

6

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040

Preliminary Specification

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

1st Bus

2nd Bus

3rd Bus

4th Bus

5th Bus

6th Bus

Sequence

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Byte-Program

5555H

AAH

2AAAH

55H

5555H

A0H

BA2

Data

 

 

 

 

Sector-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

SAX3

30H

Chip-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

 

 

 

 

 

 

 

 

 

 

 

 

 

Software ID Entry4,5

5555H

AAH

2AAAH

55H

5555H

90H

 

 

 

 

 

 

Software ID Exit6

XXH

F0H

 

 

 

 

 

 

 

 

 

 

Software ID Exit6

5555H

AAH

2AAAH

55H

5555H

F0H

 

 

 

 

 

 

T4.2 398

1.Address format A14-A0 (Hex), Addresses A15 - AMS can be VIL or VIH, but no other value, for the Command sequence.

2.BA = Program Byte address

3.SAX for Sector-Erase; uses AMS-A12 address lines AMS = Most significant address

AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

4.The device does not remain in Software Product ID Mode if powered down.

5.

With AMS-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0,

 

SST39SF010A Device ID = B5H, is read with A0 = 1

 

SST39SF020A Device ID = B6H, is read with A0 = 1

 

SST39SF040 Device ID = B7H, is read with A0 = 1

6.

Both Software ID Exit operations are equivalent

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-0.5V to VDD + 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-1.0V to VDD + 1.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . 240°C

Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . 100 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range

 

Ambient Temp

 

VDD

 

 

Commercial

 

0°C to +70°C

 

5.0V±10%

 

 

Industrial

 

-40°C to +85°C

 

5.0V±10%

 

 

 

 

 

 

 

 

AC CONDITIONS OF TEST

 

 

 

 

 

 

 

 

Input Rise/Fall Time .

. . . . . . . . . . . . .

5 ns

 

Output Load . . . . . . . .

. . . . . . . . . . . . .

CL = 30 pF for 45 ns

 

Output Load . . . . . . . .

. . . . . . . . . . . . .

CL = 100 pF for 70 ns

 

See Figures 13 and 14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

©2001 Silicon Storage Technology, Inc.

7

S71147-02-000 5/01 398

 

 

 

 

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