Silicon Storage Technology Inc SST39VF800A-55-4E-EN, SST39VF800A-55-4E-EK, SST39VF800A-55-4E-B3N, SST39VF800A-55-4E-B3K, SST39VF800A-55-4C-UK Datasheet

...
0 (0)

2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash

SST39LF200A / SST39LF400A / SST39LF800A

SST39VF200A / SST39VF400A / SST39VF800A

FEATURES:

Organized as 128K x16 / 256K x16 / 512K x16

Single Voltage Read and Write Operations

3.0-3.6V for SST39LF200A/400A/800A

2.7-3.6V for SST39VF200A/400A/800A

Superior Reliability

Endurance: 100,000 Cycles (typical)

Greater than 100 years Data Retention

Low Power Consumption

Active Current: 20 mA (typical)

Standby Current: 3 µA (typical)

Sector-Erase Capability

Uniform 2 KWord sectors

Block-Erase Capability

Uniform 32 KWord blocks

Fast Read Access Time

45 and 55 ns for SST39LF200A/400A

55 ns for SST39LF800A

70 and 90 ns for SST39VF200A/400A/800A

Latched Address and Data

Data Sheet

Fast Erase and Word-Program

Sector-Erase Time: 18 ms (typical)

Block-Erase Time: 18 ms (typical)

Chip-Erase Time: 70 ms (typical)

Word-Program Time: 14 µs (typical)

Chip Rewrite Time:

2 seconds (typical) for SST39LF/VF200A

4 seconds (typical) for SST39LF/VF400A

8 seconds (typical) for SST39LF/VF800A

Automatic Write Timing

Internal VPP Generation

End-of-Write Detection

Toggle Bit

Data# Polling

CMOS I/O Compatibility

JEDEC Standard

Flash EEPROM Pinouts and command sets

Packages Available

48-lead TSOP (12mm x 20mm)

48-ball TFBGA (6mm x 8mm)

PRODUCT DESCRIPTION

The SST39LF200A/400A/800A and SST39VF200A/400A/ 800A devices are 128K x16 / 256K x16 / 512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF200A/400A/800A write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF200A/400A/800A write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories.

Featuring high performance Word-Program, the SST39LF200A/400A/800A and SST39VF200A/400A/ 800A devices provide a typical Word-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, they have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST39LF200A/400A/800A and SST39VF200A/400A/ 800A devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they signifi-

cantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet surface mount requirements, the SST39LF200A/ 400A/800A and SST39VF200A/400A/800A are offered in both 48-lead TSOP packages and 48-ball TFBGA packages. See Figures 1 and 2 for pinouts.

©2001 Silicon Storage Technology, Inc.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

S71117-04-000 6/01

360

MPF is a trademark of Silicon Storage Technology, Inc.

 

 

These specifications are subject to change without notice.

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39LF200A/400A/800A and SST39VF200A/400A/800A is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3).

Word-Program Operation

The SST39LF200A/400A/800A and SST39VF200A/400A/ 800A are programmed on a word-by-word basis. Before programming, one must ensure that the sector, in which the word which is being programmed exists, is fully erased. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. The SST39LF200A/400A/800A and SST39VF200A/400A/800A offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-

Data Sheet

Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of- Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored.

Chip-Erase Operation

The SST39LF200A/400A/800A and SST39VF200A/400A/ 800A provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST39LF200A/400A/800A and SST39VF200A/400A/ 800A provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.

©2001 Silicon Storage Technology, Inc.

S71117-04-000 6/01 360

2

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Data# Polling (DQ7)

When the SST39LF200A/400A/800A and SST39VF200A/ 400A/800A are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Blockor Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 17 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Blockor Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 17 for a flowchart.

Data Protection

The SST39LF200A/400A/800A and SST39VF200A/400A/ 800A provide both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39LF200A/400A/800A and SST39VF200A/400A/ 800A provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence.

Common Flash Memory Interface (CFI)

The SST39LF200A/400A/800A and SST39VF200A/400A/ 800A also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

©2001 Silicon Storage Technology, Inc.

S71117-04-000 6/01 360

3

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

Product Identification

The Product Identification mode identifies the devices as the SST39LF/VF200A, SST39LF/VF400A and SST39LF/ VF800A and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram, and Figure 18 for the Software ID Entry command sequence flowchart.

TABLE 1: PRODUCT IDENTIFICATION TABLE

 

Address

Data

 

 

 

Manufacturer’s ID

0000H

00BFH

 

 

 

Device ID

 

 

SST39LF/VF200A

0001H

2789H

SST39LF/VF400A

0001H

2780H

SST39LF/VF800A

0001H

2781H

 

 

 

T1.3 360

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure 18 for a flowchart.

©2001 Silicon Storage Technology, Inc.

S71117-04-000 6/01 360

4

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SuperFlash

 

 

 

 

 

 

 

 

 

 

X-Decoder

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE#

 

 

Address Buffer & Latches

 

 

 

 

 

 

Y-Decoder

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE#

 

 

 

 

Control Logic

 

 

 

I/O Buffers and Data Latches

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ15 - DQ0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

360 ILL B1.2

SST39LF/VF800A SST39LF/VF400A SST39LF/VF200A

A15

A15

A15

 

1

A14

A14

A14

 

2

A13

A13

A13

 

 

3

A12

A12

A12

 

4

A11

A11

A11

 

5

A10

A10

A10

 

6

A9

A9

A9

 

7

A8

A8

A8

 

8

NC

NC

NC

 

9

NC

NC

NC

 

 

10

WE#

WE#

WE#

 

 

11

NC

NC

NC

 

 

12

NC

NC

NC

 

 

13

NC

NC

NC

 

 

14

NC

NC

NC

 

15

A18

NC

NC

 

 

16

 

 

A17

A17

NC

 

17

A7

A7

A7

 

18

A6

A6

A6

 

19

A5

A5

A5

 

20

A4

A4

A4

 

21

A3

A3

A3

 

22

A2

A2

A2

 

 

23

 

 

A1

A1

A1

 

 

24

 

 

 

 

 

 

 

 

Standard Pinout

Top View

Die Up

SST39LF/VF200A SST39LF/VF400A SST39LF/VF800A

48

 

A16

A16

A16

47

 

NC

NC

NC

46

 

VSS

VSS

VSS

 

45

 

DQ15

DQ15

DQ15

44

 

DQ7

DQ7

DQ7

43

 

DQ14

DQ14

DQ14

42

 

DQ6

DQ6

DQ6

41

 

DQ13

DQ13

DQ13

40

 

DQ5

DQ5

DQ5

39

 

DQ12

DQ12

DQ12

38

 

DQ4

DQ4

DQ4

37

 

VDD

VDD

VDD

 

36

 

DQ11

DQ11

DQ11

35

 

DQ3

DQ3

DQ3

34

 

DQ10

DQ10

DQ10

33

 

DQ2

DQ2

DQ2

32

 

DQ9

DQ9

DQ9

31

 

DQ1

DQ1

DQ1

30

 

DQ8

DQ8

DQ8

29

 

DQ0

DQ0

DQ0

28

 

OE#

OE#

OE#

27

 

VSS

VSS

VSS

 

26

 

CE#

CE#

CE#

 

25

 

A0

A0

A0

 

 

 

 

 

 

SST39LF200A/400A/800A

360 ILL F01.2

SST39VF200A/400A/800A

FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP

©2001 Silicon Storage Technology, Inc.

S71117-04-000 6/01 360

5

Silicon Storage Technology Inc SST39VF800A-55-4E-EN, SST39VF800A-55-4E-EK, SST39VF800A-55-4E-B3N, SST39VF800A-55-4E-B3K, SST39VF800A-55-4C-UK Datasheet

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

6

5

4

3

2

1

 

TOP VIEW

(balls facing down)

 

SST39LF/VF200A

A13

A12

A14

A15

A16

NC

DQ15 VSS

A9

A8

A10

A11

DQ7 DQ14 DQ13 DQ6

WE#

NC

NC

NC

DQ5 DQ12 VDD DQ4

NC

NC

NC

NC

DQ2 DQ10 DQ11 DQ3

A7

NC

A6

A5

DQ0

DQ8

DQ9 DQ1

A3

A4

A2

A1

A0

CE#

OE# VSS

360 ILL F02_2.0

A B C D E F G H

6

5

4

3

2

1

 

TOP VIEW

(balls facing down)

 

SST39LF/VF400A

A13

A12

A14

A15

A16

NC

DQ15 VSS

A9

A8

A10

A11

DQ7 DQ14 DQ13 DQ6

WE#

NC

NC

NC

DQ5 DQ12 VDD DQ4

NC

NC

NC

NC

DQ2 DQ10 DQ11 DQ3

A7

A17

A6

A5

DQ0

DQ8

DQ9 DQ1

A3

A4

A2

A1

A0

CE#

OE# VSS

A

B

C

D

E

F

G H

360 ILL F02_4.0

6

5

4

3

2

1

 

TOP VIEW

(balls facing down)

 

SST39LF/VF800A

A13

A12

A14

A15

A16

NC

DQ15 VSS

A9

A8

A10

A11

DQ7 DQ14 DQ13 DQ6

WE#

NC

NC

NC

DQ5 DQ12 VDD DQ4

NC

NC

A18

NC

DQ2 DQ10 DQ11 DQ3

A7

A17

A6

A5

DQ0

DQ8

DQ9 DQ1

A3

A4

A2

A1

A0

CE#

OE# VSS

A

B

C

D

E

F

G H

360 ILL F02_8.0

FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA

©2001 Silicon Storage Technology, Inc.

S71117-04-000 6/01 360

6

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

TABLE 2: PIN DESCRIPTION

Symbol

Pin Name

Functions

 

 

 

 

AMS1-A0

Address Inputs

To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the

 

 

sector. During Block-Erase AMS-A15 address lines will select the block.

DQ15-DQ0

Data Input/output

To output data during Read cycles and receive input data during Write cycles.

 

 

Data is internally latched during a Write cycle.

 

 

The outputs are in tri-state when OE# or CE# is high.

CE#

Chip Enable

To activate the device when CE# is low.

OE#

Output Enable

To gate the data output buffers.

 

WE#

Write Enable

To control the Write operations.

 

VDD

Power Supply

To provide power supply voltage:

3.0-3.6V for SST39LF200A/400A/800A

 

 

 

2.7-3.6V for SST39VF200A/400A/800A

VSS

Ground

 

 

NC

No Connection

Unconnected pins.

 

 

 

 

 

 

 

 

T2.2 360

1.AMS = Most significant address

AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A, and A18 for SST39LF/VF800A

TABLE 3: OPERATION MODES SELECTION

Mode

CE#

OE#

WE#

DQ

Address

 

 

 

 

 

 

Read

VIL

VIL

VIH

DOUT

AIN

Program

VIL

VIH

VIL

DIN

AIN

Erase

VIL

VIH

VIL

X1

Sector or Block address,

 

 

 

 

 

XXH for Chip-Erase

Standby

VIH

X

X

High Z

X

Write Inhibit

X

VIL

X

High Z/ DOUT

X

 

X

X

VIH

High Z/ DOUT

X

Product Identification

 

 

 

 

 

Software Mode

VIL

VIL

VIH

 

See Table 4

T3.4 360

1. X can be VIL or VIH, but no other value.

©2001 Silicon Storage Technology, Inc.

S71117-04-000 6/01 360

7

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

1st Bus

2nd Bus

3rd Bus

4th Bus

5th Bus

6th Bus

Sequence

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr1

Data2

Addr1

Data2

Addr1

Data2

Addr1

Data2

Addr1

Data2

Addr1

Data2

Word-Program

5555H

AAH

2AAAH

55H

5555H

A0H

WA3

Data

 

 

 

 

Sector-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

SAX4

30H

Block-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

BAX4

50H

Chip-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

 

 

 

 

 

 

 

 

 

 

 

 

 

Software ID Entry5,6

5555H

AAH

2AAAH

55H

5555H

90H

 

 

 

 

 

 

CFI Query Entry5

5555H

AAH

2AAAH

55H

5555H

98H

 

 

 

 

 

 

Software ID Exit7/

XXH

F0H

 

 

 

 

 

 

 

 

 

 

CFI Exit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Software ID Exit7/

5555H

AAH

2AAAH

55H

5555H

F0H

 

 

 

 

 

 

CFI Exit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T4.2 360

1. Address format A14-A0 (Hex),

Addresses A15 and A16 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF200A. Addresses A15, A16, and A17 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF400A. Addresses A15, A16, A17, and A18 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF800A.

2.DQ15 - DQ8 can be VIL or VIH, but no other value, for the Command sequence

3.WA = Program word address

4.SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address

AMS = A16 for SST39LF/VF200A, A17 for SST39LF/VF400A and A18 for SST39LF/VF800A

5.The device does not remain in Software Product ID Mode if powered down.

6.With AMS-A1 =0; SST Manufacturer’s ID= 00BFH, is read with A0 = 0,

SST39LF/VF200A Device ID = 2789H, is read with A0 = 1. SST39LF/VF400A Device ID = 2780H, is read with A0 = 1. SST39LF/VF800A Device ID = 2781H, is read with A0 = 1.

7. Both Software ID Exit operations are equivalent

TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF200A/400A/800A AND SST39VF200A/400A/800A

Address

Data

Data

10H

0051H

Query Unique ASCII string “QRY”

11H

0052H

 

12H

0059H

 

13H

0001H

Primary OEM command set

14H

0007H

 

15H

0000H

Address for Primary Extended Table

16H

0000H

 

17H

0000H

Alternate OEM command set (00H = none exists)

18H

0000H

 

19H

0000H

Address for Alternate OEM extended Table (00H = none exits)

1AH

0000H

 

T5.0 360

1. Refer to CFI publication 100 for more details.

©2001 Silicon Storage Technology, Inc.

S71117-04-000 6/01 360

8

2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A

Data Sheet

 

 

TABLE

6: SYSTEM INTERFACE INFORMATION FOR SST39LF200A/400A/800A AND SST39VF200A/400A/800A

 

 

 

Address

Data

Data

 

 

 

 

1BH

 

0027H1

VDD Min. (Program/Erase)

 

 

0030H1

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH

 

0036H

VDD Max. (Program/Erase)

 

 

 

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH

 

0000H

VPP min. (00H = no VPP pin)

1EH

 

0000H

VPP max. (00H = no VPP pin)

1FH

 

0004H

Typical time out for Word-Program 2N µs (24 = 16 µs)

20H

 

0000H

Typical time out for min. size buffer program 2N µs (00H = not supported)

21H

 

0004H

Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)

22H

 

0006H

Typical time out for Chip-Erase 2N ms (26 = 64 ms)

23H

 

0001H

Maximum time out for Word-Program 2N times typical (21 x 24 = 32 µs)

24H

 

0000H

Maximum time out for buffer program 2N times typical

25H

 

0001H

Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)

26H

 

0001H

Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)

 

 

 

T6.2 360

1. 0030H for SST39LF200A/400A/800A and 0027H for SST39VF200A/400A/800A

TABLE

7: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF200A

 

 

 

Address

Data

Data

27H

 

0012H

Device size = 2N Byte (12H = 18; 218 = 256 KBytes)

28H

 

0001H

Flash Device Interface description; 0001H = x16-only asynchronous interface

29H

 

0000H

 

2AH

 

0000H

Maximum number of byte in multi-byte write = 2N (00H = not supported)

2BH

 

 

 

2CH

 

0002H

Number of Erase Sector/Block sizes supported by device

2DH

 

003FH

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH

 

0000H

y = 63 + 1 = 64 sectors (003FH = 63)

2FH

 

0010H

 

30H

 

0000H

z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)

31H

 

0003H

Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H

 

0000H

y = 3 + 1 = 4 blocks (0003H = 3)

33H

 

0000H

 

34H

 

0001H

z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

 

 

 

T7.2 360

©2001 Silicon Storage Technology, Inc.

S71117-04-000 6/01 360

9

Loading...
+ 21 hidden pages