Silicon Storage Technology Inc SST39VF512-70-4C-B3H, SST39VF512-55-4I-WK, SST39VF512-55-4I-WH, SST39VF512-55-4I-NK, SST39VF512-55-4I-NH Datasheet

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

FEATURES:

Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

Single Voltage Read and Write Operations

3.0-3.6V for SST39LF512/010/020/040

2.7-3.6V for SST39VF512/010/020/040

Superior Reliability

Endurance: 100,000 Cycles (typical)

Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 10 mA (typical)

Standby Current: 1 µA (typical)

Sector-Erase Capability

Uniform 4 KByte sectors

Fast Read Access Time:

45 ns for SST39LF512/010/020/040

55 ns for SST39LF020/040

70 and 90 ns for SST39VF512/010/020/040

Latched Address and Data

Fast Erase and Byte-Program:

Sector-Erase Time: 18 ms (typical)

Chip-Erase Time: 70 ms (typical)

Byte-Program Time: 14 µs (typical)

Chip Rewrite Time:

1 second (typical) for SST39LF/VF512

2 seconds (typical) for SST39LF/VF010

4 seconds (typical) for SST39LF/VF020

8 seconds (typical) for SST39LF/VF040

Automatic Write Timing

Internal VPP Generation

End-of-Write Detection

Toggle Bit

Data# Polling

CMOS I/O Compatibility

JEDEC Standard

Flash EEPROM Pinouts and command sets

Packages Available

32-lead PLCC

32-lead TSOP (8mm x 14mm)

48-ball TFBGA (6mm x 8mm) for 1 Mbit

PRODUCT DESCRIPTION

The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 are 64K x8, 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF512/ 010/020/040 devices write (Program or Erase) with a 3.0- 3.6V power supply. The SST39VF512/010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST39LF512/010/020/040 and SST39VF512/010/020/ 040 devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, they are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they

significantly improves performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet surface mount requirements, the SST39LF512/ 010/020/040 and SST39VF512/010/020/040 devices are offered in 32-lead PLCC and 32-lead TSOP packages. The 39LF/VF010 is also offered in a 48-ball TFBGA package. See Figures 1 and 2 for pinouts.

©2001 Silicon Storage Technology, Inc.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

S71150-03-000 6/01

395

MPF is a trademark of Silicon Storage Technology, Inc.

 

 

These specifications are subject to change without notice.

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39LF512/010/020/040 and SST39VF512/010/020/040 device is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4).

Byte-Program Operation

The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 are programmed on a byte-by-byte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte-com- mand sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE#

Data Sheet

pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored.

Chip-Erase Operation

The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1s” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the ChipErase operation will be ignored.

Write Operation Status Detection

The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

©2001 Silicon Storage Technology, Inc.

S71150-03-000 6/01 395

2

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

Data# Polling (DQ7)

When the SST39LF512/010/020/040 and SST39VF512/ 010/020/040 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sectoror Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart.

Software Data Protection (SDP)

The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or powerdown. Any Erase operation requires the inclusion of six byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sectoror ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart.

Product Identification

The Product Identification mode identifies the devices as the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 and SST39LF/VF040 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram, and Figure 17 for the Software ID entry command sequence flowchart.

Data Protection

The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

TABLE 1: PRODUCT IDENTIFICATION

 

Address

Data

 

 

 

Manufacturer’s ID

0000H

BFH

 

 

 

Device ID

 

 

SST39LF/VF512

0001H

D4H

SST39LF/VF010

0001H

D5H

SST39LF/VF020

0001H

D6H

SST39LF/VF040

0001H

D7H

 

 

 

T1.1 395

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform, and Figure 17 for a flowchart.

©2001 Silicon Storage Technology, Inc.

S71150-03-000 6/01 395

3

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SuperFlash

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X-Decoder

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Buffers & Latches

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y-Decoder

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE#

 

 

Control Logic

 

 

 

 

 

 

 

 

 

 

I/O Buffers and Data Latches

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ7 - DQ0

 

395 ILL B1.1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SST39LF/VF040

A12

A15

A16

A18

V

 

WE#

A17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SST39LF/VF020

 

 

 

 

 

 

DD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A12

A15

A16

NC

V

 

WE#

A17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SST39LF/VF010

 

 

 

 

 

 

DD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A12

A15

A16

NC

V

 

WE#

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SST39LF/VF512

A12

A15

NC

NC

V

 

WE#

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DD

 

 

 

 

 

 

 

 

 

 

SST39LF/VF040

SST39LF/VF020

SST39LF/VF010

SST39LF/VF512

4

3

2

1

32

31

30

 

 

SST39LF/VF512

SST39LF/VF010

SST39LF/VF020

SST39LF/VF040

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

A7

 

 

 

A7

 

A7

5

 

 

 

 

 

 

 

 

 

 

29

A14

A14

A14

A14

A6

A6

 

 

 

A6

 

A6

6

 

 

 

 

 

 

 

 

 

 

28

A13

A13

A13

A13

A5

A5

 

 

 

A5

 

A5

7

 

 

 

 

 

 

 

 

 

 

27

A8

A8

A8

A8

A4

A4

 

 

 

A4

 

A4

8

 

 

32-lead PLCC

26

A9

A9

A9

A9

A3

A3

 

 

 

A3

 

A3

9

 

 

25

A11

A11

A11

A11

 

 

 

 

 

 

 

Top View

 

 

A2

A2

 

 

 

A2

 

A2

10

 

 

 

 

 

24

OE#

OE#

OE#

OE#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

A1

 

 

 

A1

 

A1

11

 

 

 

 

 

 

 

 

 

 

23

A10

A10

A10

A10

A0

A0

 

 

 

A0

 

A0

12

 

 

 

 

 

 

 

 

 

 

22

CE#

CE#

CE#

CE#

DQ0

DQ0

 

 

 

DQ0

 

DQ0

13

 

 

 

 

 

 

 

 

 

 

21

DQ7

DQ7

DQ7

DQ7

 

 

 

 

 

 

 

 

 

 

 

14

15

16

17

18

19

20

 

 

 

 

 

 

 

SST39LF/VF512

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ1

 

DQ2

 

V

 

DQ3

 

DQ4

 

DQ5

 

DQ6

SST39LF/VF010

 

 

 

 

SS

 

 

 

 

 

 

 

 

DQ1

 

DQ2

 

V

 

DQ3

 

DQ4

 

DQ5

 

DQ6

 

 

 

 

 

SS

 

 

 

 

 

 

 

 

SST39LF/VF020

DQ1

 

DQ2

 

V

 

DQ3

 

DQ4

 

DQ5

 

DQ6

SST39LF/VF040

 

 

 

 

SS

 

 

 

 

 

 

 

 

DQ1

 

DQ2

 

V

 

DQ3

 

DQ4

 

DQ5

 

DQ6

 

 

 

 

 

SS

 

 

 

 

 

 

 

 

395 ILL F02b.3

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

©2001 Silicon Storage Technology, Inc.

S71150-03-000 6/01 395

4

Silicon Storage Technology Inc SST39VF512-70-4C-B3H, SST39VF512-55-4I-WK, SST39VF512-55-4I-WH, SST39VF512-55-4I-NK, SST39VF512-55-4I-NH Datasheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

SST39LF/VF040

SST39LF/VF020

SST39LF/VF010

SST39LF/VF512

 

 

A11

A11

A11

A11

 

 

 

1

 

A9

A9

A9

A9

 

 

 

2

 

A8

A8

A8

A8

 

 

 

3

 

A13

A13

A13

A13

 

 

 

4

 

A14

A14

A14

A14

 

 

 

5

Standard Pinout

A17

A17

NC

NC

 

 

 

6

WE#

WE#

WE#

WE#

 

 

 

7

Top View

VDD

VDD

VDD

VDD

 

 

 

8

 

 

 

 

A18

NC

NC

NC

 

 

 

9

Die Up

A16

A16

A16

NC

 

 

 

10

A15

A15

A15

A15

 

 

 

11

 

A12

A12

A12

A12

 

 

 

12

 

A7

A7

A7

A7

 

 

 

13

 

A6

A6

A6

A6

 

 

 

14

 

A5

A5

A5

A5

 

 

 

15

 

A4

A4

A4

A4

 

 

 

16

 

 

 

 

 

 

 

 

 

 

SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040

32

 

 

OE#

OE#

OE#

OE#

31

 

 

A10

A10

A10

A10

30

 

 

CE#

CE#

CE#

CE#

29

 

 

DQ7

DQ7

DQ7

DQ7

28

 

 

DQ6

DQ6

DQ6

DQ6

27

 

 

DQ5

DQ5

DQ5

DQ5

26

 

 

DQ4

DQ4

DQ4

DQ4

25

 

 

DQ3

DQ3

DQ3

DQ3

24

 

 

VSS

VSS

VSS

VSS

 

 

23

 

 

DQ2

DQ2

DQ2

DQ2

22

 

 

DQ1

DQ1

DQ1

DQ1

21

 

 

DQ0

DQ0

DQ0

DQ0

20

 

 

A0

A0

A0

A0

19

 

 

A1

A1

A1

A1

18

 

 

A2

A2

A2

A2

17

 

 

A3

A3

A3

A3

 

 

 

 

 

 

 

395 ILL F01.0

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

 

TOP VIEW

(balls facing down)

 

 

SST39LF/VF010

 

6

 

 

 

NC

NC

NC VSS

A14 A13 A15 A16

5

A8 A11 A12

NC A10 DQ6 DQ7

A9

4

 

 

 

 

 

 

WE# NC NC

NC DQ5 NC VDD DQ4

3

 

 

 

 

 

 

NC NC NC

NC DQ2 DQ3 VDD NC

2

 

 

 

 

 

 

A7

NC

A6

A5

DQ0 NC

NC DQ1

1

 

 

 

 

 

 

A3

A4

A2

A1

A0 CE# OE# VSS

A

B

C

D

E

F

G H

395 ILL F01a.0.eps

FIGURE 3: PIN ASSIGNMENT FOR 48-BALL TFBGA (6MM X 8MM) FOR 1 MBIT

©2001 Silicon Storage Technology, Inc.

S71150-03-000 6/01 395

5

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

TABLE

2: PIN DESCRIPTION

 

 

Symbol

 

Pin Name

Functions

 

 

 

 

 

AMS1-A0

 

Address Inputs

To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the

 

 

 

sector. During Block-Erase AMS-A16 address lines will select the block.

DQ7-DQ0

 

Data Input/output

To output data during Read cycles and receive input data during Write cycles.

 

 

 

Data is internally latched during a Write cycle.

 

 

 

The outputs are in tri-state when OE# or CE# is high.

CE#

 

Chip Enable

To activate the device when CE# is low.

OE#

 

Output Enable

To gate the data output buffers.

 

WE#

 

Write Enable

To control the Write operations.

 

VDD

 

Power Supply

To provide power supply voltage:

3.0-3.6V for SST39LF512/010/020/040

 

 

 

 

2.7-3.6V for SST39VF512/010/020/040

VSS

 

Ground

 

 

NC

 

No Connection

Unconnected pins.

 

 

 

 

 

 

 

 

 

 

T2.1 395

1.AMS = Most significant address

AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040

TABLE 3: OPERATION MODES SELECTION

Mode

CE#

OE#

WE#

DQ

Address

 

 

 

 

 

 

Read

VIL

VIL

VIH

DOUT

AIN

Program

VIL

VIH

VIL

DIN

AIN

Erase

VIL

VIH

VIL

X1

Sector address,

 

 

 

 

 

XXH for Chip-Erase

Standby

VIH

X

X

High Z

X

Write Inhibit

X

VIL

X

High Z/ DOUT

X

 

X

X

VIH

High Z/ DOUT

X

Product Identification

 

 

 

 

 

Software Mode

VIL

VIL

VIH

 

See Table 4

T3.4 395

1. X can be VIL or VIH, but no other value.

©2001 Silicon Storage Technology, Inc.

S71150-03-000 6/01 395

6

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

1st Bus

2nd Bus

3rd Bus

4th Bus

5th Bus

6th Bus

Sequence

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Byte-Program

5555H

AAH

2AAAH

55H

5555H

A0H

BA2

Data

 

 

 

 

Sector-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

SAX3

30H

Chip-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

 

 

 

 

 

 

 

 

 

 

 

 

 

Software ID Entry4,5

5555H

AAH

2AAAH

55H

5555H

90H

 

 

 

 

 

 

Software ID Exit6

XXH

F0H

 

 

 

 

 

 

 

 

 

 

Software ID Exit6

5555H

AAH

2AAAH

55H

5555H

F0H

 

 

 

 

 

 

T4.2 395

1. Address format A14-A0 (Hex),

Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF512. Addresses A15-A16 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF010. Addresses A15-A17 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF020. Addresses A15-A18 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF040.

2.BA = Program Byte address

3.SAX for Sector-Erase; uses AMS-A12 address lines AMS = Most significant address

AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040

4.The device does not remain in Software Product ID Mode if powered down.

5.

With AMS-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0,

 

SST39LF/VF512 Device ID = D4H, is read with A0 = 1

 

SST39LF/VF010 Device ID = D5H, is read with A0 = 1

 

SST39LF/VF020 Device ID = D6H, is read with A0 = 1

 

SST39LF/VF040 Device ID = D7H, is read with A0 = 1

6.

Both Software ID Exit operations are equivalent

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-0.5V to VDD + 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-1.0V to VDD + 1.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . 1.0W

Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST39LF512/010/020/040

Range

Ambient Temp

VDD

Commercial

0°C to +70°C

3.0-3.6V

 

 

 

OPERATING RANGE FOR SST39VF512/010/020/040

Range

Ambient Temp

VDD

Commercial

0°C to +70°C

2.7-3.6V

Industrial

-40°C to +85°C

2.7-3.6V

 

 

 

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load

CL = 30 pF for SST39LF512/010/020/040 CL = 100 pF for SST39VF512/010/020/040

See Figures 13 and 14

©2001 Silicon Storage Technology, Inc.

S71150-03-000 6/01 395

7

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

TABLE

5: DC OPERATING CHARACTERISTICS

 

 

 

 

 

 

 

 

 

 

VDD = 3.0-3.6V FOR SST39LF512/010/020/040 AND 2.7-3.6V FOR SST39VF512/010/020/040

 

 

 

 

 

 

 

Limits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

 

Parameter

 

Min

 

Max

Units

Test Conditions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDD

 

 

Power Supply Current

 

 

 

 

 

Address input=VIL/VIH, at f=1/TRC Min

 

 

 

 

 

 

 

 

 

 

VDD=VDD Max

 

 

 

 

Read

 

 

 

20

mA

CE#=OE#=VIL, WE#=VIH, all I/Os open

 

 

 

Write

 

 

 

20

mA

CE#=WE#=VIL, OE#=VIH

 

ISB

 

 

Standby VDD Current

 

 

 

15

µA

CE#=VIHC, VDD=VDD Max

 

ILI

 

 

Input Leakage Current

 

 

 

1

µA

VIN=GND to VDD, VDD=VDD Max

 

ILO

 

 

Output Leakage Current

 

 

 

10

µA

VOUT=GND to VDD, VDD=VDD Max

 

VIL

 

 

Input Low Voltage

 

 

 

0.8

V

VDD=VDD Min

 

VIH

 

 

Input High Voltage

 

0.7VDD

 

 

V

VDD=VDD Max

 

VIHC

 

 

Input High Voltage (CMOS)

 

VDD-0.3

 

 

V

VDD=VDD Max

 

VOL

 

 

Output Low Voltage

 

 

 

0.2

V

IOL=100 µA, VDD=VDD Min

 

VOH

 

 

Output High Voltage

 

VDD-0.2

 

 

V

IOH=-100 µA, VDD=VDD Min

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T5.2 395

TABLE

6: RECOMMENDED SYSTEM POWER-UP TIMINGS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

 

 

Parameter

 

 

 

 

 

Minimum

 

Units

 

 

 

 

 

 

 

 

 

 

 

TPU-READ1

 

Power-up to Read Operation

 

 

 

 

 

100

 

µs

TPU-WRITE1

 

Power-up to Program/Erase Operation

 

 

100

 

µs

 

 

 

 

 

 

 

 

 

 

 

 

 

T6.1 395

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

Maximum

 

 

 

 

CI/O1

I/O Pin Capacitance

VI/O = 0V

12 pF

CIN1

Input Capacitance

VIN = 0V

6 pF

T7.0 395

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE

8: RELIABILITY CHARACTERISTICS

 

 

 

Symbol

 

Parameter

Minimum Specification

Units

Test Method

 

 

 

 

 

 

NEND1

 

Endurance

10,000

Cycles

JEDEC Standard A117

TDR1

 

Data Retention

100

Years

JEDEC Standard A103

ILTH1

 

Latch Up

100 + IDD

mA

JEDEC Standard 78

T8.2 395

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

©2001 Silicon Storage Technology, Inc.

S71150-03-000 6/01 395

8

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