Silicon Storage Technology Inc SST39VF080-90-4C-EK, SST39VF080-90-4C-EI, SST39VF080-90-4C-B3K, SST39VF080-90-4C-B3I, SST39VF080-70-4I-EK Datasheet

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8 Mbit / 16 Mbit (x8) Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

FEATURES:

Organized as 1M x8 / 2M x8

Single Voltage Read and Write Operations

3.0-3.6V for SST39LF080/016

2.7-3.6V for SST39VF080/016

Superior Reliability

Endurance: 100,000 Cycles (typical)

Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 15 mA (typical)

Standby Current: 4 µA (typical)

Auto Low Power Mode: 4 µA (typical)

Sector-Erase Capability

Uniform 4 KByte sectors

Block-Erase Capability

Uniform 64 KByte blocks

Fast Read Access Time:

55 ns for SST39LF080/016

70 and 90 ns for SST39VF080/016

Latched Address and Data

Data Sheet

Fast Erase and Byte-Program:

Sector-Erase Time: 18 ms (typical)

Block-Erase Time: 18 ms (typical)

Chip-Erase Time: 70 ms (typical)

Byte-Program Time: 14 µs (typical)

Chip Rewrite Time:

15 seconds (typical) for SST39LF/VF080

30 seconds (typical) for SST39LF/VF016

Automatic Write Timing

Internal VPP Generation

End-of-Write Detection

Toggle Bit

Data# Polling

CMOS I/O Compatibility

JEDEC Standard

Flash EEPROM Pinouts and command sets

Packages Available

40-lead TSOP (10mm x 20mm)

48-ball TFBGA (6mm x 8mm)

PRODUCT DESCRIPTION

The SST39LF/VF080 and SST39LF/VF016 devices are 1M x8 / 2M x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF080/016 write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF080/016 write (Program or Erase) with a 2.7-3.6V power supply. They conform to JEDEC standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST39LF/ VF080 and SST39LF/VF016 devices provide a typical Byte-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST39LF/VF080 and SST39LF/VF016 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption.

They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. They also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST39LF/VF080 and SST39LF/VF016 are offered in 40lead TSOP and 48-ball TFBGA packaging. See Figures 1 and 2 for pinouts.

©2001 Silicon Storage Technology, Inc.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

S71146-03-000 6/01

396

MPF is a trademark of Silicon Storage Technology, Inc.

 

 

These specifications are subject to change without notice.

8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST39LF/VF080 and SST39LF/VF016 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 15 mA to typically 4 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 1 mA/MHz of read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto Low Power mode after power-up with CE# held steadily low until the first address transition or CE# is driven high.

Read

The Read operation of the SST39LF/VF080 and SST39LF/VF016 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3).

Byte-Program Operation

The SST39LF/VF080 and SST39LF/VF016 are programmed on a byte-by-byte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Program operation consists of three steps. The first step is the threebyte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads

Data Sheet

are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. The SST39LF/VF080 and SST39LF/VF016 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform block size of 64 KByte. The Sector-Erase operation is initiated by executing a six-byte-command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte-command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored.

Chip-Erase Operation

The SST39LF/VF080 and SST39LF/VF016 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST39LF/VF080 and SST39LF/VF016 provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.

©2001 Silicon Storage Technology, Inc.

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2

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST39LF/VF080 and SST39LF/VF016 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Blockor Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 17 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 17 for a flowchart.

Data Protection

The SST39LF/VF080 and SST39LF/VF016 provide both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39LF/VF080 and SST39LF/VF016 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST39LF/VF080 and SST39LF/VF016 devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC.

Common Flash Memory Interface (CFI)

The SST39LF/VF080 and SST39LF/VF016 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 5555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 8. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

©2001 Silicon Storage Technology, Inc.

S71146-03-000 6/01 396

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8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

Product Identification

The Product Identification mode identifies the device as the SST39LF080, SST39VF080, SST39LF016, and SST39VF016 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 11 for the Software ID Entry and Read timing diagram and Figure 18 for the Software ID Entry command sequence flowchart.

TABLE 1: PRODUCT IDENTIFICATION

 

Address

Data

 

 

 

Manufacturer’s ID

0000H

BFH

 

 

 

Device ID

 

 

SST39LF/VF080

0001H

D8H

SST39LF/VF016

0001H

D9H

 

 

 

T1.2 396

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure 18 for a flowchart.

FUNCTIONAL BLOCK DIAGRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SuperFlash

 

 

 

 

 

 

 

 

 

 

X-Decoder

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Buffer & Latches

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y-Decoder

CE#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE#

 

 

 

 

Control Logic

 

 

 

 

I/O Buffers and Data Latches

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ7 - DQ0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

396 ILL B1.2

©2001 Silicon Storage Technology, Inc.

S71146-03-000 6/01 396

4

Silicon Storage Technology Inc SST39VF080-90-4C-EK, SST39VF080-90-4C-EI, SST39VF080-90-4C-B3K, SST39VF080-90-4C-B3I, SST39VF080-70-4I-EK Datasheet

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

SST39LF/VF160

SST39LF/VF080

 

 

 

 

A16

A16

 

 

1

 

A15

A15

 

2

 

A14

A14

 

3

 

A13

A13

 

4

 

A12

A12

 

5

 

A11

A11

 

6

 

A9

A9

 

7

 

A8

A8

 

8

Standard Pinout

WE#

WE#

 

9

NC

NC

 

 

10

Top View

NC

NC

 

 

11

NC

NC

 

 

12

Die Up

A18

A18

 

 

13

A7

A7

 

 

14

 

A6

A6

 

15

 

A5

A5

 

 

16

 

 

 

 

A4

A4

 

17

 

A3

A3

 

18

 

A2

A2

 

19

 

A1

A1

 

20

 

 

 

 

 

 

 

FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP

TOP VIEW (balls facing down)

SST39LF/VF080

6

 

 

 

 

 

 

VSS

 

6

A14

A13

A15

A16

A17

NC

NC

 

 

5

A8

A11

A12

A19

A10

DQ6 DQ7

 

5

A9

 

 

4

 

 

 

 

 

VDD DQ4

 

4

WE#

NC

NC

NC

DQ5

NC

 

 

3

 

 

 

DQ2 DQ3 VDD

 

 

3

NC

NC

NC

NC

NC

 

 

2

 

 

 

 

 

 

 

F20.1

2

A7

A18

A6

A5

DQ0

NC

NC

DQ1

 

 

 

1

 

 

 

 

 

 

 

ILL

1

A3

A4

A2

A1

A0

CE#

OE# VSS

 

396

 

A

B

C

D

E

F

G

H

 

 

FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA

©2001 Silicon Storage Technology, Inc.

5

SST39LF/VF080 SST39LF/VF016

40

 

A17

A17

39

 

VSS

VSS

 

38

 

NC

A20

37

 

A19

A19

36

 

A10

A10

35

 

DQ7

DQ7

34

 

DQ6

DQ6

33

 

DQ5

DQ5

32

 

DQ4

DQ4

31

 

VDD

VDD

 

30

 

VDD

VDD

 

29

 

NC

NC

28

 

DQ3

DQ3

27

 

DQ2

DQ2

26

 

DQ1

DQ1

25

 

DQ0

DQ0

24

 

OE#

OE#

 

23

 

VSS

VSS

 

22

 

CE#

CE#

 

21

 

A0

A0

 

396 ILL F01.2

 

TOP VIEW

(balls facing down)

 

 

SST39LF/VF016

 

 

 

A14

A13

A15

A16

A17

NC

A20

VSS

 

A9

A8

A11

A12

A19

A10

DQ6 DQ7

 

WE#

NC

NC

NC

DQ5

NC

VDD DQ4

 

NC

NC

NC

NC

DQ2 DQ3

VDD

NC

F21.1ILL

A7

A18

A6

A5

DQ0

NC

NC

DQ1

 

A3

A4

A2

A1

A0

CE#

OE# VSS

396

 

 

 

 

 

 

 

 

A

B

C

D

E

F

G

H

 

S71146-03-000 6/01 396

8 Mbit / 16 Mbit Multi-Purpose Flash SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

TABLE

2: PIN DESCRIPTION

 

 

Symbol

 

Pin Name

Functions

 

 

 

 

 

AMS1-A0

 

Address Inputs

To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the

 

 

 

sector. During Block-Erase AMS-A16 address lines will select the block.

DQ7-DQ0

 

Data Input/output

To output data during Read cycles and receive input data during Write cycles.

 

 

 

Data is internally latched during a Write cycle.

 

 

 

The outputs are in tri-state when OE# or CE# is high.

CE#

 

Chip Enable

To activate the device when CE# is low.

OE#

 

Output Enable

To gate the data output buffers.

 

WE#

 

Write Enable

To control the Write operations.

 

VDD

 

Power Supply

To provide power supply voltage:

3.0-3.6V for SST39LF080/016

 

 

 

 

2.7-3.6V for SST39VF080/016

VSS

 

Ground

 

 

NC

 

No Connection

Unconnected pins.

 

 

 

 

 

 

 

 

 

 

T2.3 396

1.AMS = Most significant address

AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016

TABLE 3: OPERATION MODES SELECTION

Mode

CE#

OE#

WE#

DQ

Address

 

 

 

 

 

 

Read

VIL

VIL

VIH

DOUT

AIN

Program

VIL

VIH

VIL

DIN

AIN

Erase

VIL

VIH

VIL

X1

Sector or Block address,

 

 

 

 

 

XXH for Chip-Erase

Standby

VIH

X

X

High Z

X

Write Inhibit

X

VIL

X

High Z/ DOUT

X

 

X

X

VIH

High Z/ DOUT

X

Product Identification

 

 

 

 

 

Software Mode

VIL

VIL

VIH

 

See Table 4

T3.4 396

1. X can be VIL or VIH, but no other value.

©2001 Silicon Storage Technology, Inc.

S71146-03-000 6/01 396

6

8 Mbit / 16 Mbit Multi-Purpose Flash

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

Data Sheet

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

1st Bus

2nd Bus

3rd Bus

4th Bus

5th Bus

6th Bus

Sequence

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Byte-Program

5555H

AAH

2AAAH

55H

5555H

A0H

WA2

Data

 

 

 

 

Sector-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

SAX3

30H

Block-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

BAX3

50H

Chip-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

 

 

 

 

 

 

 

 

 

 

 

 

 

Software ID Entry4,5

5555H

AAH

2AAAH

55H

5555H

90H

 

 

 

 

 

 

CFI Query Entry4

5555H

AAH

2AAAH

55H

5555H

98H

 

 

 

 

 

 

Software ID Exit6/

XXH

F0H

 

 

 

 

 

 

 

 

 

 

CFI Exit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Software ID Exit6/

5555H

AAH

2AAAH

55H

5555H

F0H

 

 

 

 

 

 

CFI Exit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T4.3 396

1.Address format A14-A0 (Hex),

Addresses A15 - A19 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF080. Addresses A15 - A20 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF016.

2.WA = Program Byte address

3.SAX for Sector-Erase; uses AMS-A12 address lines BAX, for Block-Erase; uses AMS-A16 address lines AMS = Most significant address

AMS = A19 for SST39LF/VF080 and A20 for SST39LF/VF016

4.The device does not remain in Software Product ID Mode if powered down.

5. With AMS-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0, SST39LF/VF080 Device ID = D8H, is read with A0 = 1 SST39LF/VF016 Device ID = D9H, is read with A0 = 1

6. Both Software ID Exit operations are equivalent

TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF/VF080 AND SST39LF/VF016

Address

Data

Data

10H

51H

Query Unique ASCII string “QRY”

11H

52H

 

12H

59H

 

13H

01H

Primary OEM command set

14H

07H

 

15H

00H

Address for Primary Extended Table

16H

00H

 

17H

00H

Alternate OEM command set (00H = none exists)

18H

00H

 

19H

00H

Address for Alternate OEM extended Table (00H = none exits)

1AH

00H

 

T5.3 396

1. Refer to CFI publication 100 for more details.

©2001 Silicon Storage Technology, Inc.

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8 Mbit / 16 Mbit Multi-Purpose Flash

 

 

 

SST39LF080 / SST39LF016 / SST39VF080 / SST39VF016

 

 

 

 

 

 

 

Data Sheet

TABLE

6: SYSTEM INTERFACE INFORMATION FOR SST39VF320/640

 

 

 

Address

Data

Data

 

 

 

 

1BH

 

27H1

VDD Min (Program/Erase)

 

 

30H1

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH

 

36H

VDD Max (Program/Erase)

 

 

 

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH

 

00H

VPP min. (00H = no VPP pin)

1EH

 

00H

VPP max. (00H = no VPP pin)

1FH

 

04H

Typical time out for Byte-Program 2N µs (24 = 16 µs)

20H

 

00H

Typical time out for min. size buffer program 2N µs (00H = not supported)

21H

 

04H

Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)

22H

 

06H

Typical time out for Chip-Erase 2N ms (26 = 64 ms)

23H

 

01H

Maximum time out for Byte-Program 2N times typical (21 x 24 = 32 µs)

24H

 

00H

Maximum time out for buffer program 2N times typical

25H

 

01H

Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)

26H

 

01H

Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)

 

 

 

T6.1 396

1. 0030H for SST39LF080/016 and 0027H for SST39VF080/016

TABLE

7: DEVICE GEOMETRY INFORMATION FOR SST39LF/VF080

 

 

 

Address

Data

Data

27H

 

14H

Device size = 2N Bytes (14H = 20; 220 = 1 MBytes)

28H

 

00H

Flash Device Interface description; 0000H = x8-only asynchronous interface

29H

 

00H

 

2AH

 

00H

Maximum number of byte in multi-byte write = 2N (00H = not supported)

2BH

 

00H

 

2CH

 

02H

Number of Erase Sector/Block sizes supported by device

2DH

 

FFH

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH

 

00H

y = 255 + 1 = 256 sectors (00FFH = 255)

2FH

 

10H

 

30H

 

00H

z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)

31H

 

0FH

Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H

 

00H

y = 15 + 1 = 16 blocks (000FH = 15)

33H

 

00H

 

34H

 

01H

z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)

 

 

 

T7.0 396

©2001 Silicon Storage Technology, Inc.

S71146-03-000 6/01 396

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