Silicon Storage Technology Inc SST34HF1641-90-4E-LFP, SST34HF1641-90-4E-L1P, SST34HF1641-90-4C-LFP, SST34HF1641-90-4C-L1P, SST34HF1641-70-4E-LFP Datasheet

...
0 (0)

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory

SST34HF1621 / SST34HF1641

Data Sheet

FEATURES:

Flash Organization: 1M x16

Dual-Bank Architecture for Concurrent Read/Write Operation

16 Mbit: 12 Mbit + 4 Mbit

SRAM Organization:

2 Mbit: 256K x8 or 128K x16

4 Mbit: 512K x8 or 256K x16

Single 2.7-3.3V Read and Write Operations

Superior Reliability

Endurance: 100,000 Cycles (typical)

Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 25 mA (typical)

Standby Current: 20 µA (typical)

Hardware Sector Protection (WP#)

Protects 4 outer most sectors (4 KWord) in the larger bank by holding WP# low and unprotects by holding WP# high

Hardware Reset Pin (RST#)

Resets the internal state machine to reading data array

Sector-Erase Capability

Uniform 1 KWord sectors

Block-Erase Capability

Uniform 32 KWord blocks

Read Access Time

Flash: 70 and 90 ns

SRAM: 70 and 90 ns

Latched Address and Data

Fast Erase and Word-Program:

Sector-Erase Time: 18 ms (typical)

Block-Erase Time: 18 ms (typical)

Chip-Erase Time: 70 ms (typical)

Word-Program Time: 14 µs (typical)

Chip Rewrite Time: 8 seconds (typical)

Automatic Write Timing

Internal VPP Generation

End-of-Write Detection

Toggle Bit

Data# Polling

Ready/Busy# pin

CMOS I/O Compatibility

JEDEC Standard Command Set

Conforms to Common Flash Memory Interface (CFI)

Packages Available

56-ball LFBGA (8mm x 10mm)

PRODUCT DESCRIPTION

The SST34HF1621/1641 ComboMemory devices integrate a 1M x16 CMOS flash memory bank with a 256K x8/ 128K x16 or 512K x8/ 256K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP). These devices are fabricated using SST’s proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF1621/1641 devices are ideal for applications such as cellular phones, GPSs, PDAs and other portable electronic devices in a low power and small form factor system.

The SST34HF1621/1641 features dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the SRAM. The devices can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The two flash memory banks are partitioned into 4 Mbit and 12 Mbit with top or bottom sector protection options for storing boot code, program code, configuration/parameter data and user data.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF1621/1641 devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high performance Word-Program, the flash memory banks provide a typical Word-Program time of 14 µsec. The entire flash memory bank can be erased and programmed word-by- word in typically 8 seconds for the SST34HF1621/1641, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST34HF1621/ 1641 devices contain on-chip hardware and software data protection schemes.

©2001 Silicon Storage Technology, Inc.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

S71172-05-000 10/01

523

Concurrent SuperFlash and ComboMemory are trademarks of Silicon Storage Technology, Inc.

 

 

These specifications are subject to change without notice.

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF1621 / SST34HF1641

The flash and SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The SRAM bank enable signal, BES1# and BES2, selects the SRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. Bus contention is eliminated as the device will not recognize both bank enables as being simultaneously active.

Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF1621/ 1641 are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements.

Device Operation

The SST34HF1621/1641 uses BES1#, BES2 and BEF# to control operation of either the flash or the SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low, and BES2 is high the SRAM is activated for Read and Write operation. BEF# and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES1# bank enables are raised to VIHC (Logic High) or when BEF# is high and BES2 is low.

Concurrent Read/Write Operation

Dual bank architecture of SST34HF1621/1641 devices allows the Concurrent Read/Write operation whereby the user can read from one bank while program or erase in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank. See Figure 1 for Dual-Bank Memory Organization.

 

 

Data Sheet

CONCURRENT READ/WRITE STATE TABLE

 

 

 

Flash

 

 

 

 

Bank 1

Bank 2

SRAM

 

 

 

Read

Write

No Operation

 

 

 

Write

Read

No Operation

 

 

 

Write

No Operation

Read

 

 

 

No Operation

Write

Read

 

 

 

Write

No Operation

Write

 

 

 

No Operation

Write

Write

 

 

 

Note: For the purposes of this table, write means to Block-, Sector, or Chip-Erase, or Word-Program as applicable to the appropriate bank.

Flash Read Operation

The Read operation of the SST34HF1621/1641 is controlled by BEF# and OE#, both have to be low for the system to obtain data from the outputs. BEF# is used for device selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6).

Flash Word-Program Operation

The SST34HF1621/1641 are programmed on a word-by- word basis. Before Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed typically within 10 µs. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 21 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.

©2001 Silicon Storage Technology, Inc.

S71172-05-000 10/01 523

2

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF1621 / SST34HF1641

Data Sheet

Flash Sector/Block-Erase Operation

The Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector or block-by-block basis. The SST34HF1621/1641 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 1 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. See Figures 12 and 13 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored.

Flash Chip-Erase Operation

The SST34HF1621/1641 provide a Chip-Erase operation, which allows the user to erase all unprotected sectors/ blocks to the “1” state. This is useful when the device must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 11 for timing diagram, and Figure 24 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.

Flash Write Operation Status Detection

The SST34HF1621/1641 provide one hardware and two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The hardware detection uses the Ready/Busy# (RY/BY#) pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result,

i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Ready/Busy# (RY/BY#)

The SST34HF1621/1641 includes a Ready/Busy# (RY/ BY#) output signal. RY/BY# is actively pulled low during internal Program/Erase operation. The status of RY/BY# is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Blockor Bank-Erase, the RY/BY# is valid after the rising edge of sixth WE# or (CE#) pulse. RY/BY# is an open drain output that allows several devices to be tied in parallel to VDD via an external pull up resistor. Ready/Busy# is in high impedance whenever OE# or CE# is high or RST# is low.

Flash Data# Polling (DQ7)

When the SST34HF1621/1641 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling (DQ7) is valid after the rising edge of fourth WE# (or BEF#) pulse for Program operation. For Sector-, Blockor Chip-Erase, the Data# Polling (DQ7) is valid after the rising edge of sixth WE# (or BEF#) pulse. After the completion of a Program operation, Data# Polling on DQ7 remains active and the device may not return to the Read mode for approximately 1 µs. See Figure 9 for Data# Polling (DQ7) timing diagram and Figure 22 for a flowchart.

Flash Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. After the completion of a Program operation, DQ6 will stop toggling for approximately 1 µs. The device is then ready for the next operation. The Toggle Bit (DQ6) is valid after the rising edge of fourth WE# (or BEF#) pulse for Program operation. For Sector-, Blockor Chip-Erase, the

©2001 Silicon Storage Technology, Inc.

S71172-05-000 10/01 523

3

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF1621 / SST34HF1641

Toggle Bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. See Figure 10 for Toggle Bit timing diagram and Figure 22 for a flowchart.

Data Protection

The SST34HF1621/1641 provide both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

Data Sheet

Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST34HF1621/1641 are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15- DQ8 are “Don’t Care” during any SDP command sequence.

Common Flash Memory Interface (CFI)

The SST34HF1621/1641 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write threebyte sequence, same as Software ID Entry command with 98H (CFI Query command) to address 555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

Hardware Block Protection

The SST34HF1621/1641 provide a hardware block protection which protects the outermost 4 KWord in the larger bank.The block is protected when WP# is held low. See Figure 1 for Block-Protection location.

A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 18). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 17).

The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity.

Software Data Protection (SDP)

Product Identification

The Product Identification mode identifies the devices as the SST34HF1621/1641 and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 3 and 4 for software operation, Figure 14 for the software ID entry and read timing diagram and Figure 23 for the ID entry command sequence flowchart.

TABLE 1: PRODUCT IDENTIFICATION

 

ADDRESS

DATA

 

 

 

Manufacturer’s ID

0000H

00BFH

 

 

 

Device ID

 

 

SST34HF1621

0001H

2761H

SST34HF1641

0001H

2761H

 

 

 

T1.2 523

The SST34HF1621/1641 provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent

©2001 Silicon Storage Technology, Inc.

S71172-05-000 10/01 523

4

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF1621 / SST34HF1641

Data Sheet

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 16 for timing waveform and Figure 23 for a flowchart.

deselected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 3 for SRAM Read and Write data byte control modes of operation.

SRAM Read

The SRAM Read operation of the SST34HF1621/1641 is controlled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the outputs. BES1# and BES2 are used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 3, for further details.

SRAM Operation

With BES1# low, BES2 and BEF# high, the SST34HF162x operates as 256K x8 or 128K x16 CMOS SRAM, and the SST34HF164x operates as 512K x8 or 256K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The CIOs pin configures the SRAM for x8 or x16 SRAM operation modes. The SST34HF162x SRAM is mapped into the first 256 KByte/128 KWord address space of the device, and the SST34HF164x SRAM is mapped into the first 512 KByte/256 KWord address space. When BES1#, BEF# are high and BES2 is low, all memory banks are

SRAM Write

The SRAM Write operation of the SST34HF1621/1641 is controlled by WE# and BES1#, both have to be low, BES2 have to be high for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES1#, WE#, or the falling edge of BES2 whichever occurs first. The write time is measured from the last falling edge of BES#1 or WE# or the rising edge of BES2 to the first rising edge of BES1#, or WE# or the falling edge of BES2. Refer to the Write cycle timing diagram, Figures 4 and 5, for further details.

FUNCTIONAL BLOCK DIAGRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AMS - A0

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Buffers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SuperFlash Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RST#

 

 

 

 

 

 

 

 

(Bank 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BEF#

 

 

 

 

 

 

 

 

SuperFlash Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WP#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SA

 

 

 

 

 

 

 

 

(Bank 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LBS#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UBS#

 

 

 

Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Logic

 

 

 

 

 

 

 

 

 

 

 

DQ15 - DQ8

 

 

OE#

 

 

 

 

 

 

 

 

 

 

I/O Buffers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BES1#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ7 - DQ0

 

 

BES2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CIOs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RY/BY#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 Mbit or 4 Mbit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Buffers

 

 

 

 

 

 

 

523 ILL B1.1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AMS = Most significant address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

©2001 Silicon Storage Technology, Inc.

 

 

 

 

 

 

 

 

 

 

 

 

S71172-05-000 10/01 523

5

Silicon Storage Technology Inc SST34HF1641-90-4E-LFP, SST34HF1641-90-4E-L1P, SST34HF1641-90-4C-LFP, SST34HF1641-90-4C-L1P, SST34HF1641-70-4E-LFP Datasheet

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF1621 / SST34HF1641

Data Sheet

Bottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors

4 KWord Sector Protection

(Four 1 KWord Sectors)

FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H

007FFFH

001000H

000FFFH

000000H

Block 31

 

Block 30

 

Block 29

Bank

Block 28

 

Block 27

2

 

Block 26

 

Block 25

 

Block 24

 

Block 23

 

Block 22

 

Block 21

 

Block 20

 

Block 19

 

Block 18

 

Block 17

 

Block 16

 

Block 15

 

Block 14

 

Block 13

1Bank

Block 12

 

Block 11

 

Block 10

 

Block 9

 

Block 8

 

Block 7

 

Block 6

 

Block 5

 

Block 4

 

Block 3

 

Block 2

 

Block 1

 

Block 0

 

 

523 ILL F02.1

FIGURE 1: SST34HF1621/1641, 1 MBIT X 16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION

©2001 Silicon Storage Technology, Inc.

S71172-05-000 10/01 523

6

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF1621 / SST34HF1641

Data Sheet

TOP VIEW (balls facing down)

SST34HF1621/1641

 

8

 

A15

NC

NC

A16

NC

VSS

 

 

 

 

 

 

7

A11

A12

A13

A14

SA

DQ15

DQ7 DQ14

 

 

 

6

A8

A19

A9

A10

DQ6

DQ13

DQ12 DQ5

 

 

 

5

WE# BES2

NC

 

 

DQ4

VDDS CIOs

 

4

 

 

 

WP#

RST#

RY/BY#

 

 

DQ3

VDDF DQ11

 

3

 

 

 

LBS# UBS# A18

A17

DQ1

DQ9

DQ10

DQ2

 

 

 

2

A7

A6

A5

A4

VSS

OE#

DQ0

DQ8

 

1

 

 

A3

A2

A1

A0

BEF# BES1#

 

 

 

 

 

 

 

A

B

C

D

E F

G

H

 

 

 

 

 

 

 

 

 

523 56-lfbga ILL P01.2

FIGURE

2: PIN ASSIGNMENTS FOR 56-BALL LFBGA (8MM X 10MM) COMBOMEMORY PINOUT

TABLE 2: PIN DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Pin Name

Functions

 

 

 

 

 

 

 

 

 

AMS1 to A0

Address Inputs

To provide flash address, A19-A0.

 

 

To provide SRAM address, A16-A0 for 2M and A17-A0 for 4M

SA

Address Input (SRAM)

To provide SRAM address input in byte mode (x8). When CIOs is VIL, the SRAM is in

 

 

Byte mode and SA provides the most significant address input. When CIOs is VIH, the

 

 

SRAM is in Word mode and SA becomes a Don’t Care pin.

DQ15-DQ0

Data Inputs/Outputs

To output data during Read cycles and receive input data during Write cycles.

 

 

Data is internally latched during a flash Erase/Program cycle. The outputs are in

 

 

tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.

BEF#

Flash Memory Bank Enable

To activate the Flash memory bank when BEF# is low

BES1#

SRAM Memory Bank Enable

To activate the SRAM memory bank when BES1# is low

BES2

SRAM Memory Bank Enable

To activate the SRAM memory bank when BES2 is high

OE#

Output Enable

To gate the data output buffers

 

WE#

Write Enable

To control the Write operations

 

UBS#

Upper Byte Control (SRAM)

To enable DQ15-DQ8

 

 

 

LBS#

Lower Byte Control (SRAM)

To enable DQ7-DQ0

 

 

 

 

CIOs

I/O Configuration (SRAM)

CIOs = VIH is Word mode (x16), CIOs = VIL is Byte mode (x8)

WP#

Write Protect

To protect and unprotect sectors from Erase or Program operation

RST#

Reset

To Reset and return the device to Read mode

RY/BY#

Ready/Busy#

To output the status of a Program or Erase Operation

 

 

RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required to

 

 

allow RY/BY# to transition high indicating the device is ready to read.

VSS

Ground

 

 

 

 

 

 

 

 

VDDF

Power Supply (Flash)

2.7-3.3V Power Supply to Flash only

VDDS

Power Supply (SRAM)

2.7-3.3V Power Supply to SRAM only

NC

No Connection

Unconnected pins

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. AMS = Most Significant Address

 

 

 

 

 

 

 

T2.5 523

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

©2001 Silicon Storage Technology, Inc.

 

 

 

7

 

 

 

S71172-05-000 10/01 523

 

 

 

 

 

 

 

 

 

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF1621 / SST34HF1641

 

 

 

 

 

 

 

 

 

 

 

Data Sheet

TABLE 3: OPERATIONAL MODES SELECTION1

 

 

 

 

 

 

 

 

Mode

BEF#

BES1#

BES22

CIOs3

OE#

WE#

SA

LBS#

UBS#

DQ0-7

 

DQ8-15

Full Standby

VIH

VIH

X

X

X

X

X

X

X

HIGH-Z

 

HIGH-Z

 

 

X

VIL

X

X

X

X

X

X

 

 

 

Output Disable

VIH

VIL

VIH

X

VIH

VIH

X

X

X

HIGH-Z

 

HIGH-Z

 

 

VIL

VIH

VIH

X

X

X

VIH

VIH

 

 

 

 

VIL

VIH

X

X

VIH

VIH

X

X

X

HIGH-Z

 

HIGH-Z

 

 

X

VIL

 

 

 

 

 

 

 

 

 

Flash Read

VIL

VIH

X

X

VIL

VIH

X

X

X

DOUT

 

DOUT

 

 

X

VIL

 

 

 

 

 

 

 

 

 

Flash Write

VIL

VIH

X

X

VIH

VIL

X

X

X

DIN

 

DIN

 

 

X

VIL

 

 

 

 

 

 

 

 

 

Flash Erase

VIL

VIH

X

X

VIH

VIL

X

X

X

X

 

X

 

 

X

VIL

 

 

 

 

 

 

 

 

 

SRAM Read

VIH

VIL

VIH

VIH

VIL

VIH

X

VIL

VIL

DOUT

 

DOUT

 

 

 

 

 

 

 

 

VIH

VIL

HIGH-Z

 

DOUT

 

 

 

 

 

 

 

 

VIL

VIH

DOUT

 

HIGH-Z

 

VIH

VIL

VIH

VIL

VIL

VIH

SA

X

X

DOUT

 

HIGH-Z

SRAM Write

VIH

VIL

VIH

VIH

X

VIL

X

VIL

VIL

DIN

 

DIN

 

 

 

 

 

 

 

 

VIH

VIL

HIGH-Z

 

DIN

 

 

 

 

 

 

 

 

VIL

VIH

DIN

 

HIGH-Z

 

VIH

VIL

VIH

VIL

X

VIL

SA

X

X

DIN

 

HIGH-Z

Product

VIL

VIH

X

X

VIL

VIH

X

X

X

Manufacturer’s ID5

Identification4

 

 

 

 

 

 

 

 

 

Device ID5

 

X

VIL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T3.6 523

1.X can be VIL or VIH, but no other value.

2.Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time

3.SRAM I/O configuration input CIOs; VIH = x16 (word mode), VIL = x8 (byte mode)

4.Software mode only

5.With A19-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,

SST34HF1621/1641 Device ID = 2761H, is read with A0 = 1

©2001 Silicon Storage Technology, Inc.

S71172-05-000 10/01 523

8

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF1621 / SST34HF1641

Data Sheet

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

1st Bus

2nd Bus

3rd Bus

4th Bus

5th Bus

6th Bus

Sequence

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr1

Data2

Addr1

Data2

Addr1

Data2

Addr1

Data2

Addr1

Data2

Addr1

Data2

Word-Program

5555H

AAH

2AAAH

55H

5555H

A0H

WA3

Data

 

 

 

 

Sector-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

SAX4

30H

Block-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

BAX4

50H

Chip-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

 

 

 

 

 

 

 

 

 

 

 

 

 

Software ID Entry5

5555H

AAH

2AAAH

55H

5555H

90H

 

 

 

 

 

 

CFI Query Entry5

5555H

AAH

2AAAH

55H

5555H

98H

 

 

 

 

 

 

Software ID Exit/

5555H

AAH

2AAAH

55H

5555H

F0H

 

 

 

 

 

 

CFI Exit6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T4.4 523

1.Address format A14-A0 (Hex),Address A15-A19 can be VIL or VIH, but no other value, for the Command sequence.

2.Data format DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence.

3.WA = Program Word address

4.SAX for Sector-Erase; uses A19-A11 address lines BAX for Block-Erase; uses A19-A15 address lines

5.The device does not remain in Software Product Identification mode if powered down.

6. With A20-A1 = 0;

SST Manufacturer’s ID = 00BFH, is read with A0 = 0

 

 

SST34HF1621/1641 Device ID = 2761H, is read with A0 = 1.

TABLE 5: CFI QUERY IDENTIFICATION STRING1

Address

Data

Data

 

 

 

10H

0051H

Query Unique ASCII string “QRY”

11H

0052H

 

12H

0059H

 

 

 

 

13H

0001H

Primary OEM command set

14H

0007H

 

 

 

 

15H

0000H

Address for Primary Extended Table

16H

0000H

 

 

 

 

17H

0000H

Alternate OEM command set (00H = none exists)

18H

0000H

 

 

 

 

19H

0000H

Address for Alternate OEM extended Table (00H = none exits)

1AH

0000H

 

 

 

 

T5.0 523

1. Refer to CFI publication 100 for more details.

©2001 Silicon Storage Technology, Inc.

S71172-05-000 10/01 523

9

16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF1621 / SST34HF1641

Data Sheet

TABLE

6: SYSTEM INTERFACE INFORMATION

Address

Data

Data

 

 

 

 

1BH

 

0027H

VDD Min (Program/Erase)

 

 

 

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH

 

0036H

VDD Max (Program/Erase)

 

 

 

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH

 

0000H

VPP Min (00H = no VPP pin)

1EH

 

0000H

VPP Max (00H = no VPP pin)

1FH

 

0004H

Typical time out for Word-Program 2N µs (24 = 16 µs)

20H

 

0000H

Typical time out for Min size buffer program 2N µs (00H = not supported)

21H

 

0004H

Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)

22H

 

0006H

Typical time out for Chip-Erase 2N ms (26 = 64 ms)

23H

 

0001H

Maximum time out for Word-Program 2N times typical (21 x 24 = 32 µs)

24H

 

0000H

Maximum time out for buffer program 2N times typical

25H

 

0001H

Maximum time out for individual Sector/Block-Erase 2N times typical

 

 

 

(21 x 24 = 32 ms)

26H

 

0001H

Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)

 

 

 

T6.0 523

TABLE

7: DEVICE GEOMETRY INFORMATION

 

 

 

Address

Data

Data

 

 

 

 

27H

 

0015H

Device size = 2N Byte (15H = 21; 221 = 2M Bytes)

28H

 

0001H

Flash Device Interface description; 0001H = x16-only asynchronous interface

29H

 

0000H

 

 

 

 

 

2AH

 

0000H

Maximum number of byte in multi-byte write = 2N (00H = not supported)

2BH

 

0000H

 

 

 

 

 

2CH

 

0002H

Number of Erase Sector/Block sizes supported by device

 

 

 

 

2DH

 

00FFH

Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH

 

0003H

y = 1023 + 1 = 1024 sectors (03FF = 1023)

2FH

 

0008H

 

30H

 

0000H

z = 8 x 256 Bytes = 2 KByte/sector (0008H = 8)

 

 

 

 

31H

 

001FH

Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H

 

0000H

y = 31 + 1 = 32 blocks (001F = 31)

33H

 

0000H

 

34H

 

0001H

z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

 

 

 

 

 

 

 

T7.0 523

©2001 Silicon Storage Technology, Inc.

S71172-05-000 10/01 523

10

Loading...
+ 22 hidden pages