Silicon Storage Technology Inc SST32HF401-70-4C-L3K, SST32HF202-90-4E-L3K, SST32HF202-90-4C-L3K, SST32HF202-70-4E-L3K, SST32HF202-70-4C-L3K Datasheet

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

FEATURES:

• MPF + SRAM ComboMemory

 

– SST32HF201: 128K x16 Flash +

64K x16 SRAM

SST32HF202: 128K x16 Flash + 128K x16 SRAM

SST32HF401: 256K x16 Flash +

64K x16 SRAM

SST32HF402: 256K x16 Flash + 128K x16 SRAM

Single 2.7-3.3V Read and Write Operations

Concurrent Operation

Read from or write to SRAM while Erase/Program Flash

Superior Reliability

Endurance: 100,000 Cycles (typical)

Greater than 100 years Data Retention

Low Power Consumption:

Active Current: 15 mA (typical) for Flash or SRAM Read

Standby Current: 20 µA (typical)

Flexible Erase Capability

Uniform 2 KWord sectors

Uniform 32 KWord size blocks

Fast Read Access Times:

Flash: 70 and 90 ns

SRAM: 70 and 90 ns

Latched Address and Data for Flash

Flash Fast Erase and Word-Program:

Sector-Erase Time: 18 ms (typical)

Block-Erase Time: 18 ms (typical)

Chip-Erase Time: 70 ms (typical)

Word-Program Time: 14 µs (typical)

Chip Rewrite Time: SST32HF201/202: 2 seconds (typical) SST32HF401/402: 4 seconds (typical)

Flash Automatic Erase and Program Timing

Internal VPP Generation

Flash End-of-Write Detection

Toggle Bit

Data# Polling

CMOS I/O Compatibility

JEDEC Standard Command Set

Conforms to Flash pinout

Package Available

48-ball LFBGA (6mm x 8mm)

PRODUCT DESCRIPTION

The SST32HF20x/40x ComboMemory devices integrate a 128K x16 or 256K x16 CMOS flash memory bank with a 64K x16 or 128K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST’s proprietary, high performance SuperFlash technology.

Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 14 µsec. The entire flash memory bank can be erased and programmed word-by-word in typically 2 seconds for the SST32HF201/202 and 4 seconds for the SST32HF401/ 402, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST32HF20x/40x devices contain on-chip hardware and software data protection schemes.The SST32HF20x/40x devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST32HF20x/40x devices consist of two independent memory banks with respective bank enable signals. The Flash and SRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the

SRAM bank. The flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration.

The SST32HF20x/40x provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write.

The SST32HF20x/40x devices are suited for applications that use both flash memory and SRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HF20x/40x devices significantly improve performance and reliability, while lowering power

©2001 Silicon Storage Technology, Inc.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

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MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.

 

 

These specifications are subject to change without notice.

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

consumption, when compared with multiple chip solutions. The SST32HF20x/40x inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

Device Operation

The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. When BES# is low, the SRAM Bank is activated for Read and Write operation. When BEF# is low the flash bank is activated for Read, Program or Erase operation. BES# and BEF# cannot be at low level at the same time. If BES# and BEF# are both asserted to low level bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by SRAM Bank and flash bank which minimizes power consumption and loading. The device goes into standby when both bank enables are high.

SRAM Operation

With BES# low and BEF# high, the SST32HF201/401 operate as 64K x16 CMOS SRAM, and the SST32HF202/ 402 operates as 128K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SST32HF201/401 SRAM is mapped into the first 64 KWord address space of the device, and the SST32HF202/402 SRAM is mapped into the first 128 KWord address space. When BES# and BEF# are high, both memory banks are deselected and the device enters standby mode. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 3 for SRAM read and write data byte control modes of operation.

Preliminary Specifications

control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 2 for the Read cycle timing diagram.

SRAM Write

The SRAM Write operation of the SST32HF20x/40x is controlled by WE# and BES#, both have to be low for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The write time is measured from the last falling edge to the first rising edge of BES# or WE#. See Figures 3 and 4 for the Write cycle timing diagrams.

Flash Operation

With BEF# active, the SST32HF201/202 operate as 128K x16 flash memory and the SST32HF401/402 operates as 256K x16 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and during the internally timed Erase and Program operations.

Flash Read

The Read operation of the SST32HF20x/40x devices is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to Figure 5 for further details.

Flash Erase/Program Operation

SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST32HF20x/40x. SDP commands are loaded to the flash memory bank using standard microprocessor write sequences. A command is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the falling edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first.

SRAM Read

The SRAM Read operation of the SST32HF20x/40x is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. BES# is used for SRAM bank selection. OE# is the output

Flash Word-Program Operation

The flash memory bank of the SST32HF20x/40x devices is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program

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Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

operation consists of three steps. The first step is the threebyte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 6 and 7 for WE# and BEF# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored.

Flash Sector/Block-Erase Operation

The Flash Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. The SST32HF20x/40x offer both SectorErase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A16-A11, for SST32HF201/202, and A17-A11, for SST32HF401/402, are used to determine the sector address. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The address lines A16-A15, for SST32HF201/202, and A17- A15, for SST32HF401/402, are used to determine the block address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored.

Flash Chip-Erase Operation

The SST32HF20x/40x provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 20 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST32HF20x/40x provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Flash Data# Polling (DQ7)

When the SST32HF20x/40x flash memory banks are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles, after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sectoror Block-Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 18 for a flowchart.

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Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Flash Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating ‘1’s and ‘0’s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the toggling will stop. The flash memory bank is then ready for the next operation. The Toggle Bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sectoror Bank-Erase, the Toggle Bit is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 9 for Toggle Bit timing diagram and Figure 18 for a flowchart.

Flash Memory Data Protection

The SST32HF20x/40x flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down.

Flash Software Data Protection (SDP)

The SST32HF20x/40x provide the JEDEC approved software data protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST32HF20x/40x devices are shipped with the software data protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid SDP commands will abort the device to the read mode, within Read Cycle Time (TRC).

Concurrent Read and Write Operations

The SST32HF20x/40x provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the Flash. This allows data alteration code to be executed from SRAM, while altering the data in Flash. The following table lists all valid states.

 

Preliminary Specifications

CONCURRENT READ/WRITE STATE TABLE

 

 

Flash

SRAM

Program/Erase

Read

Program/Erase

Write

The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress.

Product Identification

The Product Identification mode identifies the devices as the SST32HF20x/40x and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers, cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device.

Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 3 and 4 for software operation, Figure 13 for the software ID entry and Read timing diagram, and Figure 19 for the ID entry command sequence flowchart.

TABLE 1: PRODUCT IDENTIFICATION

 

Address

Data

 

 

 

Manufacturer’s ID

0000H

00BFH

 

 

 

Device ID

 

 

SST32HF201/202

0001H

2789H

SST32HF401/402

0001H

2780H

 

 

 

T1.0 557

Product Identification Mode Exit/Reset

In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software-reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 14 for timing waveform and Figure 19 for a flowchart.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the

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Silicon Storage Technology Inc SST32HF401-70-4C-L3K, SST32HF202-90-4E-L3K, SST32HF202-90-4C-L3K, SST32HF202-70-4E-L3K, SST32HF202-70-4C-L3K Datasheet

Multi-Purpose Flash (MPF) + SRAM ComboMemory SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin.

FUNCTIONAL BLOCK DIAGRAM

Address Buffers

 

 

SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UBS#

 

 

 

 

 

 

 

 

LBS#

 

 

 

 

 

 

 

AMS-A0

BES#

 

Control Logic

 

BEF#

 

 

 

 

OE#

 

 

 

 

 

 

WE#

 

 

 

 

 

Address Buffers

 

 

SuperFlash

& Latches

 

 

Memory

 

 

 

 

TOP VIEW (balls facing down)

SST32HF201/202

6

 

 

 

 

USB# DQ15 VSS

 

6

A13

A12

A14

A15

A16

 

 

5

 

 

 

DQ7 DQ14 DQ13 DQ6

 

5

A9

A8

A10

A11

 

 

4

 

 

 

 

 

 

DQ4

 

4

WE#

NC

LBS#

NC

DQ5 DQ12 VDD

 

 

3

 

 

 

DQ2 DQ10 DQ11 DQ3

 

3

BES#

NC

NC

NC

 

 

2

 

 

 

 

 

 

DQ1

F01a.0

2

A7

NC

A6

A5

DQ0

DQ8

DQ9

 

 

 

1

 

 

 

 

 

 

VSS

ILL

1

A3

A4

A2

A1

A0

BEF#

OE#

 

 

 

 

 

 

 

 

 

557

 

A

B

C

D

E

F

G

H

 

 

FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LFBGA

I/O Buffers

 

 

DQ15 - DQ8

 

 

 

 

 

DQ7 - DQ0

 

 

 

557 ILL B1.0

 

TOP VIEW

(balls facing down)

 

 

SST32HF401/402

 

 

 

A13

A12

A14

A15

A16

USB# DQ15 VSS

 

A9

A8

A10

A11

DQ7 DQ14 DQ13 DQ6

 

WE#

NC

LBS#

NC

DQ5 DQ12 VDD DQ4

 

BES#

NC

NC

NC

DQ2 DQ10 DQ11 DQ3

F01b.0ILL

A7

A17

A6

A5

DQ0

DQ8

DQ9

DQ1

 

A3

A4

A2

A1

A0

BEF#

OE#

VSS

557

 

 

 

 

 

 

 

 

A

B

C

D

E

F

G

H

 

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Multi-Purpose Flash (MPF) + SRAM ComboMemory

 

 

 

 

 

 

 

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Preliminary Specifications

 

TABLE

2: PIN DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Pin Name

 

 

 

 

Functions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AMS1-A0

 

Address Inputs

 

 

 

 

To provide flash addresses, A16-A0 for 2M and A17-A0 for 4M.

 

 

 

 

 

 

 

 

 

 

To provide SRAM addresses, A15-A0 for 1M and A16-A0 for 2M.

 

DQ15-DQ0

Data Input/output

 

 

 

 

To output data during Read cycles and receive input data during Write cycles.

 

 

 

 

 

 

 

 

 

 

Data is internally latched during a flash Erase/Program cycle.

 

 

 

 

 

 

 

 

 

 

The outputs are in tri-state when OE# or BES# and BEF# are high.

 

BES#

 

SRAM Memory Bank Enable

 

To activate the SRAM memory bank when BES# is low.

 

BEF#

 

Flash Memory Bank Enable

 

To activate the Flash memory bank when BEF# is low.

 

OE#

 

Output Enable

 

 

 

 

To gate the data output buffers.

 

 

 

WE#

 

Write Enable

 

 

 

 

To control the Write operations.

 

 

 

VDD

 

Power Supply

 

 

 

 

2.7-3.3V power supply

 

 

 

VSS

 

Ground

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UBS#

 

Upper Byte Control (SRAM)

 

To enable DQ15-DQ8

 

 

 

 

LBS#

 

Lower Byte Control (SRAM)

 

To enable DQ7-DQ0

 

 

 

 

NC

 

No Connection

 

 

 

 

Unconnected Pins

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. AMS = Most significant address

 

 

 

 

 

 

 

 

 

T2.0 557

 

 

 

 

 

 

 

 

 

 

 

 

TABLE

3: OPERATION MODES SELECTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mode

 

 

BES#1

 

BEF#1

 

OE#

WE#

UBS#

LBS#

 

DQ15 to DQ8

DQ7 to DQ0

Address

 

Not Allowed

 

VIL

 

VIL

 

X2

 

X

X

X

 

X

X

X

 

Flash

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

 

VIH

 

VIL

 

VIL

 

VIH

X

X

 

DOUT

DOUT

AIN

 

Program

 

VIH

 

VIL

 

VIH

 

VIL

X

X

 

DIN

DIN

AIN

 

Erase

 

 

X

 

VIL

 

VIH

 

VIL

X

X

 

X

X

Sector or Block address,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XXH for Chip-Erase

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

 

VIL

 

VIH

 

VIL

 

VIH

VIL

VIL

 

DOUT

DOUT

AIN

 

 

 

 

VIL

 

VIH

 

VIL

 

VIH

VIL

VIH

 

DOUT

High Z

AIN

 

 

 

 

VIL

 

VIH

 

VIL

 

VIH

VIH

VIL

 

High Z

DOUT

AIN

 

Write

 

 

VIL

 

VIH

 

X

 

VIL

VIL

VIL

 

DIN

DIN

AIN

 

 

 

 

VIL

 

VIH

 

X

 

VIL

VIL

VIH

 

DIN

High Z

AIN

 

 

 

 

VIL

 

VIH

 

X

 

VIL

VIH

VIL

 

High Z

DIN

AIN

 

Standby

 

 

VIHC

 

VIHC

 

X

 

X

X

X

 

High Z

High Z

X

 

Flash Write Inhibit

X

 

X

 

VIL

 

X

X

X

 

High Z / DOUT

High Z / DOUT

X

 

 

 

 

X

 

X

 

X

 

VIH

X

X

 

High Z / DOUT

High Z / DOUT

X

 

 

 

 

X

 

VIH

 

X

 

X

X

X

 

High Z / DOUT

High Z / DOUT

X

 

Output Disable

VIH

 

VIL

 

VIH

 

VIH

X

X

 

High Z

High Z

X

 

 

 

 

VIL

 

VIH

 

X

 

X

VIH

VIH

 

High Z

High Z

X

 

 

 

 

VIL

 

VIH

 

VIH

 

VIH

X

X

 

High Z

High Z

X

 

Product Identification

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Software Mode

VIH

 

VIL

 

VIL

 

VIH

X

X

 

Manufacturer’s ID (00BFH)

AMSF4-A1=VIL, A0=VIH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device ID3

(See Table 4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T3.2 557

 

1.Do not apply BES#=VIL and BEF#=VIL at the same time

2.X can be VIL or VIH, but no other value.

3.Device ID for: SST32HF201/202 = 2789H and SST32HF401/402 = 2780H

4.AMS = Most significant flash address

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S71209-00-000 9/01 557

6

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

1st Bus

2nd Bus

3rd Bus

4th Bus

5th Bus

6th Bus

Sequence

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Word-Program

5555H

AAH

2AAAH

55H

5555H

A0H

WA2

Data

 

 

 

 

Sector-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

SAX3

30H

Block-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

BAX3

50H

Chip-Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

 

 

 

 

 

 

 

 

 

 

 

 

 

Software ID Entry4,5

5555H

AAH

2AAAH

55H

5555H

90H

 

 

 

 

 

 

Software ID Exit

XXH

F0H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Software ID Exit

5555H

AAH

2AAAH

55H

5555H

F0H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T4.1 557

1.Address format A14-A0 (Hex),Address A15 can be VIL or VIH, but no other value, for the Command sequence.

2.WA = Program Word address

3.SAX for Sector-Erase; uses AMS-A11 address lines BAX for Block-Erase; uses AMS-A15 address lines AMS = Most significant address

AMS = A16 for SST32HF201/202 and A17 for SST32HF401/402

4.The device does not remain in Software Product ID mode if powered down.

5.With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,

SST32HF201/202 Device ID = 2789H, is read with A0 = 1,

SST32HF401/402 Device ID = 2780H, is read with A0 = 1.

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range

Ambient Temp

VDD

Commercial

0°C to +70°C

2.7-3.3V

Extended

-20°C to +85°C

2.7-3.3V

 

 

 

AC CONDITIONS OF TEST

. . . . . . . . . . . . . . .Input Rise/Fall Time

5 ns

Output Load . . . . . . . . . . . . . . . . . . . . .

CL = 30 pF

See Figures 15 and 16

 

 

 

©2001 Silicon Storage Technology, Inc.

S71209-00-000 9/01 557

7

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402

Preliminary Specifications

TABLE

5: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V)

 

 

 

 

 

 

 

 

Limits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

 

Parameter

 

Min

 

Max

Units

Test Conditions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDD

 

 

Power Supply Current

 

 

 

 

 

Address input=VIL/VIH, at f=1/TRC Min,

 

 

 

 

 

 

 

 

 

 

VDD=VDD Max, all DQs open

 

 

 

 

Read

 

 

 

20

mA

OE#=VIL, WE#=VIH

 

 

 

 

Flash

 

 

 

BEF#=VIL, BES#=VIH

 

 

 

 

SRAM

 

 

 

20

mA

BEF#=VIH, BES#=VIL

 

 

 

 

Concurrent Operation

 

 

 

45

mA

BEF#=VIH, BES#=VIL

 

 

 

 

Write

 

 

 

 

 

WE#=VIL

 

 

 

 

Flash

 

 

 

25

mA

BEF#=VIL, BES#=VIH, OE#=VIH

 

 

 

 

SRAM

 

 

 

20

mA

BEF#=VIH, BES#=VIL

 

ISB

 

 

Standby VDD Current

 

 

 

30

µA

VDD=VDD Max, BEF#=BES#=VIHC

 

ILI

 

 

Input Leakage Current

 

 

 

1

µA

VIN=GND to VDD, VDD=VDD Max

 

ILO

 

 

Output Leakage Current

 

 

 

1

µA

VOUT=GND to VDD, VDD=VDD Max

 

VIL

 

 

Input Low Voltage

 

 

 

0.8

V

VDD=VDD Min

 

VIH

 

 

Input High Voltage

 

0.7 VDD

 

 

V

VDD=VDD Max

 

VIHC

 

 

Input High Voltage (CMOS)

 

VDD-0.3

 

 

V

VDD=VDD Max

 

VOLF

 

 

Flash Output Low Voltage

 

 

 

0.2

V

IOL=100 µA, VDD=VDD Min

 

VOHF

 

 

Flash Output High Voltage

 

VDD-0.2

 

 

V

IOH=-100 µA, VDD=VDD Min

 

VOLS

 

 

Output Low Voltage

 

 

 

0.4

V

IOL=1 mA, VDD=VDD Min

 

VOHS

 

 

Output High Voltage

 

2.2

 

 

V

IOH=-500 µA, VDD=VDD Min

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T5.1 557

TABLE

6: RECOMMENDED SYSTEM POWER-UP TIMINGS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

 

 

Parameter

 

 

 

 

 

Minimum

 

Units

 

 

 

 

 

 

 

 

 

 

 

TPU-READ1

 

Power-up to Read Operation

 

 

 

 

 

100

 

µs

TPU-WRITE1

 

Power-up to Program/Erase Operation

 

 

100

 

µs

 

 

 

 

 

 

 

 

 

 

 

 

 

T6.0 557

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter

Description

Test Condition

Maximum

 

 

 

 

CI/O1

I/O Pin Capacitance

VI/O = 0V

24 pF

CIN1

Input Capacitance

VIN = 0V

12 pF

T7.0 557

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE

8: FLASH RELIABILITY CHARACTERISTICS

 

 

 

Symbol

 

Parameter

Minimum Specification

Units

Test Method

 

 

 

 

 

 

NEND1

 

Endurance

10,000

Cycles

JEDEC Standard A117

TDR1

 

Data Retention

100

Years

JEDEC Standard A103

ILTH1

 

Latch Up

100 + IDD

mA

JEDEC Standard 78

T8.0 557

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

©2001 Silicon Storage Technology, Inc.

S71209-00-000 9/01 557

8

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