Silicon Storage Technology Inc SST29VE010-90-4I-WN, SST29VE010-90-4I-WH, SST29VE010-150-4C-WH, SST29VE010-150-4C-UN, SST29VE010-150-4C-UH Datasheet

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1 Mbit (128K x8) Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Data Sheet

FEATURES:

Single Voltage Read and Write Operations

5.0V-only for SST29EE010

3.0-3.6V for SST29LE010

2.7-3.6V for SST29VE010

Superior Reliability

Endurance: 100,000 Cycles (typical)

Greater than 100 years Data Retention

Low Power Consumption

Active Current: 20 mA (typical) for 5V and 10 mA (typical) for 3.0/2.7V

Standby Current: 10 µA (typical)

Fast Page-Write Operation

128 Bytes per Page, 1024 Pages

Page-Write Cycle: 5 ms (typical)

Complete Memory Rewrite: 5 sec (typical)

Effective Byte-Write Cycle Time: 39 µs (typical)

Fast Read Access Time

5.0V-only operation: 70 and 90 ns

3.0-3.6V operation: 150 and 200 ns

2.7-3.6V operation: 200 and 250 ns

Latched Address and Data

Automatic Write Timing

Internal VPP Generation

End of Write Detection

Toggle Bit

Data# Polling

Hardware and Software Data Protection

Product Identification can be accessed via Software Operation

TTL I/O Compatibility

JEDEC Standard

Flash EEPROM Pinouts and command sets

Packages Available

32-lead PLCC

32-lead TSOP (8mm x 14mm, 8mm x 20mm)

32-pin PDIP

PRODUCT DESCRIPTION

The SST29EE/LE/VE010 are 128K x8 CMOS Page-Write EEPROMs manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29EE/LE/VE010 write with a single power supply. Internal Erase/Program is transparent to the user. The SST29EE/LE/VE010 conform to JEDEC standard pinouts for byte-wide memories.

Featuring high performance Page-Write, the SST29EE/LE/ VE010 provide a typical Byte-Write time of 39 µsec. The entire memory, i.e., 128 KBytes, can be written page-by- page in as little as 5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a Write cycle. To protect against inadvertent write, the SST29EE/LE/VE010 have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST29EE/LE/VE010 are offered with a guaranteed PageWrite endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST29EE/LE/VE010 are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST29EE/LE/VE010 significantly improve performance and reliability, while lowering power consumption. The SST29EE/LE/VE010 improve flexibility while lowering the cost for program, data, and configuration storage applications.

To meet high density, surface mount requirements, the SST29EE/LE/VE010 are offered in 32-lead PLCC and 32lead TSOP packages. A 600-mil, 32-pin PDIP package is also available. See Figures 1, 2, and 3 for pinouts.

Device Operation

The SST Page-Mode EEPROM offers in-circuit electrical write capability. The SST29EE/LE/VE010 does not require separate Erase and Program operations. The internally timed write cycle executes both erase and program transparently to the user. The SST29EE/LE/VE010 have industry standard optional Software Data Protection, which SST recommends always to be enabled. The SST29EE/LE/ VE010 are compatible with industry standard EEPROM pinouts and functionality.

©2001 Silicon Storage Technology, Inc.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

S71061-07-000 6/01

304

SSF is a trademark of Silicon Storage Technology, Inc.

 

 

These specifications are subject to change without notice.

1 Mbit Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Read

The Read operations of the SST29EE/LE/VE010 are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the read cycle timing diagram for further details (Figure 4).

Write

The Page-Write to the SST29EE/LE/VE010 should always use the JEDEC Standard Software Data Protection (SDP) three-byte command sequence. The SST29EE/LE/VE010 contain the optional JEDEC approved Software Data Protection scheme. SST recommends that SDP always be enabled, thus, the description of the Write operations will be given using the SDP enabled format. The three-byte SDP Enable and SDP Write commands are identical; therefore, any time a SDP Write command is issued, Software Data Protection is automatically assured. The first time the three-byte SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same command bypasses the data protection for the page being written. At the end of the desired Page-Write, the entire device remains protected. For additional descriptions, please see the application notes, The Proper Use of JEDEC Standard Software Data Protection and Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories.

The Write operation consists of three steps. Step 1 is the three-byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the SST29EE/LE/VE010. Steps 1 and 2 use the same timing for both operations. Step 3 is an internally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP three-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The internal write cycle is initiated by the TBLCO timer after the rising edge of WE# or CE#, whichever occurs first. The Write cycle, once initiated, will continue to completion, typically within 5 ms. See Figures 5 and 6 for WE# and CE# controlled Page-Write cycle timing diagrams and Figures 15 and 17 for flowcharts.

The Write operation has three functional cycles: the Software Data Protection load sequence, the page load cycle, and the internal write cycle. The Software Data Protection

Data Sheet

consists of a specific three-byte load sequence that allows writing to the selected page and will leave the SST29EE/ LE/VE010 protected at the end of the Page-Write. The page load cycle consists of loading 1 to 128 bytes of data into the page buffer. The internal write cycle consists of the TBLCO time-out and the write timer operation. During the Write operation, the only valid reads are Data# Polling and Toggle Bit.

The Page-Write operation allows the loading of up to 128 bytes of data into the page buffer of the SST29EE/LE/ VE010 before the initiation of the internal write cycle. During the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the Page-Write feature of SST29EE/LE/VE010 allow the entire memory to be written in as little as 5 seconds. During the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page-Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A7 through A16. Any byte not loaded with user data will be written to FFH.

See Figures 5 and 6 for the Page-Write cycle timing diagrams. If after the completion of the three-byte SDP load sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 100 µs, the SST29EE/LE/VE010 will stay in the page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 µs (TBLCO) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. The page load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 µs. The page to be loaded is determined by the page address of the last byte loaded.

Software Chip-Erase

The SST29EE/LE/VE010 provide a Chip-Erase operation, which allows the user to simultaneously clear the entire memory array to the “1” state. This is useful when the entire device must be quickly erased.

The Software Chip-Erase operation is initiated by using a specific six-byte load sequence. After the load sequence, the device enters into an internally timed cycle similar to the Write cycle. During the Erase operation, the only valid read is Toggle Bit. See Table 4 for the load sequence, Figure 10 for timing diagram, and Figure 19 for the flowchart.

©2001 Silicon Storage Technology, Inc.

S71061-07-000 6/01 304

2

1 Mbit Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Data Sheet

Write Operation Status Detection

The SST29EE/LE/VE010 provide two software means to detect the completion of a Write cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the internal write cycle.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST29EE/LE/VE010 are in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the byte-load cycle will receive the complement of the true data. Once the Write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart.

Toggle Bit (DQ6)

During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart. The initial read of the Toggle Bit will typically be a “1”.

Data Protection

The SST29EE/LE/VE010 provide both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

Software Data Protection (SDP)

The SST29EE/LE/VE010 provide the JEDEC approved optional Software Data Protection scheme for all data alteration operations, i.e., Write and Chip-Erase. With this scheme, any Write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. The three byte-load sequence is used to initiate the Write cycle, providing optimal protection from inadvertent write operations, e.g., during the system powerup or power-down. The SST29EE/LE/VE010 are shipped with the Software Data Protection disabled.

The software protection scheme can be enabled by applying a three-byte sequence to the device, during a pageload cycle (Figures 5 and 6). The device will then be automatically set into the data protect mode. Any subsequent Write operation will require the preceding three-byte sequence. See Table 4 for the specific software command codes and Figures 5 and 6 for the timing diagrams. To set the device into the unprotected mode, a six-byte sequence is required. See Table 4 for the specific codes and Figure 9 for the timing diagram. If a write is attempted while SDP is enabled the device will be in a non-accessible state for ~300 µs. SST recommends Software Data Protection always be enabled. See Figure 17 for flowcharts.

The SST29EE/LE/VE010 Software Data Protection is a global command, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). Therefore using SDP for a single Page-Write will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled or disabled.

Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SST strongly recommends that Software Data Protection (SDP) always be enabled. The SST29EE/LE/VE010 should be programmed using the SDP command sequence. SST recommends the SDP Disable Command Sequence not be issued to the device prior to writing.

Please refer to the following Application Notes for more information on using SDP:

Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories

The Proper Use of JEDEC Standard Software Data Protection

©2001 Silicon Storage Technology, Inc.

S71061-07-000 6/01 304

3

Silicon Storage Technology Inc SST29VE010-90-4I-WN, SST29VE010-90-4I-WH, SST29VE010-150-4C-WH, SST29VE010-150-4C-UN, SST29VE010-150-4C-UH Datasheet

1 Mbit Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Product Identification

The product identification mode identifies the device as the SST29EE/LE/VE010 and manufacturer as SST. This mode is accessed via software. For details, see Table 4, Figure 11 for the software ID entry and read timing diagram and Figure 18, for the ID entry command sequence flowchart.

TABLE 1: PRODUCT IDENTIFICATION

 

Address

Data

 

 

 

Manufacturer’s ID

0000H

BFH

 

 

 

Device ID

 

 

SST29EE010

0001H

07H

SST29LE010

0001H

08H

SST29VE010

0001H

08H

 

 

 

T1.3 304

Data Sheet

Product Identification Mode Exit

In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the Read operation. The Reset operation may also be used to reset the device to the Read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. See Table 4 for software command codes, Figure 12 for timing waveform, and Figure 18 for a flowchart.

FUNCTIONAL BLOCK DIAGRAM

 

 

 

SuperFlash

X-Decoder

 

 

 

 

Memory

 

 

 

 

 

 

 

 

 

 

A16 - A0 Address Buffer & Latches

Y-Decoder and Page Latches

CE#

 

 

 

 

 

 

 

 

 

 

Control Logic

 

 

 

 

 

OE#

 

 

 

 

 

I/O Buffers and Data Latches

 

 

 

 

WE#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ7 - DQ0

304 ILL B1.1

 

 

A12

 

A15

 

A16

 

NC

V

 

WE#

NC

 

 

 

 

 

 

 

 

 

 

 

DD

 

 

 

 

 

 

 

4

3

2

1

 

32

31

30

 

 

A7

5

 

 

 

 

 

 

 

 

 

 

 

 

29

A14

A6

6

 

 

 

 

 

 

 

 

 

 

 

 

28

A13

A5

7

 

 

 

 

 

 

 

 

 

 

 

 

27

A8

A4

8

 

 

32-lead PLCC

26

A9

A3

9

 

 

25

A11

 

 

 

 

Top View

 

 

 

A2

10

 

 

 

 

 

 

 

24

OE#

 

 

 

 

 

 

 

 

 

 

 

 

A1

11

 

 

 

 

 

 

 

 

 

 

 

 

23

A10

A0

12

 

 

 

 

 

 

 

 

 

 

 

 

22

CE#

DQ0

13

 

 

 

 

 

 

 

 

 

 

 

 

21

DQ7

 

14

15

16

17

18

19

 

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ1

DQ2

SS

DQ3

DQ4

DQ5

DQ6

V

304 ILL F02.3

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

©2001 Silicon Storage Technology, Inc.

S71061-07-000 6/01 304

4

1 Mbit Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Data Sheet

A11 1

A9 2

A8 3

A13 4

A14 5 NC 6 WE# 7

VDD 8 NC 9

A16 10

A15 11

A12 12

A7 13

A6 14

A5 15

A4 16

 

32

 

 

OE#

 

31

 

 

A10

 

30

 

 

CE#

 

29

 

 

DQ7

Standard Pinout

28

 

 

DQ6

27

 

 

DQ5

Top View

26

 

 

DQ4

25

 

 

DQ3

Die Up

24

 

 

VSS

 

 

23

 

 

DQ2

 

22

 

 

DQ1

 

21

 

 

DQ0

 

20

 

 

A0

 

19

 

 

A1

 

18

 

 

A2

 

17

 

 

A3

 

 

 

 

 

304 ILL F01.2

FIGURE

2: PIN ASSIGNMENTS FOR 32-LEAD TSOP

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

1

 

32

VDD

 

 

 

A16

2

 

31

WE#

 

 

 

A15

3

 

30

NC

 

 

 

A12

4

 

29

A14

 

 

 

A7

5

32-pin

28

A13

 

 

 

A6

6

27

A8

 

 

 

 

 

 

 

A5

7

PDIP

26

A9

 

 

 

A4

8

Top View

25

A11

 

 

 

A3

9

 

24

OE#

 

 

 

A2

10

 

23

A10

 

 

 

A1

11

 

22

CE#

 

 

 

A0

12

 

21

DQ7

 

 

 

DQ0

13

 

20

DQ6

 

 

 

DQ1

14

 

19

DQ5

 

 

 

DQ2

15

 

18

DQ4

 

 

 

VSS

16

 

17

DQ3

 

 

 

 

 

 

304 ILL F19.0

 

 

 

 

 

 

 

FIGURE

3: PIN ASSIGNMENTS FOR 32-PIN PDIP

 

 

 

TABLE 2: PIN DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Pin Name

Functions

 

 

 

 

 

 

 

 

A16-A7

 

Row Address Inputs

To provide memory addresses. Row addresses define a page for a Write cycle.

A6-A0

 

Column Address Inputs

Column Addresses are toggled to load page data

DQ7-DQ0

 

Data Input/output

To output data during Read cycles and receive input data during Write cycles.

 

 

 

Data is internally latched during a Write cycle.

 

 

 

The outputs are in tri-state when OE# or CE# is high.

CE#

 

Chip Enable

To activate the device when CE# is low.

OE#

 

Output Enable

To gate the data output buffers.

 

WE#

 

Write Enable

To control the Write operations.

 

VDD

 

Power Supply

To provide:

5.0V supply (±10%) for SST29EE010

 

 

 

 

3.0V supply (3.0-3.6V) for SST29LE010

 

 

 

 

2.7V supply (2.7-3.6V) for SST29VE010

VSS

 

Ground

 

 

 

 

 

NC

 

No Connection

Unconnected pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T2.1 304

 

 

 

 

 

 

 

©2001 Silicon Storage Technology, Inc.

 

 

5

 

S71061-07-000 6/01 304

 

 

 

 

 

 

 

1 Mbit Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Data Sheet

TABLE 3: OPERATION MODES SELECTION

Mode

CE#

OE#

WE#

DQ

Address

 

 

 

 

 

 

Read

VIL

VIL

VIH

DOUT

AIN

Page-Write

VIL

VIH

VIL

DIN

AIN

Standby

VIH

X1

X

High Z

X

Write Inhibit

X

VIL

X

High Z/ DOUT

X

 

X

X

VIH

High Z/ DOUT

X

Software Chip-Erase

VIL

VIH

VIL

DIN

AIN, See Table 4

Product Identification

 

 

 

 

 

Software Mode

VIL

VIH

VIL

Manufacturer’s ID (BFH)

See Table 4

 

 

 

 

Device ID2

 

SDP Enable Mode

VIL

VIH

VIL

 

See Table 4

SDP Disable Mode

VIL

VIH

VIL

 

See Table 4

T3.3 304

1.X can be VIL or VIH, but no other value.

2.Device ID = 07H for SST29EE010 and 08H for SST29LE/VE010

TABLE 4: SOFTWARE COMMAND SEQUENCE

 

1st Bus

2nd Bus

3rd Bus

4th Bus

5th Bus

6th Bus

Command

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

Write Cycle

 

 

 

 

 

 

 

 

 

 

 

 

Sequence

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Addr1

Data

Software

5555H

AAH

2AAAH

55H

5555H

A0H

Addr2

Data

 

 

 

 

Data Protect Enable

 

 

 

 

 

 

 

 

 

 

 

 

& Page-Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Software

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

20H

Data Protect Disable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Software Chip-Erase3

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

Software ID Entry4,5

5555H

AAH

2AAAH

55H

5555H

90H

 

 

 

 

 

 

Software ID Exit

5555H

AAH

2AAAH

55H

5555H

F0H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Alternate

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

60H

Software ID Entry6

 

 

 

 

 

 

 

 

 

 

 

 

1. Address format A14-A0 (Hex),

Addresses A15 and A16 can be VIL or VIH, but no other value.”

 

 

 

T4.3 304

 

 

 

 

2.Page-Write consists of loading up to 128 Bytes (A6-A0)

3.The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if you require this function for an industrial temperature part.

4.The device does not remain in Software Product ID Mode if powered down.

5.

With A14-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0,

 

SST29EE010 Device ID = 07H, is read with A0 = 1

 

SST29LE/VE010 Device ID = 08H, is read with A0 = 1

6.

Alternate six-byte Software Product ID Command Code

Note: This product supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code sequence. For new designs, SST recommends that the three-byte command code sequence be used.

©2001 Silicon Storage Technology, Inc.

S71061-07-000 6/01 304

6

1 Mbit Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Data Sheet

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-0.5V to VDD + 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .

-1.0V to VDD + 1.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . -0.5V to 14.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . 240°C

Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . 100 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST29EE010

Range

 

Ambient Temp

 

VDD

 

Commercial

 

0°C to +70°C

 

5.0V±10%

 

Industrial

 

-40°C to +85°C

 

5.0V±10%

 

 

 

 

 

 

OPERATING RANGE FOR SST29LE010

 

 

 

 

 

 

Range

 

Ambient Temp

 

VDD

 

Commercial

 

0°C to +70°C

 

3.0-3.6V

 

Industrial

 

-40°C to +85°C

 

3.0-3.6V

 

 

 

 

 

 

OPERATING RANGE FOR SST29VE010

 

 

 

 

 

 

Range

 

Ambient Temp

 

VDD

 

Commercial

 

0°C to +70°C

 

2.7-3.6V

 

Industrial

 

-40°C to +85°C

 

2.7-3.6V

 

 

 

 

 

 

AC CONDITIONS OF TEST

 

 

 

 

 

 

Input Rise/Fall Time

. . . . . . . . . . . . . . 10 ns

 

 

Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF

See Figures 13 and 14

©2001 Silicon Storage Technology, Inc.

S71061-07-000 6/01 304

7

1 Mbit Page-Mode EEPROM

SST29EE010 / SST29LE010 / SST29VE010

Data Sheet

TABLE

5: DC OPERATING CHARACTERISTICS VDD = 5.0V±10% FOR SST29EE010

 

 

 

 

Limits

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

Min

 

Max

Units

Test Conditions

 

 

 

 

 

 

 

 

IDD

 

Power Supply Current

 

 

 

 

Address input=VIL/VIH, at f=1/TRC Min,

 

 

 

 

 

 

 

VDD=VDD Max

 

 

Read

 

 

30

mA

CE#=OE#=VIL, WE#=VIH, all I/Os open

 

 

Write

 

 

50

mA

CE#=WE#=VIL, OE#=VIH, VDD=VDD Max

ISB1

 

Standby VDD Current

 

 

3

mA

CE#=OE#=WE#=VIH, VDD=VDD Max

 

 

(TTL input)

 

 

 

 

 

ISB2

 

Standby VDD Current

 

 

50

µA

CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max

 

 

(CMOS input)

 

 

 

 

 

 

 

 

 

 

 

 

 

ILI

 

Input Leakage Current

 

 

1

µA

VIN =GND to VDD, VDD=VDD Max

ILO

 

Output Leakage Current

 

 

10

µA

VOUT =GND to VDD, VDD=VDD Max

VIL

 

Input Low Voltage

 

 

0.8

V

VDD=VDD Min

VIH

 

Input High Voltage

2.0

 

 

V

VDD=VDD Max

VOL

 

Output Low Voltage

 

 

0.4

V

IOL=2.1 mA, VDD=VDD Min

VOH

 

Output High Voltage

2.4

 

 

V

IOH=-400 µA, VDD=VDD Min

 

 

 

 

 

 

 

T5.3 304

TABLE

6: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST29LE010 AND 2.7-3.0V FOR SST29VE010

 

 

 

 

 

 

 

 

 

 

 

Limits

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

Min

 

Max

Units

Test Conditions

 

 

 

 

 

 

 

 

IDD

 

Power Supply Current

 

 

 

 

Address input=VIL/VIH, at f=1/TRC Min,

 

 

 

 

 

 

 

VDD=VDD Max

 

 

Read

 

 

12

mA

CE#=OE#=VIL, WE#=VIH, all I/Os open

 

 

Write

 

 

15

mA

CE#=WE#=VIL, OE#=VIH, VDD=VDD Max

ISB1

 

Standby VDD Current

 

 

1

mA

CE#=OE#=WE#=VIH, VDD=VDD Max

 

 

(TTL input)

 

 

 

 

 

ISB2

 

Standby VDD Current

 

 

15

µA

CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max

 

 

(CMOS input)

 

 

 

 

 

 

 

 

 

 

 

 

 

ILI

 

Input Leakage Current

 

 

1

µA

VIN=GND to VDD, VDD=VDD Max

ILO

 

Output Leakage Current

 

 

10

µA

VOUT=GND to VDD, VDD=VDD Max

VIL

 

Input Low Voltage

 

 

0.8

V

VDD=VDD Min

VIH

 

Input High Voltage

2.0

 

 

V

VDD=VDD Max

VOL

 

Output Low Voltage

 

 

0.4

V

IOL=100 µA, VDD=VDD Min

VOH

 

Output High Voltage

2.4

 

 

V

IOH=-100 µA, VDD=VDD Min

 

 

 

 

 

 

 

T6.3 304

©2001 Silicon Storage Technology, Inc.

S71061-07-000 6/01 304

8

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