256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
FEATURES:
•Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8
•4.5-5.5V Read Operation
•Superior Reliability
–Endurance: At least 1000 Cycles
–Greater than 100 years Data Retention
•Low Power Consumption
–Active Current: 20 mA (typical)
–Standby Current: 10 µA (typical)
•Fast Read Access Time
–70 ns
–90 ns
Data Sheet
•Fast Byte-Program Operation
–Byte-Program Time: 20 µs (typical)
–Chip Program Time:
0.7seconds (typical) for SST27SF256
1.4seconds (typical) for SST27SF512
2.8seconds (typical) for SST27SF010
5.6seconds (typical) for SST27SF020
•Electrical Erase Using Programmer
–Does not require UV source
–Chip-Erase Time: 100 ms (typical)
•TTL I/O Compatibility
•JEDEC Standard Byte-wide EPROM Pinouts
•Packages Available
–32-pin PLCC
–32-pin TSOP (8mm x 14mm)
–28-pin PDIP for SST27SF256/512
–32-pin PDIP for SST27SF010/020
PRODUCT DESCRIPTION
The SST27SF256/512/010/020 are a 32K x8 / 64K x8 / 128K x8 / 256K x8 CMOS, Many-Time Programmable (MTP) low cost flash, manufactured with SST’s proprietary, high performance SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. These MTP devices can be electrically erased and programmed at least 1000 times using an external programmer with a 12 volt power supply. They have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide memories.
Featuring high performance Byte-Program, the SST27SF256/512/010/020 provide a Byte-Program time of 20 µs. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years.
The SST27SF256/512/010/020 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs.
To meet surface mount and conventional through hole requirements, the SST27SF256/512 are offered in 32-pin PLCC, 32-pin TSOP, and 28-pin PDIP packages. The SST27SF010/020 are offered in 32-pin PDIP, 32-pin PLCC and 32-pin TSOP packages. See Figures 1, 2, and 3 for pinouts.
Device Operation
The SST27SF256/512/010/020 are a low cost flash solution that can be used to replace existing UV-EPROM, OTP, and mask ROM sockets. These devices are functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, these devices also support electrical erase operation via an external programmer. They do not require a UV source to erase, and therefore the packages do not have a window.
Read
The Read operation of the SST27SF256/512/010/020 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least TCE - TOE. When the CE# pin is high, the chip is deselected and a typical standby current of 10 µA is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high.
Byte-Program Operation
The SST27SF256/512/010/020 are programmed by using an external programmer. The programming mode for SST27SF256/010/020 is activated by asserting 12V (±5%)
©2001 Silicon Storage Technology, Inc. |
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. |
|
S71152-02-000 5/01 |
502 |
MTP is a trademark of Silicon Storage Technology, Inc. |
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These specifications are subject to change without notice. |
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
on VPP pin, VDD = 5V (±5%), VIL on CE# pin, and VIH on OE# pin. The programming mode for SST27SF512 is activated by asserting 12V (±5%) on OE#/VPP pin, VDD = 5V (±5%), and VIL on CE# pin. These devices are programmed byte-by-byte with the desired data at the desired address using a single pulse (CE# pin low for SST27SF256/512 and PGM# pin low for SST27SF010/ 020) of 20 µs. Using the MTP programming algorithm, the Byte-Programming process continues byte-by-byte until the entire chip has been programmed.
Chip-Erase Operation
The only way to change a data from a “0” to “1” is by electrical erase that changes every bit in the device to “1”. Unlike traditional EPROMs, which use UV light to do the ChipErase, the SST27SF256/512/010/020 uses an electrical Chip-Erase operation. This saves a significant amount of time (about 30 minutes for each Erase operation). The entire chip can be erased in a single pulse of 100 ms (CE# pin low for SST27SF256/512 and PGM# pin for SST27SF010/020). In order to activate the Erase mode for SST27SF256/010/020, the 12V (±5%) is applied to VPP and A9 pins, VDD = 5V (±5%), VIL on CE# pin, and VIH on OE# pin. In order to activate Erase mode for SST27SF512, the 12V (±5%) is applied to OE#/VPP and A9 pins, VDD = 5V (±5%), and VIL on CE# pin. All other address and data pins are “don’t care”. The falling edge of CE# (PGM# for SST27SF010/020) will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figures 13, 14, and 15 for the flowcharts.
Data Sheet
Product Identification Mode
The Product Identification mode identifies the devices as the SST27SF256, SST27SF512, SST27SF010 and SST27SF020 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode for SST27SF256/010/020, the programming equipment must force VH (12V±5%) on address A9 with VPP pin at VDD (5V±10%) or VSS. To activate this mode for SST27SF512, the programming equipment must force VH (12V±5%) on address A9 with OE#/VPP pin at VIL. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Tables 3, 4, and 5 for hardware operation.
TABLE 1: PRODUCT IDENTIFICATION
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Data |
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Manufacturer’s ID |
0000H |
BFH |
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Device ID |
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SST27SF256 |
0001H |
A3H |
SST27SF512 |
0001H |
A4H |
SST27SF010 |
0001H |
A5H |
SST27SF020 |
0001H |
A6H |
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T1.1 502
©2001 Silicon Storage Technology, Inc. |
S71152-02-000 5/01 502 |
2
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF256
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X-Decoder |
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A14 - A0 |
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CE# |
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OE# |
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Control Logic |
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VPP |
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A9 |
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DQ7 - DQ0 |
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502 ILL B1.1 |
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FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF512 |
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SuperFlash |
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X-Decoder |
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A15 - A0 |
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Address Buffer |
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CE# |
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OE#/VPP |
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A9 |
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DQ7 - DQ0 |
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502 ILL B2.1 |
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FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF010/020 |
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SuperFlash |
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X-Decoder |
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Memory |
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AMS - A0 |
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Address Buffer |
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Y-Decoder |
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CE# |
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OE# |
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Control Logic |
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I/O Buffers |
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A9 |
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VPP |
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DQ7 - DQ0 |
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PGM# |
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502 ILL B3.2 |
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AMS = A17 for SST27SF020, A16 for SST27SF010 |
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©2001 Silicon Storage Technology, Inc. |
3 |
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S71152-02-000 5/01 502 |
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256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
|
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SST27SF020 |
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A12 |
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A15 |
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A16 |
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V |
V |
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PGM# |
A17 |
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SST27SF010 |
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PP |
DD |
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A12 |
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A15 |
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A16 |
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V |
V |
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PGM# |
NC |
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SST27SF512 |
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PP |
DD |
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A7 |
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A12 |
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A15 |
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NC |
V |
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A14 |
A13 |
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DD |
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SST27SF256 |
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A7 |
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A12 |
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V |
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NC |
V |
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A14 |
A13 |
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PP |
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DD |
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SST27SF020 |
SST27SF010 SST27SF512 |
SST27SF256 |
4 |
3 |
2 |
1 |
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32 |
31 |
30 |
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A7 |
A7 |
A6 |
A6 |
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5 |
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29 |
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A6 |
A6 |
A5 |
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6 |
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28 |
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A5 |
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A5 |
A5 |
A4 |
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7 |
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27 |
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A4 |
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A4 |
A4 |
A3 |
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8 |
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26 |
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A3 |
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32-pin PLCC |
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A3 |
A3 |
A2 |
A2 |
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9 |
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25 |
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Top View |
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A2 |
A2 |
A1 |
A1 |
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10 |
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24 |
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A1 |
A1 |
A0 |
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11 |
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23 |
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A0 |
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A0 |
A0 |
NC |
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12 |
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22 |
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NC |
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DQ0 |
DQ0 |
DQ0 |
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13 |
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21 |
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DQ0 |
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SST27SF256 |
14 |
15 |
16 |
17 |
18 |
19 |
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20 |
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DQ1 |
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DQ2 |
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V |
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NC |
DQ3 |
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DQ4 |
DQ5 |
||||||
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SST27SF512 |
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SS |
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DQ1 |
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DQ2 |
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V |
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NC |
DQ3 |
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DQ4 |
DQ5 |
|||||
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SST27SF010 |
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SS |
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DQ1 |
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DQ2 |
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V |
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DQ3 |
DQ4 |
|
DQ5 |
DQ6 |
|||||
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SST27SF020 |
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SS |
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DQ1 |
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DQ2 |
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V |
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DQ3 |
DQ4 |
|
DQ5 |
DQ6 |
|||||
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SS |
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SST27SF256 SST27SF512 SST27SF010 SST27SF020
A8 |
A8 |
A14 |
A14 |
A9 |
A9 |
A13 |
A13 |
A11 |
A11 |
A8 |
A8 |
NC |
NC |
A9 |
A9 |
OE# |
OE#/VPP |
A11 |
A11 |
A10 |
A10 |
OE# |
OE# |
CE# |
CE# |
A10 |
A10 |
DQ7 |
DQ7 |
CE# |
CE# |
DQ6 |
DQ6 |
DQ7 |
DQ7 |
502 ILL F02c.2
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC
©2001 Silicon Storage Technology, Inc. |
S71152-02-000 5/01 502 |
4
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
SST27SF020 SST27SF010 SST27SF512 SST27SF256 |
SST27SF256 SST27SF512 SST27SF010 SST27SF020 |
A11 |
A11 |
A11 |
A11 |
|
|
1 |
|
A9 |
A9 |
A9 |
A9 |
|
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2 |
|
A8 |
A8 |
A8 |
A8 |
|
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3 |
|
A13 |
A13 |
A13 |
A13 |
|
|
4 |
|
A14 |
A14 |
A14 |
A14 |
|
|
5 |
Standard Pinout |
A17 |
NC |
NC |
NC |
|
|
6 |
|
PGM# |
PGM# |
NC |
NC |
|
|
7 |
Top View |
VDD |
VDD |
VDD |
VDD |
|
|
8 |
|
|
|
||||||
VPP |
VPP |
NC |
VPP |
|
|
9 |
Die Up |
|
|
||||||
A16 |
A16 |
NC |
NC |
|
|
10 |
|
A15 |
A15 |
A15 |
NC |
|
|
11 |
|
A12 |
A12 |
A12 |
A12 |
|
|
12 |
|
A7 |
A7 |
A7 |
A7 |
|
|
13 |
|
A6 |
A6 |
A6 |
A6 |
|
|
14 |
|
A5 |
A5 |
A5 |
A5 |
|
|
15 |
|
A4 |
A4 |
A4 |
A4 |
|
|
16 |
|
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|||||
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32 |
|
|
OE# |
OE#/VPP |
OE# |
OE# |
|
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|||||
31 |
|
|
A10 |
A10 |
A10 |
A10 |
30 |
|
|
CE# |
CE# |
CE# |
CE# |
29 |
|
|
DQ7 |
DQ7 |
DQ7 |
DQ7 |
28 |
|
|
DQ6 |
DQ6 |
DQ6 |
DQ6 |
27 |
|
|
DQ5 |
DQ5 |
DQ5 |
DQ5 |
26 |
|
|
DQ4 |
DQ4 |
DQ4 |
DQ4 |
25 |
|
|
DQ3 |
DQ3 |
DQ3 |
DQ3 |
24 |
|
|
VSS |
VSS |
VSS |
VSS |
|
|
|||||
23 |
|
|
DQ2 |
DQ2 |
DQ2 |
DQ2 |
22 |
|
|
DQ1 |
DQ1 |
DQ1 |
DQ1 |
21 |
|
|
DQ0 |
DQ0 |
DQ0 |
DQ0 |
20 |
|
|
A0 |
A0 |
A0 |
A0 |
19 |
|
|
A1 |
A1 |
A1 |
A1 |
18 |
|
|
A2 |
A2 |
A2 |
A2 |
17 |
|
|
A3 |
A3 |
A3 |
A3 |
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|
502 ILL F01.1 |
|
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|
|||||||
FIGURE |
2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM) |
|
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|||||||
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SST27SF020 |
SST27SF010 |
|
|
|
SST27SF010 |
SST27SF020 |
|
SST27SF512 |
SST27SF256 |
|
|
|
SST27SF256 |
SST27SF512 |
VPP |
VPP |
1 |
|
32 |
VDD |
VDD |
|
|
|
|
|
|
|
|
|
|||||||
A15 |
VPP |
1 |
|
28 |
VDD |
VDD |
A16 |
A16 |
2 |
|
31 |
PGM# |
PGM# |
|
A12 |
A12 |
2 |
|
27 |
A14 |
A14 |
A15 |
A15 |
3 |
|
30 |
NC |
A17 |
|
A7 |
A7 |
3 |
|
26 |
A13 |
A13 |
A12 |
A12 |
4 |
|
29 |
A14 |
A14 |
|
A6 |
A6 |
4 |
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25 |
A8 |
A8 |
A7 |
A7 |
5 |
32-pin |
28 |
A13 |
A13 |
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A5 |
A5 |
5 |
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24 |
A9 |
A9 |
A6 |
A6 |
6 |
27 |
A8 |
A8 |
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28-pin |
PDIP |
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A4 |
A4 |
6 |
23 |
A11 |
A11 |
A5 |
A5 |
7 |
26 |
A9 |
A9 |
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A3 |
A3 |
7 |
PDIP |
22 |
OE# |
OE#/VPP |
A4 |
A4 |
8 |
Top View |
25 |
A11 |
A11 |
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A2 |
A2 |
8 |
Top View |
21 |
A10 |
A10 |
A3 |
A3 |
9 |
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24 |
OE# |
OE# |
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A2 |
A2 |
10 |
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23 |
A10 |
A10 |
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A1 |
A1 |
9 |
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20 |
CE# |
CE# |
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A0 |
A0 |
10 |
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19 |
DQ7 |
DQ7 |
A1 |
A1 |
11 |
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22 |
CE# |
CE# |
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DQ0 |
DQ0 |
11 |
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18 |
DQ6 |
DQ6 |
A0 |
A0 |
12 |
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21 |
DQ7 |
DQ7 |
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DQ1 |
DQ1 |
12 |
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17 |
DQ5 |
DQ5 |
DQ0 |
DQ0 |
13 |
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20 |
DQ6 |
DQ6 |
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DQ2 |
DQ2 |
13 |
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16 |
DQ4 |
DQ4 |
DQ1 |
DQ1 |
14 |
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19 |
DQ5 |
DQ5 |
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VSS |
VSS |
14 |
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15 |
DQ3 |
DQ3 |
DQ2 |
DQ2 |
15 |
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18 |
DQ4 |
DQ4 |
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502 ILL F02a.1 |
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VSS |
VSS |
16 |
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17 |
DQ3 |
DQ3 |
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502 ILL F02b.1 |
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FIGURE |
3: PIN ASSIGNMENTS FOR 28-PIN AND 32-PIN PDIP |
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©2001 Silicon Storage Technology, Inc. |
S71152-02-000 5/01 502 |
5
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256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash |
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SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020 |
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Data Sheet |
TABLE |
2: PIN DESCRIPTION |
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Symbol |
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Pin Name |
Functions |
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AMS1-A0 |
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Address Inputs |
To provide memory addresses |
DQ7-DQ0 |
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Data Input/output |
To output data during Read cycles and receive input data during Program cycles |
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The outputs are in tri-state when OE# or CE# is high. |
CE# |
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Chip Enable |
To activate the device when CE# is low |
OE# |
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Output Enable |
For SST27SF256/010/020, to gate the data output buffers during Read operation |
OE#/VPP |
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Output Enable/VPP |
For SST27SF512, to gate the data output buffers during Read operation and high voltage |
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pin during Chip-Erase and programming operation |
VPP |
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Power Supply for |
For SST27SF256/010/020, high voltage pin during Chip-Erase and programming opera- |
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Program or Erase |
tion 12V (±5%) |
VDD |
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Power Supply |
To provide 5.0V supply (±10%) |
VSS |
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Ground |
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NC |
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No Connection |
Unconnected pins. |
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T2.3 502 |
1.AMS = Most significant address
AMS = A14 for SST27SF256, A15 for SST27SF512, A16 for SST27SF010, and A17 for SST27SF020
©2001 Silicon Storage Technology, Inc. |
S71152-02-000 5/01 502 |
6
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
TABLE |
3: OPERATION MODES SELECTION FOR SST27SF256 |
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Mode |
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CE# |
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OE# |
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VPP |
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A9 |
DQ |
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Address |
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Read |
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VIL |
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VIL |
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VDD or VSS |
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AIN |
DOUT |
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AIN |
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Output Disable |
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VIL |
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VIH |
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VDD or VSS |
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X |
High Z |
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X |
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Byte-Program |
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VIL |
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VIH |
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VPPH |
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AIN |
DIN |
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AIN |
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Standby |
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VIH |
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X |
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VDD or VSS |
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X |
High Z |
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X |
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Chip-Erase |
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VIL |
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VIH |
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VPPH |
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VH |
High Z |
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X |
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Program/Erase Inhibit |
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VIH |
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X |
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VPPH |
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X |
High Z |
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X |
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Product Identification |
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VIL |
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VIL |
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VDD or VSS |
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VH |
Manufacturer’s ID (BFH) |
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A14 - A1 = VIL, A0 = VIL |
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Device ID (A3H) |
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A14 - A1 = VIL, A0 = VIH |
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T3.1 502 |
Note: X = VIL or VIH |
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VPPH = 12V±5%, VH = 12V±5% |
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TABLE |
4: OPERATION MODES SELECTION FOR SST27SF512 |
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Mode |
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CE# |
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OE#/VPP |
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A9 |
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DQ |
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Address |
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Read |
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VIL |
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VIL |
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AIN |
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DOUT |
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AIN |
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Output Disable |
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VIL |
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VIH |
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X |
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High Z |
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X |
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Program |
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VIL |
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VPPH |
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AIN |
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DIN |
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AIN |
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Standby |
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VIH |
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X |
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X |
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High Z |
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X |
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Chip-Erase |
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VIL |
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VPPH |
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VH |
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High Z |
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X |
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Program/Erase Inhibit |
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VIH |
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VPPH |
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X |
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High Z |
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X |
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Product Identification |
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VIL |
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VIL |
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VH |
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Manufacturer’s ID (BFH) |
A15 - A1 = VIL, A0 = VIL |
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Device ID (A4H) |
A15 - A1 = VIL, A0 = VIH |
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Note: X = VIL or VIH |
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T4.1 502 |
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VPPH = 12V±5%, VH = 12V±5% |
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TABLE |
5: OPERATION MODES SELECTION FOR SST27SF010/020 |
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Mode |
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CE# |
OE# |
PGM# |
A9 |
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VPP |
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DQ |
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Address |
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Read |
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VIL |
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VIL |
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X |
AIN |
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VDD or VSS |
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DOUT |
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AIN |
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Output Disable |
VIL |
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VIH |
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X |
X |
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VDD or VSS |
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High Z |
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AIN |
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Program |
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VIL |
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VIH |
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VIL |
AIN |
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VPPH |
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DIN |
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AIN |
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Standby |
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VIH |
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X |
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X |
X |
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VDD or VSS |
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High Z |
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X |
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Chip-Erase |
VIL |
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VIH |
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VIL |
VH |
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VPPH |
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High Z |
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X |
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Program/Erase Inhibit |
VIH |
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X |
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X |
X |
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VPPH |
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High Z |
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X |
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Product Identification |
VIL |
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VIL |
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X |
VH |
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VDD or VSS |
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Manufacturer’s ID (BFH) |
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AMS2 - A1 = VIL, A0 = VIL |
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Device ID1 |
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AMS2 - A1 = VIL, A0 = VIH |
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T5.1 502 |
1.Device ID = A5H for SST27SF010 and A6H for SST27SF020
2.AMS = Most significant address
AMS = A16 for SST27SF010 and A17 for SST27SF020
Note: X = VIL or VIH
VPPH = 12V±5%, VH = 12V±5%
©2001 Silicon Storage Technology, Inc. |
S71152-02-000 5/01 502 |
7
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C |
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C |
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V |
Transient Voltage (<20 ns) on Any Pin to Ground Potential |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V |
Voltage on A9 and VPP Pin to Ground Potential . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V |
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W |
Through Hold Lead Soldering Temperature (10 Seconds) . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C |
Surface Mount Lead Soldering Temperature (3 Seconds) . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C |
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA |
1. Outputs shorted for no more than one second. No more than one output shorted at a time. |
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OPERATING RANGE |
AC CONDITIONS OF TEST |
Range |
Ambient Temp |
VDD |
VPP |
Commercial |
0°C to +70°C |
5.0V±10% |
12V±5% |
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. . . . . . . . . . .Input Rise/Fall Time |
10 ns |
Output Load . . . . . . . . . . . . . . . . . |
CL = 100 pF for 90 ns |
Output Load . . . . . . . . . . . . . . . . . |
CL = 30 pF for 70 ns |
See Figures 11 and 12 |
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TABLE |
6: READ MODE DC OPERATING CHARACTERISTICS FOR SST27SF256/512/010/020 |
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VDD = 5.0V±10%, V PP=VDD OR VSS (Ta = 0°C to +70°C (Commercial)) |
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Limits |
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Symbol |
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Parameter |
Min |
Max |
Units |
Test Conditions |
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IDD |
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VDD Read Current |
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Address input=VIL/VIH at f=1/TRC Min |
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VDD=VDD Max |
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30 |
mA |
CE#=OE#=VIL, all I/Os open |
IPPR |
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VPP Read Current |
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Address input=VIL/VIH at f=1/TRC Min |
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VDD=VDD Max, VPP=VDD |
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100 |
µA |
CE#=OE#=VIL, all I/Os open |
ISB1 |
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Standby VDD Current |
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3 |
mA |
CE#=VIH, VDD=VDD Max |
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(TTL input) |
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ISB2 |
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Standby VDD Current |
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100 |
µA |
CE#=VDD-0.3 |
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(CMOS input) |
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VDD=VDD Max |
ILI |
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Input Leakage Current |
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1 |
µA |
VIN=GND to VDD, VDD=VDD Max |
ILO |
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Output Leakage Current |
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10 |
µA |
VOUT=GND to VDD, VDD=VDD Max |
VIL |
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Input Low Voltage |
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0.8 |
V |
VDD=VDD Min |
VIH |
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Input High Voltage |
2.0 |
VDD+0.5 |
V |
VDD=VDD Max |
VOL |
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Output Low Voltage |
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0.2 |
V |
IOL=2.1 mA, VDD=VDD Min |
VOH |
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Output High Voltage |
2.4 |
|
V |
IOH=-400 µA, VDD=VDD Min |
IH |
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Supervoltage Current for A9 |
|
100 |
µA |
CE#=OE#=VIL, A9=VH Max |
T6.3 502
©2001 Silicon Storage Technology, Inc. |
S71152-02-000 5/01 502 |
8