SGS Thomson Microelectronics M24256-WBN6, M24256-W, M24256-MW6, M24256-BN6, M24256 Datasheet

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M24256

M24128

256/128 Kbit Serial I²C Bus EEPROM

Without Chip Enable Lines

PRELIMINARY DATA

■Compatible with I2C Extended Addressing

■Two Wire I2C Serial Interface Supports 400 kHz Protocol

■Single Supply Voltage:

–4.5V to 5.5V for M24xxx

–2.5V to 5.5V for M24xxx-W

■Hardware Write Control

■BYTE and PAGE WRITE (up to 64 Bytes)

■RANDOM and SEQUENTIAL READ Modes

■Self-Timed Programming Cycle

■Automatic Address Incrementing

■Enhanced ESD/Latch-Up Behavior

■100,000 Erase/Write Cycles (minimum)

■40 Year Data Retention (minimum)

DESCRIPTION

These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32Kx8 bits (M24256) and 16Kx8 bits (M24128), and operate down to 2.5 V (for the -W version of each device).

	8
	1
	PSDIP8 (BN)
	0.25 mm frame
8	8
1	1
SO8 (MN)	SO8 (MW)
150 mil width	200 mil width

The M24256 and M24128 are available in Plastic Dual-in-Line and Plastic Small Outline packages.

These memory devices are compatible with the I2C extended memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4- bit unique Device Type Identifier code (1010) in accordance with the I2C bus definition.

Table 1. Signal Names

	SDA		Serial Data/Address Input/
			Output

	SCL		Serial Clock

			Write Control
	WC		Write Control

	VCC		Supply Voltage
	VSS		Ground

Figure 1. Logic Diagram

VCC

SCL

SDA

M24256

M24128

VSS

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M24256, M24128

Figure 2A. DIP Connections

Figure 2B. SO Connections

M24256

M24128

VCC

SCL

VSS

SDA

VSS

SDA

AI01883

AI01884

Note: 1. NC = Not Connected

The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit.

When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is

Table 2. Absolute Maximum Ratings 1

held active until the VCC voltage has reached the POR threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal.

SIGNAL DESCRIPTION Serial Clock (SCL)

The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resis-

Symbol	Parameter		Value	Unit

TA	Ambient Operating Temperature		–40 to 125	°C

TSTG	Storage Temperature		–65 to 150	°C

TLEAD	Lead Temperature during Soldering	PSDIP8: 10 sec	260	°C
TLEAD	Lead Temperature during Soldering	SO8: 40 sec	215	°C
		SO8: 40 sec	215

VIO	Input or Output range		–0.6 to 6.5	V

VCC	Supply Voltage		–0.3 to 6.5	V

VESD	Electrostatic Discharge Voltage (Human Body model) 2		4000	V

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)

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M24256, M24128

tor is not necessary, provided that the master has a push-pull (rather than open drain) output.

Serial Data (SDA)

The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated).

Write Control (WC)

The hardware Write Control pin (WC) is useful for protecting the entire contents of the memory from inadvertent erase/write. The Write Control signal is used to enable (WC=VIL) or disable (WC=VIH) write instructions to the entire memory area. When unconnected, the WC input is internally read as VIL, and write operations are allowed.

When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged.

Please see the Application Note AN404 for a more detailed description of the Write Control feature.

DEVICE OPERATION

The memory device supports the I2C protocol. This is summarized in Figure 4, and is compared with other serial bus protocols in Application Note AN1001. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory

device is always a slave device in all communication.

Start Condition

START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device continuously monitors (except during a programming cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read command, after (and only after) a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits.

Data Input

During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high transition, and the data must change only when the SCL line is low.

Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus

Maximum RP value (kΩ)

VCC

SDA

MASTER

CBUS

SCL

fc = 100kHz

fc = 400kHz

CBUS

100

1000

CBUS (pF)

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SGS Thomson Microelectronics M24256-WBN6, M24256-W, M24256-MW6, M24256-BN6, M24256 Datasheet

M24256, M24128

Figure 4. I2C Bus Protocol

SCL
SDA
START	SDA	SDA	STOP
CONDITION	INPUT	CHANGE	CONDITION

SCL	1	2	3	7	8	9
SDA	MSB					ACK
	START
	CONDITION
SCL	1	2	3	7	8	9
SDA	MSB					ACK

STOP

CONDITION

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Memory Addressing

To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code is further subdivided into: a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address” (0, 0, 0).

Table 3. Device Select Code 1

To address the memory array, the 4-bit Device Type Identifier is 1010b.

The 8th bit is the RW bit. This is set to ‘1’ for read and ‘0’ for write operations. If a match occurs on the Device Select Code, the corresponding memory gives an acknowledgment on the SDA bus during the 9th bit time. If the memory does not match the Device Select Code, it deselects itself from the bus, and goes into stand-by mode.

There are two modes both for read and write. These are summarized in Table 4 and described

		Device Type Identifier				Chip Enable		RW
	b7	b6	b5	b4	b3	b2	b1	b0
Device Select Code	1	0	1	0	0	0	0	RW

Note: 1. The most significant bit, b7, is sent first.

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Table 4. Operating Modes

Mode

bit

Data Bytes

Initial Sequence

Current Address Read

= ‘1’

START, Device Select, RW

= ‘0’, Address

Random Address Read

START, Device Select, RW

= ‘1’

reSTART, Device Select, RW

Sequential Read

³ 1

Similar to Current or Random Address Read

Byte Write

VIL

= ‘0’

START, Device Select, RW

Page Write

VIL

£ 64

= ‘0’

START, Device Select, RW

Note: 1. X = VIH or VIL.

later. A communication between the master and the slave is ended with a STOP condition.

Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 5) is sent first, followed by the Least significant Byte (Table 6). Bits b15 to b0 form the address of

the byte in memory. Bit b15 is treated as a Don’t Care bit on the M24256 memory. Bits b15 and b14 are treated as Don’t Care bits on the M24128 memory.

Figure 5. Write Mode Sequences with WC=1 (data write inhibited)

ACK

NO ACK

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

START

R/W

STOP

PAGE WRITE

START

WC (cont'd)

PAGE WRITE (cont'd)

ACK

NO ACK

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

R/W

NO ACK

DATA IN N

STOP

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