Datasheet SC1406TS Datasheet (Semtech Corporation)

PORTABLE PENTIUM® II & III
POWER SUPPLY CONTROLLER

SC1406

PRELIMINA RY - A ugust 27, 1999

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DESCRIPTION

The SC1406 is a High S peed, High perf ormance Hys­teretic Mode control ler. It is part of a two chip solution,
with the SC1405 Smart Dri ver, pr ovi ding power to ad­vanced micro- processors. It uses a Dynamic S et Point
switching technique along with an ultra-fast compara­tor to provide t he c ontrol signal to an external high
speed Mosfet dri ver. A 5-bit DAC sets the output v olt­age, thus providing a voltage resolution of 25mV .

SC1406 has two on-chip linear regulator s which driv e
external PNP transistor s with output voltage settings
of 1.5V and 2.5Vdc. The linear regul ator drivers have
a separate soft start. A PWRGD TTL level signal is
asserted when all voltages are within specifications.
The part features Low Battery Det ec t and Underv olt­age Lock-Out for the main Hysteretic controller to as­sure V-DC is within ac c eptable limits. An Over-Current
comparat or disables the main controller during an
overc urrent condition using an ex ternally pr o­grammable threshold.

FEATURES

•

High Speed Hysteret ic controller provides high
efficienc y over a wide operating load range

•

Inherently stable

•

Complet e power solution with two LDO driv er s

•

Programmable output vol tage for Pentium
Processors

APPLICATIONS

•

Laptop and Notebook computers

•

High perf ormance Microprocessor based systems

•

High efficiency distributed power supplies

ORDERING INFORMATION

DEVICE PACKAGE TEMP. (TJ)

SC1406TS TSSOP- 28 0 - 125°C

®

II & III

PIN CONFIGURATION

Top View

TSSOP-28

BLOCK DIAGRAM

Pentium is a registered trademark of Intel Corporation

© 1999 SEMTECH CORP. 652 MITCHELL ROA D NEW B URY P A RK CA 91320

1

PORTABLE PENTIUM® II & III
POWER SUPPLY CONTROLLER

PRELIMINA RY - A ugust 27, 1999

PIN DESCRIPTION:

Pin Pin Name Pin Function

1 HYS Core comparator hysteresis settling.
2 CLSET Current limit setting pin.
3 VCOUT Voltage clamp output.
4 VCIN Voltage clamp input.
5 VCBY P Voltage clamp bypass pin.
6 VID4 VID most si gnificant bit input.
7 VID3 VID input
8 VID2 VID input
9 VID1 VID input

10 VID0 VID least signi ficant bit i nput.
11 BASE25 2.5V Linear regulator drive.
12 FB25 2.5V Linear regulator output feedback.
13 BASE15 1.5V Linear regulator drive.
14 FB15 1.5V Linear regulator output feedback.
15 EN Enables the IC when high. This is capable of accepting 5.0V signal lev el.
16 PWRGD When the main c onvert er output is withi n +10% of the V ID DAC setting, this signal i s

driven high to VCC lev el. Inter nal pull- down 100K.

17 LBIN Low battery input. This pin is used to set t he mini mum volt age to the converter.

When the input to this pin is l ess than 1. 225V , the converter i s hel d in an Under-Voltage­Lock-Out mode regardless of the status of EN.

18 SSLR Linear regul ators soft start. During power-up, the external soft-start c apac itor (1200pF,

typ) is charged by an internal 1µA c ur r ent source to set the ramp up time of the linear
regulator outputs, 1.5V and 2.5V . This ram p up time is typically 2m s, 6ms max . This is
discharged when BIASEN (internal signal) is low.

19 SSCORE Main contr oller output soft start . During power-up, the external S oft-Start capaci tor

(1800pF, ty p) is charged by an inter nal 1µA current source to set the ramp up time of the
main convert er output. This ramp up time is ty picall y 3ms, 6ms m ax. This is discharged
when BIASEN is low. Core soft start current tol erance t r acks the LDO sof t start current to
within 10%.

20 CORE Converter output feedback.
21 DAC VID digital t o analog output.
22 GND Ground
23 CO Comparator output. Mai n regulator controller output. Int er nal pull- down 100K.
24 VCC Supply voltage.
25 CMP Cor e c omparator input pin.
26 CMPREF Core comparator reference input pin.
27 CL Current limit input pin.
28 CLREF Current l imi t referenc e input pin.

SC1406

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© 1999 SEMTECH CORP. 652 MITCHELL ROA D NEW B URY P A RK CA 91320

2

PORTABLE PENTIUM® II & III

SC1406

POWER SUPPLY CONTROLLER

PRELIMINA RY - A ugust 27, 1999

ABSOLU TE MAXIMUM RATINGS

PARAMETER SYMBOL MAXIMUM UNITS

VCC Supply Voltage Vmax

VCC

7V
Low Battery Input LBIN 7 V
Input & Out put Pins V

+ 0.3

CC

V

GND - 0.3
Enable EN 7 V
Operating Junction T emperature T
Lead Temperature (Soldering) 10 seconds T
Storage Temperature T

J

L

STG

0 to +125 °C

300 °C

-65 to 150 °C

ELECTRICAL CHARACTERISTICS

Unless specified: 0 < TA < 100°C; VCC = 3.3V (See Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SUPPLY, BIAS, UVLO, VDC MONITOR AND POWERGOOD
Supply (VCC, GND)

VCC Supply Voltage

V

CCMAX

Range
VCC Quiescent Current I

CCQ

EN is low, 3.0V < VCC < 3.6V 10 µA

EN is high and in UVLO 350

VCC Operati ng Current I

CC

EN is high 10.0 15 mA

Under Vol tage Lock Out Circuit

Threshold V

Hysteresis V

HCC

V

LCC

HYSTCC

Enable Input

Input High Vih 3.0 <

VCC < 5V 0.7*V

Input Low Vil 0.8 V

Low Battery Monitor

Threshold V
Input Bias Curr ent I

THDC

BDC

V
V

LB_IN

LB_IN

> V
< V

THDC

THDC

VCORE Power Good Generator

Input Threshol d V

Output Voltage V

HCORE

V

LCORE

HPWRGD

V

= 0.9V - 1. 675V 1.08*V

DAC

I

= 10µa (source) EN i s hi gh 0.95*

PWRGD

(Activ e Hi)

V

LPWRGD

I

= 10µA (sink), EN is high 0.4 V

PWRGD

(Active low)

V

PWRGD

V

OUT

I

= 10µA (sink), UVLO 0.8 V

PWRGD

During the l atency time (50µs) of

any VID code change

3.0 3.3 6.0 V

2.95 V

2.7
20 mV

CC

1.175 1.225 1.275 V
±0.3 µA

0.6 1.0 10.5

1.12*V

0.92*V

CC

CC

0.88*V

V

CC

CC

CC

Don’t

care

V

V
V

V

Note 1: Specification refers to application circuit (Figure 1.).

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© 1999 SEMTECH CORP. 652 MITCHELL ROA D NEW B URY P A RK CA 91320

PORTABLE PENTIUM® II & III

SC1406

POWER SUPPLY CONTROLLER

PRELIMINA RY - A ugust 27, 1999

ELECTRICAL CHARACTERISTICS (CONT .)

Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CORE CONVERTER CONTROLLER

Core Converter Soft Start Current

Core Conver ter Soft Start Curr ent I

SSCORE

Charge (Source) curr ent 0.6 1 1.45 µA
Discharge (Si nk ) c ur r ent 0.30 1 mA

V

Soft S tart Termination

SSCORE

V

SSTERM

Threshold
V

Discharge Threshold V

SSCORE

SSDIS

VID DAC

VID Input T hreshold V

V

VID Input-P ull-up Curr ent,VID (0-4) I
Output Voltage Accurac y V

Settling Time* t

pdVID_DAC

VID_IH

VID_IL

VID

DAC_ERRIDAC

3.0V < V

VID (0-4) = 00000...11111 6 40 µA

= 0, VID( 0- 4) = 00000...11111 -0.85 +0.85 %

C

VID is set to change V CORE from

1.30V to 1.45V or 1.45V to 1.30V

CORE Comparator (CMP, CMPRE F, HYS, CO )

V

Input Bias Curr ent I
Input Offset Voltage V

VCPMREF

BCMP

CPM-

CMP

= V

V

Hysteresis Setting Current R

I

CMPREF

R

Output Voltage V

CMP<CMPREF

CMP>CMPREF

Propagation Delay Time**

T

pd CMP-CO

Measured at device pins, from the

HCO

V

LCO

Load Impedance = 100k in

parallel with 10pF, V

Load Impedance = 100k in

parallel with 10pF, V

V

CMPREF

= 1.3V ∆ V

step with +20m V , over dr iv e

trip poi nt to 50% of CO transition.

T

CMPREF

= 1.3V ∆ V

V

step with 20mV overdrive,

T

Output Rise/Fall Times**

T

R

Measured between 30% and 70%
points of CO transition

T

F

1.53 1.70 1.87 V

150 400 mV

< 3.6V 0. 7*V

CC

= 1000pF

DAC

= 1.3V ±2 µA

CMPREF

= 1.3V ±1.5 ±3 mV

CMPREF

= open + 2

HYS

R

= 17k

= 170k

Ω

Ω

HYS

HYS

CC

±89 +

+

100 + 111 µA

8+ 10 + 12.5

2.5 V

= 3.0V

CC

= 3.6V

CC

= +40mV

CMP

= 25°C,

T

A

= full range

A

= 40mV

CMP

= 25°C,

T

A

= full range

A

CCO = 10pF

= 3.0V

V

CC

RCO = 100K

710

710

0.8

35 µs

0.4 V

20

ns

30

20
30

ns

V

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© 1999 SEMTECH CORP. 652 MITCHELL ROA D NEW B URY P A RK CA 91320

PORTABLE PENTIUM® II & III

SC1406

POWER SUPPLY CONTROLLER

PRELIMINA RY - A ugust 27, 1999

ELECTRICAL CHARACTERISTICS (CONT .)

Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Current Limit Comparator (CL, CLREF, CLSET)

Input Bias Curr ent +
Current Limit Setting Current | +

I

*The Tamky device is required to
meet the CL set ting current

requirements for R

CLSET

of

“17kΩ and 170kΩ or “42.5kΩ and
20kΩ”. Supplier production testing

will use the 17kΩ /170k
combination or the 42. 5kΩ /20k

Ω

Ω

combination.

Input Offset Voltage V

V

Propagation Delay Time**

T

pd_CL-CO

Measured at the device pins, from
the trip point to 50% of CO
transition

I

CL

|R

CLREF

R

CL -

CLREF

V

CMPREF

-50mV step wit h - 20mV overdrive,

VCS = 1.3V 5 µA

= open V

CLSET

CLREF-VCL

= 10mV

V

CLRER-VCL

= -10mV

R

CLSET

= 17k

Ω∗

V

CLREF-VCL

= 10mV

V

CLREF-VCL

= -10mV

R

CLSET

= 170k

Ω∗

V

CLREF-VCL

= 10mV

V

CLREF-VCL

= -10mV

CLSET

= 42.5k

Ω∗

V

CLRER-VCL

= 10mV

V

CLRER-VCL

= -10mV

R

CLSET

= 20k

Ω∗

V

CLREF-VCL

= 10mV

V

CLRER-VCL

= -10mV

V

= 1.3V ±4 ±6 mV

CLREF

= 1.3V, ∆ V

= +50mV

CMP

step with +20m V overdriv e,

= 25°C,

T

A

T

= full range 150 ns

A

V

CMPREF

= 1.3V, ∆ V

= 25°C,

T

A

CMP

=

7.5
µA

5.0

262.5 300 337.5 µA

175 200 225

19.5 30 40.5 µA

13 20 27

100.5 120 139.5 µA

67 80 93

222 255 288 µA

148 170 192

100

100

T

= full range 150

A

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© 1999 SEMTECH CORP. 652 MITCHELL ROA D NEW B URY P A RK CA 91320

PORTABLE PENTIUM® II & III

SC1406

POWER SUPPLY CONTROLLER

PRELIMINA RY - A ugust 27, 1999

ELECTRICAL CHARACTERISTICS (CONT .)

Unless specified: -0 < TA < 100°C; V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

1.5V Linear Regulator Controller

Input Bias Curr ent I
Output Voltage

= 56µF, 20mΩ ESR max

C

O_1.5

or 150µF, 45mΩ ESR max
Capacitance tolerance = 20%

= 3.3V (See test circuit)

CC

LINEAR REGULAT OR CONTROLLERS

LR15

V

O_1.5,

Imin =

0.1mA

V

= 1.5V 1 mA

FB_15

= 500mA, pnp BJT with B

I

O

= 500mA

I

C

MIN

> 50 @

1.47 1.50 1.54 V

Base Drive Output Curr ent I

BASE_1.5

2.5V Linear Regulator Controller

Input Bias Curr ent
Output Voltage

= 1µFceramic

C

O_2.5

ESR range = 1m

Ω −

30m

Ω

I

LR25

V

O_2.5,

Imin = 0A

Imax=0.1A

Capacitance tolerance = 20%
Base Drive Output Curr ent I

BASE_2.5

Linear Regulator Soft Start (LRSS)

Linear Reg Soft-Start Current I

Enable Threshol d V
Soft S tart Termination Threshold V

LRSS

SSLR_EN

TH_LRSS

Voltage Clamp (VCIN, V COUT, V CBY P )

Input Voltage V
Output Voltage

H_VCIN

V

H_VCOUT

Imin = 10µA

V

L_VCOUT

Progagation Delay** T

VCIN_VCOUT

@ 25°C 10 120 mA

V

= 2.5V 1 mA

FB_25

IO = Im ax, pnp BJT with B

= 100mA

I

C

> 50 @

MIN

2.45 2.50 2.55 V

3.5 20 mA

Charge Current, V

Discharge Current, V

= 0V -0.6 -1 -1.4 µA

LRSS

= 1.50V,

LRSS

0.3 1 1.45 mA

EN is low or in UVLO

150 400 mV

1.53 1.70 1.87 V

0.95 1.5 1.60 V

R

= 150

VCOUT

tied to V

= -10µA

I

VCIN

C

R

VCOUT

= 1500pF, VCIN steps from

VCBYP

pd

Ω

= 2.5V

S

= 150Ω tied to VS = 2.5V

VCIN is open 0. 8V

V

= 0.175V 0.375

VCIN

S

V

V

S

10 ns

0.175V to 1.50V and back.

Measured from 50% of VCIN step to

50% of VCOUT transient

* Guaranteed by design.
**Guaranteed by char ac terization.

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PRELIMINA RY - A ugust 27, 1999

PORTABLE PENTIUM® II & III
POWER SUPPLY CONTROLLER

SC1406

VID vs. V

VOLTAGE

DAC

VID MIN TYP MAX

43210 1% < V

O

V

O

1% > V

0 0 0 0 0 1.658 1.675 1.692
0 0 0 0 1 1.633 1.650 1.666
0 0 0 1 0 1.609 1.625 1.641
0 0 0 1 1 1.584 1.600 1.616
0 0 1 0 0 1.560 1.575 1.591
0 0 1 0 1 1.534 1.550 1.565
0 0 1 1 0 1.510 1.525 1.540
0 0 1 1 1 1.485 1.500 1.515
0 1 0 0 0 1.460 1.475 1.490
0 1 0 0 1 1.435 1.450 1.464
0 1 0 1 0 1.411 1.425 1.439
0 1 0 1 1 1.386 1.400 1.414
0 1 1 0 0 1.361 1.375 1.389
0 1 1 0 1 1.336 1.350 1.363

O

0 1 1 1 0 1.312 1.325 1.338
0 1 1 1 1 1.287 1.300 1.313
1 0 0 0 0 1.262 1.275 1.288
1 0 0 0 1 1.237 1.250 1.262
1 0 0 1 0 1.213 1.225 1.237
1 0 0 1 1 1.188 1.200 1.212
1 0 1 0 0 1.163 1.175 1.187
1 0 1 0 1 1.138 1.150 1.161
1 0 1 1 0 1.114 1.125 1.136
1 0 1 1 1 1.089 1.100 1.111
1 1 0 0 0 1.064 1.075 1.086
1 1 0 0 1 1.039 1.050 1.060
1 1 0 1 0 1.015 1.025 1.035
1 1 0 1 1 0.99 1.00 1.01
1 1 1 0 0 0.965 0.975 0.984
1 1 1 0 1 0.940 0.950 0.959
1 1 1 1 0 0.916 0.925 0.934
1 1 1 1 1 0.891 0.900 0.909

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© 1999 SEMTECH CORP. 652 MITCHELL ROA D NEW B URY P A RK CA 91320

PRELIMINA RY - A ugust 27, 1999

PORTABLE PENTIUM® II & III
POWER SUPPLY CONTROLLER

SC1406

FUNCTIONAL DESCRIPTION

SUPPLY

The chip i s opt imi z ed to operate f r om a 3.3V +
but is also designed to work up t o 6V maximum suppl y
voltage. If V

is out of the 3.3V + 5% vol tage range,

CC

the quiescent current will increase somewhat and
slight degradation of line regul ation is ex pec ted.

UNDER VOLTAGE LOCK-O UT CIRCUIT

The under voltage l oc k out circuit consists of two com­parators, the low battery and low V

(low supply volt-

CC

age) comparators. The output of the comparator
gated with the Enable signal tur ns on or off the inter­nal bias, enables or disables the CO output, and
initiates or resets the soft start timers.

POWER GOOD GENERATOR

If t he c hip is enabled but not in UVLO condition, and
the core voltage get s wit hin +

10% of the V ID pro­grammed value, then a high lev el Power Good signal
is generated on the PWRGD pin to trigger the CPU
power up sequence. If t he c hip is either disabled or
enabled in UVLO c ondition, then PWRGD stays low.
This condition is satisfied by the pr esence of an inter ­nal 100kΩ pull-down resistor c onnec ted from PWRGD
to ground.
During soft st ar t, PWRGD stays low independent ly
from the status of V c or e vol tage. During t his tim e,
PW RGD status is “don’t care” .

BAND GAP REFERENCE

A better t han +

1% precision band gap r eference act s
as the internal referenc e voltage standard of the chip,
which all c r itical biasing voltages and cur r ents are de­rived from.

CORE CONVERTER CONTROLLER

Precision V ID DAC Reference

The 5-bit digital to analog converter (D A C) serves as
the program mable reference source of the core com­parator. Pr ogr amming is accomplished by CMOS logic
level VID code applied to t he DA C inputs. The VI D
code vs. the DAC output i s shown in the O utput Volt­age Table. T he accuracy of the VID DAC is main­tained on the same level as the band gap reference.
There is a 10µA pull-up current on each DAC input
while EN is high.

5% rail

Core Comparator

This is an ultra-fast hy ster etic comparator with a t y pi­cal propagation delay of approxi mately 20ns at a
20mV overdrive. Its hysteresis is determined by the
resistance ratio of two ex ternal resistors, R
and the high accur ac y internal r eference volt age, V

R

V

=

HYS

OH

R

HYS

V

REF

= 1.7V

and ROH,

HYS

REF

This chip c an be used i n standar d hy ster etic m ode
controller configurati on and in DSPS (Dynamic Set
Point Switching) hysteretic contr oller schem e.

In standard hystereti c controller configuration

, the
core compar ator compares the output voltage of the
core converter, V
DAC voltage, V

to the VID code pr ogrammed

CORE

.

DAC

V

CORE

(t) = V

DAC

+ V

HYST

(t)

The core voltage ramps up and down between the two
thresholds determined by the hyster esi s of the com ­parator:

= V

V

HCORE

V

= V

LCORE

In DSPS hysteretic controller configuration

core compar ator compares the c or e vol tage, V
not to the DAC voltage, V

+ V

DAC

DAC

HYST

- V

DAC

HYST

directly but rather to a

, the

CORE

,
voltage less than the DAC voltage by a DSPS voltage,
V

DSPS.VCORE

(t) = V

DAC

- V

DSPS

(t) + V

HYST

(t)

The DSPS v oltage is a function of t he load current. It
is generated from the c ur r ent sense volt age, V
developed across a sense resistor, R

which is in-

CS,

CS

,

serted in series with t he main buck inductor and al so
used for current sensing for the cycle-by-cycle current
limiti ng. The sense vol tage is scaled up by the DS P S
gain, A
external resistors, R

V

DSPS

, which is set by the r esi stanc e r atio of two

DSPS

(t) = A

• VCS(t) = (1 + ) • RCS • i

DSPS

DAC

and R

CORE

R
R

.

DAC

CORE

CORE

(t)

.

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PRELIMINA RY - A ugust 27, 1999

PORTABLE PENTIUM® II & III
POWER SUPPLY CONTROLLER

SC1406

In DSPS hysteretic controller configuration
(Cont’d)

The compar ator refer enc e vol tage positioning is such
that an increasing current sense voltage, V CS , i,e, an
elevating l oad c ur r ent, causes the ref er enc e vol tage to
decrease, and as a consequence, the core out put volt­age also droops. At no l oad c ur r ent, there i s no droop
while a maxim um load, the droop is li kewise maxi­mum.

In order for the core voltage to be positioned around
the nomi nal V

voltage symmetrically and not just

DAC

one way downward from the nominal value, a DSPS
offset voltage, V

DSPSOFFS

, can be introduced. The off­set voltage moves the comparator reference voltage
upward at no load. At optimal offsetting, the referenc e
voltage is above the nominal level for load c ur r ents
less than half of the maxi mum load, and below the
nominal value for c ur r ents higher than that. The maxi­mum amount of core voltage posit ioning can be deter ­mined from the constrain which says the out put volt­age at no load condi tion must st ill remain below the
upper threshold of the core voltage regulation wi ndow,
and at maximum load, it must be above the lower
threshold.

The offset voltage can be generated across a resistor,

, which is also used to create the hysteresis volt-

R

OH

age by forcing a unipolar DSPS offsetting current
through it. The offsetti ng c urrent is conveniently pro­vided by a high value resistor , R

, connected from

OFFSET

the compar ator CMP pin t o the ground.

VV

+

+

RR

R

CORECS

OFFSETOH

R

OH

OFFSET

•≈

V

DAC

•==

•

RIRV

OHDSPSOHDSPSOFFS

<<=<<

ROFFSETROH,VDACVCORE,VCOREVCS

In DSPS hysterestic controller configuration, the com­parator threshol ds can be calculated from the DAC
voltage, V

, the DSPS of fsetting volt age, V

DAC

the DSPS v oltage V
voltage, V

by summing them at the comparator in-

HYST

, and the bipolar hysteresis

DSPS

DSPSOFFS

,

puts at the appropriate load curr ent levels:

Core Volt age Offsetti ng

In order for the core voltage to be positioned around
the nomi nal V

voltage symmetrically and not just

DAC

always one direction downward, a core offset voltage,

can be introduc ed. The offset voltage moves the

V

OFFS

comparat or r eference volt age upwards. Using opt imal
offsetting, the core compar ator reference voltage will
be above t he V ID programmed nomi nal DAC voltage
for l oad c urrents less than half of t he maximum load,
and below that for higher curr ent. The m aximum
amount of the core volt age posi tioning can be deter­mined from the constraint that the output voltage regu­lation wi ndow, and at maximum load, it has t o be
above t he lower threshold.

The positi oning offset v oltage can be generated
across the same resistor, ROH also used to create the
hysteresis v oltage, by forcing a unipolar offsett ing cur­rent through it. The offsett ing current is conveniently
provided by a high value resi stor, ROFF S c onnec ted
from the compar ator CMP pin to the ground.

Current Li mit Comparato r

The current lim it com par ator moni tors the core con­verter output current and turns the hi gh si de switc h off
when the current ex c eeds the upper c ur r ent limit
threshold, VHCL and r e- enable only i f the l oad c ur r ent
drops below the lower current lim it threshold, VLCL.
The current is sensed by monitoring the voltage drop
across the current sense resistor, R

, connected in

CS

series with the core convert er main i nduc tor (the same
resistor used for DSPS input signal generation). T he
thresholds have the following rel ationships:

R

CLOH

CLSET

CLOH

CLSET

V

••=

REF

V

••=

REF

V

•=

REF

V

HCL

LCL

HYSCL

3V

R

R

2V

R

R

CLOH

R

CLSET

RdacRcore(RoffsetIcoreRcsRcore)RohRoffset(Vdac

:Vcore

=

)RohRoffset(Rcore

Vhys2:Vcore

••=∆

+•

RohRdacRoffsetRcore

•−•

RohRdacRoffsetRcore

•−•

•

srRe

+

+•••−•+•

srRe

)RohRoffset(Rcore

+•

RohRdacRoffsetRcore

•−•

Pentium is a registered trademark of Intel Corporation

9

© 1999 SEMTECH CORP. 652 MITCHELL ROA D NEW B URY P A RK CA 91320

PRELIMINA RY - A ugust 27, 1999

PORTABLE PENTIUM® II & III
POWER SUPPLY CONTROLLER

SC1406

Core Converter Soft Start Timer

The mai n purpose of this block is to cont r ol the ram p­up tim e of the core vol tage in order to r educ e the ini­tial inrush current on t he c or e input voltage (battery)
rail. The soft start circuit consists of an internal c ur ­rent source, external soft start timi ng c apac itor, inter­nal switch across the capacitor, and a comparator
monit oring the capacitor voltage.

LINEAR REGULAT OR CONTROLLER

1.5V Lin ear Regulato r

This block is a linear regulator contr oller, whic h dr iv es
an external PNP bipol ar transistor as a pass element .
The linear regulator is capable of delivering 500mA
steady state DC current and shoul d support transient
current of 1A, assuming the output filtering capacitor
is properly sel ec ted to provide enough charge for the
duration of the load t r ansient.

2.5V Lin ear Regulato r

This block is a low drop-out (LDO) linear regulator
controller, which drives an external PNP bipolar tr an­sistor as a pass element. The LDO li near r egulator is
capable of delivering 100mA steady DC current and
should support transient c ur r ent of 100mA, assuming
the output filtering capacitor is properly selected t o
provide enough charge f or the duration of the load
transient.

Linear Regulator Soft Start Timer

A soft start timer circuit of the linear r egulators is sim i­lar to that of the c ore conver ter, and is used to cont r ol
the ramp up time of the linear regulat or output volt­ages. For maximum f lexi bility in controlling the start
up sequence, the soft star t funct ion of t he linear regu­lators is separated from that of the core converter.

VOLTAGE CLAMP

The level tr ansl ator converts an input voltage swing
on the IO rail, i nto a voltage swing on the CLK or VCC
rail depending on where the open drain output of the
translator is tied to t hr ough an external pull-up resistor .
The level tr ansl ator has to track the input i n phase,
and must be able to switch in 5ns (typical) following an
input threshold intercept.

APPLICATION INFORMAT ION

Power on/off Sequence

Pentium is a registered trademark of Intel Corporation

© 1999 SEMTECH CORP. 652 MITCHELL ROA D NEW B URY P A RK CA 91320

10

PRELIMINA RY - A ugust 27, 1999

OUTL INE DRAWING - TSSOP-28

PORTABLE PENTIUM® II & III
POWER SUPPLY CONTROLLER

SC1406

Pentium is a registered trademark of Intel Corporation

© 1999 SEMTECH CORP. 652 MITCHELL ROA D NEW B URY P A RK CA 91320

11