Samsung K4E171611D-T, K4E171611D-J, K4E171612D-T, K4E171612D-J, K4E151612D-J Datasheet

K4E171611D, K4E151611D
K4E171612D, K4E151612D	CMOS DRAM

1M x 16Bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Selfrefresh operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung′ s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.

FEATURES

•Part Identification

-K4E171611D-J(T) (5V, 4K Ref.)

-K4E151611D-J(T) (5V, 1K Ref.)

-K4E171612D-J(T) (3.3V, 4K Ref.)

-K4E151612D-J(T) (3.3V, 1K Ref.)

• Active Power Dissipation					Unit : mW
Speed		3.3V			5V
	4K		1K	4K		1K
-45	360		540	550		825
-50	324		504	495		770
-60	288		468	440		715

• Extended Data Out Mode operation

(Fast Page Mode with Extended Data Out)

•2 CAS Byte/Word Read/Write operation

•CAS-before-RAS refresh capability

•RAS-only and Hidden refresh capability

•Self-refresh capability (L-ver only)

•TTL(5V)/LVTTL(3.3V) compatible inputs and outputs

•Early Write or output enable controlled write

•JEDEC Standard pinout

•Available in plastic SOJ 400mil and TSOP(II) packages

•Single +5V±10% power supply (5V product)

•Single +3.3V±0.3V power supply (3.3V product)

•	Refresh Cycles
	Part		VCC		Refresh	Refresh period
	NO.				cycle
						Nor-		L-ver
	K4E171611D		5V		4K	64ms
	K4E171612D		3.3V					128ms
	K4E151611D		5V		1K	16ms
	K4E151612D		3.3V
•	Performance Range
	Speed	tRAC	tCAC		tRC	tHPC		Remark
	-45	45ns	13ns		69ns	16ns		5V/3.3V
	-50	50ns	15ns		84ns	20ns		5V/3.3V
	-60	60ns	17ns		104ns	25ns		5V/3.3V

FUNCTIONAL BLOCK DIAGRAM

RAS											Vcc
UCAS			Control
											Vss
LCAS			Clocks		VBB Generator
W

				Lower
				Data in	DQ0
	Refresh Timer	Row Decoder		Buffer
					to
	Refresh Control		I/O	Lower	DQ7
				Data out
			&
		Memory Array		Buffer
			Amps
					OE
	Refresh Counter	1,048,576 x16		Upper
		Cells		Data in
			Sense
					DQ8
A0-A11	Row Address Buffer			Buffer
					to
(A0 - A9)*1				Upper
					DQ15
A0 - A7
				Data out
	Col. Address Buffer	Column Decoder
(A0 - A9)*1
				Buffer
Note) *1 : 1K Refresh

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

K4E171611D, K4E151611D
K4E171612D, K4E151612D	CMOS DRAM

			PIN CONFIGURATION			(Top Views)
	• K4E17(5)1611(2)D-J					• K4E17(5)1611(2)D-T
	VCC	1	42	VSS		VCC	1	44	VSS
	DQ0	2	41	DQ15		DQ0	2	43	DQ15
	DQ1	3	40	DQ14		DQ1	3	42	DQ14
	DQ2	4	39	DQ13		DQ2	4	41	DQ13
	DQ3	5	38	DQ12		DQ3	5	40	DQ12
						VCC	6	39	VSS
	VCC	6	37	VSS
						DQ4	7	38	DQ11
	DQ4	7	36	DQ11
						DQ5	8	37	DQ10
	DQ5	8	35	DQ10
						DQ6	9	36	DQ9
	DQ6	9	34	DQ9
						DQ7	10	35	DQ8
	DQ7	10	33	DQ8		N.C	11	34	N.C
	N.C	11	32	N.C		N.C	12	33	N.C
	N.C	12	31	LCAS
	W	13	30	UCAS		N.C	13	32	LCAS
	RAS	14	29	OE		W	14	31	UCAS
	*A11(N.C)	15	28	A9		RAS	15	30	OE
					*A11(N.C)		16	29	A9
	*A10(N.C)	16	27	A8
					*A10(N.C)		17	28	A8
	A0	17	26	A7
						A0	18	27	A7
	A1	18	25	A6
						A1	19	26	A6
	A2	19	24	A5
						A2	20	25	A5
	A3	20	23	A4		A3	21	24	A4
	VCC	21	22	VSS		VCC	22	23	VSS

*A10 and A11 are N.C for K4E151611(2)D(5V/3.3V, 1K Ref. product)

J : 400mil 42 SOJ

T : 400mil 50(44) TSOP II

Pin Name

Pin Function

A0 - A11

Address Inputs (4K Product)

A0 - A9

Address Inputs (1K Product)

DQ0 - 15

Data In/Out

VSS

Ground

Row Address Strobe

RAS

Upper Column Address Strobe

UCAS

Lower Column Address Strobe

LCAS

Read/Write Input

W

Data Output Enable

OE

VCC

Power(+5V)

Power(+3.3V)

N.C

No Connection

K4E171611D, K4E151611D
K4E171612D, K4E151612D								CMOS DRAM
	ABSOLUTE MAXIMUM RATINGS
	Parameter	Symbol				Rating				Units
				3.3V				5V
	Voltage on any pin relative to VSS	VIN,VOUT	-0.5	to	+4.6		-1.0	to	+7.0	V
	Voltage on VCC supply relative to VSS	VCC	-0.5	to	+4.6		-1.0	to	+7.0	V
	Storage Temperature	Tstg	-55	to	+150		-55	to	+150	°C
	Power Dissipation	PD		1				1		W
	Short Circuit Output Current	IOS Address		50				50		mA

*Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

	Parameter	Symbol		3.3V				5V		Units
			Min	Typ		Max	Min	Typ	Max
Supply Voltage		VCC	3.0	3.3		3.6	4.5	5.0	5.5	V
Ground		VSS	0	0		0	0	0	0	V
Input High Voltage		VIH	2.0	-		VCC+0.3*1	2.4	-	VCC+1.0*1	V
Input Low Voltage		VIL	-0.3*2	-		0.8	-1.0*2	-	0.8	V
*1	: VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2	: -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

	Max	Parameter	Symbol	Min	Max	Units
		Input Leakage Current (Any input 0≤VIN≤VIN+0.3V,	II(L)	-5	5	uA
		all other input pins not under test=0 Volt)
	3.3V	Output Leakage Current	IO(L)	-5	5	uA
		(Data out is disabled, 0V≤VOUT≤VCC)
		Output High Voltage Level(IOH=-2mA)	VOH	2.4	-	V
		Output Low Voltage Level(IOL=2mA)	VOL	-	0.4	V
		Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,	II(L)	-5	5	uA
		all other input pins not under test=0 Volt)
	5V	Output Leakage Current	IO(L)	-5	5	uA
		(Data out is disabled, 0V≤VOUT≤VCC)
		Output High Voltage Level(IOH=-5mA)	VOH	2.4	-	V
		Output Low Voltage Level(IOL=4.2mA)	VOL	-	0.4	V

K4E171611D, K4E151611D
K4E171612D, K4E151612D								CMOS DRAM
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol	Power	Speed				Max			Units
				K4E171612D	K4E151612D		K4E171611D	K4E151611D
		-45		100	150		100	150	mA
ICC1	Don′t care	-50		90	140		90	140	mA
		-60		80	130		80	130	mA
ICC2	Normal	Don′t care		1	1		2	2	mA
	L			1	1		1	1	mA
		-45		100	150		100	150	mA
ICC3	Don′t care	-50		90	140		90	140	mA
		-60		80	130		80	130	mA
		-45		110	110		110	110	mA
ICC4	Don′t care	-50		100	100		100	100	mA
		-60		90	90		90	90	mA
ICC5	Normal	Don′t care		0.5	0.5		1	1	mA
	L			200	200		200	200	uA
		-45		100	150		110	150	mA
ICC6	Don′t care	-50		90	140		90	140	mA
		-60		80	130		80	130	mA
ICC7	L	Don′t care		300	200		350	250	uA
ICCS	L	Don′t care		150	150		200	200	uA

ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)

ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)

ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)

ICC4* : Hyper Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.)

ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)

ICC6* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @tRC=min.)

ICC7 : Battery back-up current, Average power supply current, Battery back-up mode

Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V,

DQ=Don′t care, TRC=31.25us(4K/L-ver), 125us(1K/L-ver)

TRAS=TRASmin~300ns

ICCS : Self Refresh Current

RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,

DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open

*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Hyper page mode cycle time, tHPC.

K4E171611D, K4E151611D

K4E171612D, K4E151612D

CMOS DRAM

CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)

Parameter

Symbol

Min

Max

Units

Input capacitance [A0 ~ A11]

CIN1

-

5

pF

Input capacitance

CIN2

-

7

pF

[RAS,

UCAS,

LCAS,

W,

OE]

Output capacitance [DQ0 - DQ15]

CDQ

-

7

pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)

Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V

Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

					Parameter												Symbol	-45				-50			-60		Units	Notes
																		Min		Max	Min		Max	Min		Max
	Random read or write cycle time																tRC	79			84			104			ns
	Read-modify-write cycle time																tRWC	105			115			140			ns
	Access time from																tRAC			45			50			60	ns	3,4,10
						RAS
	Access time from																tCAC			14			15			17	ns	3,4,5
						CAS
	Access time from column address																tAA			23/*20			25			30	ns	3,10
			to output in Low-Z														tCLZ	3			3			3			ns	3
	CAS
	Output buffer turn-off delay from																tCEZ	3		13	3		13	3		15	ns	6,19
												CAS
		to output in Low-Z															tOLZ	3			3			3			ns	3
	OE
	Transition time (rise and fall)																tT	2		50	2		50	2		50	ns	2
			precharge time														tRP	30			30			40			ns
	RAS
			pulse width														tRAS	45		10K	50		10K	60		10K	ns
	RAS
			hold time														tRSH	13			13			17			ns
	RAS
			hold time														tCSH	36			40			50			ns
	CAS
			pulse width														tCAS	7 / *6.5		10K	8		10K	10		10K	ns	18
	CAS
			to		delay time												tRCD	19		31	20		35	20		43	ns	4
	RAS			CAS
			to column address delay time														tRAD	14		22	15		25	15		30	ns	10
	RAS
			to		precharge time												tCRP	5			5			5			ns
	CAS			RAS
	Row address set-up time																tASR	0			0			0			ns
	Row address hold time																tRAH	9			10			10			ns
	Column address set-up time																tASC	0			0			0			ns	11
	Column address hold time																tCAH	7			8			10			ns	11
	Column address to										lead time						tRAL	23			25			30			ns
								RAS
	Read command set-up time																tRCS	0			0			0			ns
	Read command hold time referenced to																tRCH	0			0			0			ns	8
															CAS
	Read command hold time referenced to																tRRH	0			0			0			ns	8
														RAS
	Write command hold time																tWCH	8			10			10			ns
	Write command pulse width																tWP	8			10			10			ns
	Write command to									lead time							tRWL	10			13			15			ns
							RAS
	Write command to									lead time							tCWL	7			8			10			ns	14
							CAS

* KM416C1204DT-45 (5V, 1K Refresh) only

K4E171611D, K4E151611D
K4E171612D, K4E151612D																																																						CMOS DRAM
	AC CHARACTERISTICS (Continued)
																	Parameter																												Symbol	-45				-50			-60		Units	Notes
																																														Min		Max	Min		Max	Min		Max
		Data set-up time																																											tDS	0			0			0			ns	9,17
		Data hold time																																											tDH	7			8			10			ns	9,17
		Refresh period (1K, Normal)																																											tREF			16			16			16	ms
		Refresh period (4K, Normal)																																											tREF			64			64			64	ms
		Refresh period (L-ver)																																											tREF			128			128			128	ms
		Write command set-up time																																											tWCS	0			0			0			ns	7
						to			delay time																																				tCWD	28			32			36			ns	7,13
		CAS						W
						to			delay time																																				tRWD	59			67			79			ns	7
		RAS						W
		Column address																		delay time																									tAWD	37			42			49			ns	7
													W
						precharge to																		delay time																					tCPWD	39			47			54			ns	7
			CAS															W
						set-up time																						-before-												refresh)					tCSR	5			5			5			ns	15
		CAS														(CAS																			RAS
						hold time																		-before-														refresh)							tCHR	10			10			10			ns	16
		CAS										(CAS																						RAS
						to					precharge time																																		tRPC	5			5			5			ns
		RAS						CAS
		Access time from																										precharge																	tCPA			25			28			35	ns	3
																	CAS
		Hyper Page mode cycle time																																											tHPC	18			20			25			ns	18
		Hyper Page read-modify-write cycle time																																											tHPRWC	39			47			56			ns	18
						precharge time (Hyper Page cycle)																																							tCP	7 / *6.5			8			10			ns	12
		CAS
						pulse width (Hyper Page cycle)																																							tRASP	45		200K	50		200K	60		200K	ns
		RAS
						hold time from																									precharge														tRHCP	27			30			35			ns
		RAS																			CAS
					access time																																								tOEA			13			13			15	ns	3
		OE
					to data delay																																								tOED	10			13			15			ns
		OE
		Output buffer turn off delay time from																																											tOEZ	3		13	3		13	3		15	ns	6
																																										OE
					command hold time																																								tOEH	10			13			15			ns
			OE
		Output data hold time																																											tDOH	4			5			5			ns
		Output buffer turn off delay from																																											tREZ	3		13	3		13	3		15	ns	6,19
																																					RAS
		Output buffer turn off delay from																																											tWEZ	3		13	3		13	3		15	ns	6
																																				W
				to data delay																																									tWED	15			15			15			ns
			W
					to					hold time																																			tOCH	5			5			5			ns
		OE					CAS
						hold time to																																							tCHO	5			5			5			ns
		CAS													OE
					precharge time																																								tOEP	5			5			5			ns
		OE
				pulse width (Hyper Page Cycle)																																									tWPE	5			5			5			ns
		W
																				-B-										self refresh)															tRASS	100			100			100			us	20,21,22
		RAS				pulse width (C																						R
																													-B-				self refresh)												tRPS	79			90			110			ns	20,21,22
		RAS				precharge time (C																										R
														-B-												self refresh)																			tCHS	-50			-50			-50			ns	20,21,22
		CAS				hold time (C																R
	* KM416C1204DT-45 (5V, 1K Refresh) only

K4E171611D, K4E151611D
K4E171612D, K4E151612D	CMOS DRAM

NOTES

1.An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved.

2.Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.

3.Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.

4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.

5.Assumes that tRCD³tRCD(max).

6.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

7.tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS³tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD³tCWD(min), tRWD³tRWD(min), tAWD³tAWD(min) and tCPWD³tCPWD(min), then the cycle is a read- modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate.

8.Either tRCH or tRRH must be satisfied for a read cycle.

9.These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles.

10.Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

K4E17(5)1611(2)D Truth Table

RAS	LCAS	UCAS	W	OE	DQ0 - DQ7	DQ8-DQ15	STATE
H	X	X	X	X	Hi-Z	Hi-Z	Standby
L	H	H	X	X	Hi-Z	Hi-Z	Refresh
L	L	H	H	L	DQ-OUT	Hi-Z	Byte Read
L	H	L	H	L	Hi-Z	DQ-OUT	Byte Read
L	L	L	H	L	DQ-OUT	DQ-OUT	Word Read
L	L	H	L	H	DQ-IN	-	Byte Write
L	H	L	L	H	-	DQ-IN	Byte Write
L	L	L	L	H	DQ-IN	DQ-IN	Word Write
L	L	L	H	H	Hi-Z	Hi-Z	-

K4E171611D, K4E151611D
K4E171612D, K4E151612D	CMOS DRAM

11.tASC, tCAH are referenced to the earlier CAS falling edge.

12.tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.

13.tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.

14.tCWL is specified from W falling edge to the earlier CAS rising edge.

15.tCSR is referenced to the earlier CAS falling edge before RAS transition low.

16.tCHR is referenced to the later CAS rising edge after RAS transition low.

RAS

LCAS

UCAS

tCSR tCHR

17.tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)

18.tASC³6ns, assume tT=2.0ns.

19.If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going.

20.If tRASS³100us, then RAS precharge time must use tRPS instead of tRP.

21.For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed within 64ms/16ms before and after self refresh, in order to meet refresh specification.

22.For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.

K4E171611D, K4E151611D
K4E171612D, K4E151612D	CMOS DRAM
WORD READ CYCLE

				tRC	tRP
VIH -				tRAS
RAS
VIL -
	tCRP			tCSH	tCRP
			tRCD	tRSH
VIH -				tCAS
UCAS
VIL -
	tCRP			tCSH	tCRP
			tRCD	tRSH
VIH -				tCAS
LCAS
VIL -
			tRAD	tRAL
	tASR	tRAH	tASC
				tCAH
VIH -	ROW			COLUMN
A
	ADDRESS			ADDRESS
VIL -
			tRCS		tRCH
					tRRH
VIH -
W
VIL -
				tAA
VIH -				tOLZ
				tOEA
OE
VIL -
				tCAC	tCEZ
DQ0 ~ DQ7			tRAC	tCLZ	tOEZ
VOH -		OPEN			DATA-OUT
VOL -
				tCAC	tCEZ
DQ8 ~ DQ15			tRAC	tCLZ	tOEZ
VOH -
		OPEN			DATA-OUT
VOL -

Don′t care

Undefined

K4E171611D, K4E151611D
K4E171612D, K4E151612D	CMOS DRAM

LOWER BYTE READ CYCLE

NOTE : DIN = OPEN

				tRC
				tRAS	tRP
VIH -
RAS
VIL -
	tCRP				tRPC
VIH -
UCAS
VIL -
	tCRP			tCSH
			tRCD	tRSH
VIH -				tCAS
LCAS
VIL -			tRAD
	tASR	tRAH	tASC	tRAL
				tCAH
VIH -	ROW			COLUMN
A
	ADDRESS			ADDRESS
VIL -
			tRCS		tRCH
					tRRH
VIH -
W
VIL -					tCEZ
				tAA	tOEZ
VIH -				tOEA
OE
VIL -
				tCAC
DQ0 ~ DQ7			tRAC	tCLZ
VOH -		OPEN			DATA-OUT
VOL -

tOLZ

DQ8 ~ DQ15

VOH -

OPEN

VOL -

Don′t care

Undefined

K4E171611D, K4E151611D
K4E171612D, K4E151612D	CMOS DRAM

UPPER BYTE READ CYCLE

NOTE : DIN = OPEN

				tRAS	tRC	tRP
VIH -
RAS
VIL -				tCSH
	tCRP
			tRCD		tRSH	tCRP
VIH -					tCAS
UCAS
VIL -
	tCRP					tRPC
VIH -
LCAS			tRAD
VIL -
					tRAL
	tASR	tRAH	tASC	tCAH
VIH -	ROW			COLUMN
A
	ADDRESS			ADDRESS
VIL -
			tRCS			tRCH
						tRRH
VIH -
W
VIL -						tCEZ
				tAA
						tOEZ
VIH -					tOEA
OE
VIL -
DQ0 ~ DQ7					tOLZ
VOH -					OPEN
VOL -
				tCAC
DQ8 ~ DQ15			tRAC	tCLZ
VOH -		OPEN				DATA-OUT
VOL -

Don′t care

Undefined