K4D263238E-GC |
128M GDDR SDRAM |
128Mbit GDDR SDRAM
1M x 32Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
with Bi-directional Data Strobe and DLL (144-Ball FBGA)
Revision 1.7
November 2003
Samsung Electronics reserves the right to change products or specification without notice.
- 1 - |
Rev 1.7 (Nov. 2003) |
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K4D263238E-GC |
128M GDDR SDRAM |
Revision History
Revision 1.7 (November 14, 2003)
• Typo corrected
Revision 1.6 (August 14, 2003)
• Added a note for the input reference voltage of clock in case of differential clocks
Revision 1.5 (August 11, 2003)
• Typo corrected
Revision 1.4 (April 30, 2003)
• Added Lead free package part number in the datasheet
Revision 1.3 (April 14, 2003)
• K4D263238E-GC2A/33/36 support wide voltage range from 2.375V to 2.94V
Revision 1.2 (April 7, 2003)
• Removed K4D263238E-GL36 from the spec.
Revision 1.1 (March 17, 2003)
• Typo corrected
Revision 1.0 (February 13, 2003)
•Defined DC spec
•Added K4D263238E-GC25 and K4D263238E-GL36 in the spec.
- 2 - |
Rev 1.7 (Nov. 2003) |
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K4D263238E-GC |
128M GDDR SDRAM |
1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL
FEATURES
•VDD/VDDQ = 2.8V ± 5% for -GC25
•VDD/VDDQ = 2.5V ± 5% for -GC2A/33/36/40/45
•SSTL_2 compatible inputs/outputs
•4 banks operation
•MRS cycle with address key programs
-. Read latency 3, 4, 5 (clock)
-. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave)
•Full page burst length for sequential burst type only
•Start address of the full page burst should be even
•All inputs except data & DM are sampled at the positive going edge of the system clock
•Differential clock input
•No Wrtie-Interrupted by Read Function
•4 DQS’s ( 1DQS / Byte )
•Data I/O transactions on both edges of Data strobe
•DLL aligns DQ and DQS transitions with Clock transition
•Edge aligned data & data strobe output
•Center aligned data & data strobe input
•DM for write masking only
•Auto & Self refresh
•32ms refresh period (4K cycle)
•144-Ball FBGA
•Maximum clock frequency up to 400MHz
•Maximum data rate up to 800Mbps/pin
ORDERING INFORMATION
Part NO. |
Max Freq. |
Max Data Rate |
Interface |
Package |
K4D263238E-GC25 |
400MHz |
800Mbps/pin |
SSTL_2 |
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(VDD/VDDQ=2.8V) |
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K4D263238E-GC2A |
350MHz |
700Mbps/pin |
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K4D263238E-GC33 |
300MHz |
600Mbps/pin |
SSTL_2 |
144-Ball FBGA |
K4D263238E-GC36 |
275MHz |
550Mbps/pin |
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(VDD/VDDQ=2.5V) |
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K4D263238E-GC40 |
250MHz |
500Mbps/pin |
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K4D263238E-GC45 |
222MHz |
444Mbps/pin |
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K4D263238E-VC is the Lead Free package part number.
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238E is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 3.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
- 3 - |
Rev 1.7 (Nov. 2003) |
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K4D263238E-GC |
128M GDDR SDRAM |
PIN CONFIGURATION (Top View)
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2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
B |
DQS0 |
DM0 |
VSSQ |
DQ3 |
DQ2 |
DQ0 |
DQ31 |
DQ29 |
DQ28 |
VSSQ |
DM3 |
DQS3 |
C |
DQ4 |
VDDQ |
NC |
VDDQ |
DQ1 |
VDDQ |
VDDQ |
DQ30 |
VDDQ |
NC |
VDDQ |
DQ27 |
D |
DQ6 |
DQ5 |
VSSQ |
VSSQ |
VSSQ |
VDD |
VDD |
VSSQ |
VSSQ |
VSSQ |
DQ26 |
DQ25 |
E |
DQ7 |
VDDQ |
VDD |
VSS |
VSSQ |
VSS |
VSS |
VSSQ |
VSS |
VDD |
VDDQ |
DQ24 |
F |
DQ17 |
DQ16 |
VDDQ |
VSSQ |
VSS |
VSS |
VSS |
VSS |
VSSQ |
VDDQ |
DQ15 |
DQ14 |
Thermal |
Thermal |
Thermal |
Thermal |
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G |
DQ19 |
DQ18 |
VDDQ |
VSSQ |
VSS |
VSS |
VSS |
VSS |
VSSQ |
VDDQ |
DQ13 |
DQ12 |
Thermal |
Thermal |
Thermal |
Thermal |
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H |
DQS2 |
DM2 |
NC |
VSSQ |
VSS |
VSS |
VSS |
VSS |
VSSQ |
NC |
DM1 |
DQS1 |
Thermal |
Thermal |
Thermal |
Thermal |
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J |
DQ21 |
DQ20 |
VDDQ |
VSSQ |
VSS |
VSS |
VSS |
VSS |
VSSQ |
VDDQ |
DQ11 |
DQ10 |
Thermal |
Thermal |
Thermal |
Thermal |
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K |
DQ22 |
DQ23 |
VDDQ |
VSSQ |
VSS |
VSS |
VSS |
VSS |
VSSQ |
VDDQ |
DQ9 |
DQ8 |
L |
CAS |
WE |
VDD |
VSS |
A10 |
VDD |
VDD |
RFU1 |
VSS |
VDD |
NC |
NC |
M |
RAS |
NC |
NC |
BA1 |
A2 |
A11 |
A9 |
A5 |
RFU2 |
CK |
CK |
MCL |
N |
CS |
NC |
BA0 |
A0 |
A1 |
A3 |
A4 |
A6 |
A7 |
A8/AP |
CKE |
VREF |
NOTE:
1.RFU1 is reserved for A12
2.RFU2 is reserved for BA2
3.VSS Thermal balls are optional
PIN DESCRIPTION
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CK,CK |
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Differential Clock Input |
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BA0, BA1 |
Bank Select Address |
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CKE |
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Clock Enable |
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A0 ~A11 |
Address Input |
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Chip Select |
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DQ0 ~ DQ31 |
Data Input/Output |
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CS |
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Row Address Strobe |
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VDD |
Power |
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RAS |
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Column Address Strobe |
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VSS |
Ground |
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CAS |
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WE |
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Write Enable |
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VDDQ |
Power for DQ’s |
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DQS |
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Data Strobe |
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VSSQ |
Ground for DQ’s |
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DM |
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Data Mask |
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NC |
No Connection |
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RFU |
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Reserved for Future Use |
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MCL |
Must Connect Low |
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- 4 - Rev 1.7 (Nov. 2003)
K4D263238E-GC |
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128M GDDR SDRAM |
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INPUT/OUTPUT FUNCTIONAL DESCRIPTION |
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Symbol |
Type |
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Function |
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The differential system clock Input. |
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CK, |
CK*1 |
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All of the inputs are sampled on the rising edge of the clock except |
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DQ’s and DM’s that are sampled on both edges of the DQS. |
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Activates the CK signal when high and deactivates the |
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signal |
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CK |
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CKE |
Input |
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when low. By deactivating the clock, CKE low indicates the Power |
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down mode or Self refresh mode. |
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enables the command decoder when low and disabled the com- |
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CS |
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CS |
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Input |
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mand decoder when high. When the command decoder is disabled, |
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new commands are ignored but previous operations continue. |
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Input |
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Latches row addresses on the positive going edge of the CK with |
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RAS |
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RAS low. Enables row access & precharge. |
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Latches column addresses on the positive going edge of the CK with |
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CAS |
Input |
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CAS low. Enables column access. |
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Enables write operation and row precharge. |
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WE |
Input |
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Latches data in starting from CAS, WE active. |
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Data input and output are synchronized with both edge of DQS. |
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DQS0 ~ DQS3 |
Input/Output |
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DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23, |
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DQS3 for DQ24 ~ DQ31. |
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Data In mask. Data In is masked by DM Latency=0 when DM is high |
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DM0 ~ DM3 |
Input |
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in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for |
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DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. |
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DQ0 ~ DQ31 |
Input/Output |
Data inputs/Outputs are multiplexed on the same pins. |
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BA0, BA1 |
Input |
Selects which bank is to be active. |
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Row/Column addresses are multiplexed on the same pins. |
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A0 ~ A11 |
Input |
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Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7. |
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Column address CA8 is used for auto precharge. |
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VDD/VSS |
Power Supply |
Power and ground for the input buffers and core logic. |
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VDDQ/VSSQ |
Power Supply |
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Isolated power supply and ground for the output buffers to provide |
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improved noise immunity. |
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VREF |
Power Supply |
Reference voltage for inputs, used for SSTL interface. |
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NC/RFU |
No connection/ |
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This pin is recommended to be left "No connection" on the device |
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Reserved for future use |
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MCL |
Must Connect Low |
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Must connect low |
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*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
- 5 - |
Rev 1.7 (Nov. 2003) |
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K4D263238E-GC |
128M GDDR SDRAM |
BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank)
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32 |
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Intput Buffer |
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CK, |
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CK |
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Data Input Register |
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Bank Select |
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Serial to parallel |
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64
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Address |
BufferRow |
CounterRefresh |
DecoderRow |
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1Mx32 |
AMPSense |
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1Mx32 |
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1Mx32 |
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CK,CK |
Register |
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1Mx32 |
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ADDR |
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Column Decoder |
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LRAS |
LCBR |
Buffer.Col |
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Latency & Burst Length |
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LCKE |
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Programming Register |
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LCBR |
LWE |
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LRAS |
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LCAS |
LWCBR |
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Timing Register |
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64 |
bit-2 |
32 |
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prefetch |
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DLL
CK,CK
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I/O |
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LWE |
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Control |
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LDMi |
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Output |
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x32 |
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Buffer |
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DQi |
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Strobe .Gen |
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(DQS0~DQS3) |
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Data Strobe |
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LDMi
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CK,CK CKE |
CS |
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RAS CAS |
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WE |
DMi |
- 6 - |
Rev 1.7 (Nov. 2003) |
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