Samsung Q10 Schematic

4
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PROPRIETARY INFORMATION THAT IS
PROPRIETARY INFORMATION THAT IS
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4
3
3
2
12 1
D
D
1.
2.
D
D
3.
4.
5.
6.
CETUS
7.
8.
9.
10.
11.
CPU :
BANIAS LV
12.
13.
C
C
Chip Set : Remarks :
855GM
14.
15.
16.
C
C
17.
18.
19.
20.
21.
Model Name : PCB Code : Dev. Step :
B
B
Revision : T.R. Date :
CETUS Main BA41-xxxxxx MP
0.5
2003. 4. 24
22.
23.
24.
25.
26.
27.
28.
29.
30.
B
B
31.
DRAW
WS JUNG
A
A
4
4
CHECK
HJ KIM
APPROVAL
Kevin
3
3
A
A
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D
4
Docking
CRT
SPDIF
B
RJ-45(10/100)
FDD/ODD /2ND HDD
(FACTORY OPTION)
1394 (port 1)
A
Clocking
Clock generator
RJ-11
SPKR
HP JACK
MIC JACK
RJ-45(10/100)
LAN switch
p24
p24
p23
p23
p24
AMP
p4
LCD
CRT
MDC
CS4202
LOM
KINNERITH+ 82562EZ
1394 (port 0)
p20
EEPROM
p20
THERMISTER
ADM1032
p19
p19
#1
p24
#0
p24
EEPROM
p22
3
p5
AC LINK
(AC97 2.2)
p22
CardBus +
1394 Lynx+PHY
R5C591
p20,p21
GMCH-M
855GM
p7,p8,p9,p10
ICH4 - M
82801 DBM 1.5V
p15,p16,p17
PCI BUS
CPU
BaniasLV
400MHZ (100MHZ, 4*)
(1.2V)
HI 1.5
Mini PCI
CONN
p30
WLAN/Bluetooth
p5,p6
266DDR
USB
LPC
2
IDE0
FWH
p18
82802A
MICOM
Hitachi 2160
p25
87391
p29
HDD
p28
On Board
256MB/128MB
p11,p13,p14
SODIMM
Max 1GB
p12
USB (port 1)
BLUETOOTH
port3
Internal KBD
p29
Touch Pad
p29
FIR(Option)
p29
p30
p28
1
D
Docking
CC
2 USB (port4,5)
PS/2
B
SIO
PIO
A
SAMSUNG
SD(MMC) + MS
4
3
CARD BUS
p21 p21
2
1
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SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
PCI Devices
Devices IDSEL# Cardbus
LAN MiniPCI SLOT1 BANIAS/MGM Processor System Bus(PSB) Termination (1.05V)VCCP USB
Hub to PCI LPC bridge/IDE/AC97/SMBUS AGP Internal MAC AC Link - B-
I2 C / SMB Address
C
Devices
ICH4M
SODIMM0
MICOM Master - SMBUS Master
ADM1032 Battery 0001 011x 16h System Battery
USB PORT Assign
B
PORT NUMBER ASSIGNED TO 0
1 2 3 4 5
SYSTEM PORT LEFT SYSTEM PORT RIGHT Docking BLUETOOTH Docking Docking
POWER
MICOM_P3V
MICOM ICH4
A
P5V_AUX
ICH4
P3.3V_AUX
MINI-PCI MDC
P2.5V_AUX
MGM SODIMM
AD19 AD21 AD20 AD29(internal)
AD30(internal) AD31(internal) AD17(internal) AD24(internal)
Address
Master
1010 001x
0100 110x
P1.5V_AUX
ICH4
REQ/GNT# 0
1 2
-
-
-
-
-
Hex
-
A2h
4Ch
P3.3V P5VP1.8V
CPU 5C591
5C591 MINI-PCI
SODIMM MICOM S/IO FWH HDD HDD
FIR CLOCK THERMISTER
BLUETOOTH
Interrupts A,B,C
D E,F
USB2.0 : H
#0 : A #1 : D #2 : C
­B A,B E
Bus
SMBUS Master
Clock, Unused Clock Output DisableD2hCK-408 (Clock Generator) 1101 001x
­Photo snesor72hTSL2550 0111 001x
Thermal Sensor ( CPU )
P1.5V VCCP
MGM ICH4
ICH4 5C591
MINI-PCI STAC9750
MDC MICOM
VCC_CORE
CPU
CPUICH4 MGM
VCC_MCH
CPU MGM
Voltage Rails
VDC VCC_CORE
P1.5V P1.8V P2.5V
P2.5V_AUX P1.25V MICOM_P3V P3.3V P3.3V_AUX
P5V P5V_AUX
Primary DC system power supply (9 to 12V) Core voltage for BANIAS CPU (1.356 - 0.844V)
MCH-M Core Voltage (1.2V)VCC_MCH
1.5V switched power rail (off in S3-S5)
1.8V switched power rail (off in S3-S5)
2.5V switched power rail (off in S3-S5)
2.5V power rail (off in S4-S5)
1.25V power rail (off in S4-S5)
3.3V always on power rail for MICOM
3.3V switched power rail (off in S3-S5)
3.3V power rail (off in S4-S5)
5.0V switched power rail (off in S3-S5)
5.0V power rail ( off in S4-S5)
CPU Core Voltage Table
VID4 VoltageVID3 VID2 VID1 VID0
VID5 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Highest Freq.
0
0
0
1
0
1
0
1
0
1
0
1
0
1 1
0
1
1
0
­1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Low Voltage CPU
- Vcc (HFM = 1.1/1.2GHz) = 1.180V
- Vcc (LFM = 600MHz) = 0.956V
- 100MHz Geyserville III steps supported
- GV III points for LV Banias 1.1/1.2GHz = 600MHz, 800MHz, 900MHz, 1GHz, 1.1/1.2GHz
- 700MHz point not supported
- TDP = 12W, Iccmax = 12A
0
0
0
0
0
0
1
0
0
1
0
0 0
0
1
0
0
1
0
1
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
1 0
1
0
1
1
1
1
1
1
1
1
0
0
0 0
0
0 0
0
1
0
0
1
0
1
0
0
0
1
0
1
1
1
1
1
0 1
0
0 0
0
1 1
0
1
1
1
0
0
1
1
0
1
1 1
1
1 1
1
1
1.708 V
0
1.692 V
1 0
1.676 V
1
1.660 V
0
1.644 V
1.628 V
1 0
1.612 V
1
1.596 V
1 0
1.580 V
1.564 V
1 0
1.548 V
1.532 V
1
1.516 V
0
1.500 V
1 0
1.484 V
1
1.468 V
0
1.452 V
1.436 V
1 0
1.420 V
1
1.404 V
1.388 V
0
1.372 V
1
1.356 V
0
1.340 V
1
1 0
1.324 V
1.308 V
1 0
1.292 V
1
1.276 V
1.260 V
0
1.244 V
1 0
1.228 V
1.212 V
1
5C591
VID5 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
VID20VID0
VID41VID30VID1 0
0
0 0 0 0 0 0 0 0
­0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
0
0
0
0
0
0
1
0
1
0 1
0
0
0
0
1 1
0
1
0
1
1
1
1­0
1
0
1
0
0 0
1
1
0
1
1
1
0
1
1
0
1 1
1
1
1
1
1 0
0
0
0
0
0 0
0
1
0
0
1
1
0
0
00
1
0
1
0
1 1
1
0
1
1 0
1
0
1
0
0 0
1
1
1
0
1
1
0
1
1
0
1 1
1
1
1
1
1
Ultra Low Voltage CPU
- Vcc (HFM = 900MHz) = 1.004V
- Vcc (LFM = 600MHz) = 0.844V
- 100MHz Geyserville III steps supported
- GV III points for LV Banias 1.1GHz = 600MHz, 800MHz, 900MHz
- 700MHz point not supported
- TDP = 7W, Iccmax = 9A
DD
C
Voltage
0
1.196 V Low Voltage Banias
1.180 V
1 0 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1.164 V
1.148 V
1.132 V
1.116 V
1.100 V
1.084 V
1.068 V
1.052 V
1.036 V
1.020 V
1.004 V
0.988 V
0.972 V
0.956 V
0.940 V
0.924 V
0.908 V
0.892 V
0.876 V
0.860 V
0.844 V
0.828 V
0.812 V
0.796 V
0.780 V
0.764 V
0.748 V
0.732 V
0.716 V
0.700 V
VCC (HFM = 1.1/1.2GHz)
Ultra Low Voltage Banias VCC (HFM = 900MHz)
Low Voltage Banias VCC (LFM = 600MHz)
Ultra Low Voltage Banias VCC (LFM = 600MHz)
Deeper Sleep
B
A
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HCB3216K-601T20
Be sure to follow A/W guide line!
CHP3_CPUSTP*
CHP3_PCISTP*
CHP3_SLPS1*
SMB3_CLK
C
IMVP4_PWRGD
B B
SMB3_DATA
CLK_CPU*
CLK_CPU
CLK_MCH*
CLK_MCH
CLK_CPUITP*
CLK_CPUITP
682088
Close to chip
CLK3_DREFSSCLK
CLK3_ICH66 CLK3_MCH66
CLK3_PCLKICH
CLK3_PCLKCB CLK3_PCLKFWH
CLK3_PCLKSIO CLK3_PCLKMICOM CLK3_PCLKMIN
CLK3_DREF CLK3_ICH48
CLK3_ICH14 CLK3_SIO14
48Mhz
D
C
A
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DD
CPU1_A*(16:3)
C
CPU1_ADSTB0*
CPU1_REQ*(4:0)
CPU1_A*(31:17)
CPU1_ADSTB1*
CPU1_ADS* CPU1_BNR* CPU1_BPRI* CPU1_BREQ*
CPU1_DBSY* CPU1_DEFER* CPU1_DRDY*
CPU1_HIT* CPU1_HITM*
CPU1_INIT* CPU1_DSTBP0* CPU1_LOCK* CPU1_TRDY*
CPU1_CPURST* CPU1_RS2* CPU1_RS1* CPU1_RS0*
CPU1_A20M*
CPU1_FERR*
CPU1_IGNNE*
CPU1_INTR CPU1_NMI CPU1_SMI* CPU1_STPCLK*
B
KBC3_THERM_SMCLK CPU2_THERMDA
KBC3_THERM_SMDATA
CPU1_D*(15:0)
CPU1_DSTBN0*
CPU1_D*(31:16)
CPU1_DBI1* CPU1_DSTBN1* CPU1_DSTBP1*
CPU2_THERMDCSMB3_ALERT* CHP3_OVERT*
CPU1_D*(47:32)
CPU1_DBI2*CPU1_DBI0* CPU1_DSTBN2* CPU1_DSTBP2*
CPU1_D*(63:48)
CPU1_DBI3* CPU1_DSTBN3* CPU1_DSTBP3*
C
B
A
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D
CPU1_PWRGDCPU
CPU1_PROCHOT*
Placed as close as possible to each of the four VCCA pins.
CLK_CPU
CLK_CPU*
CLK_CPUITP
CLK_CPUITP*
CPU1_SLP*
CPU1_DPSLP*
CPU1_DPWR*
CPU3_VID(5:0)
3
2
1
D
CPU1_GTLREF0
C
GTLREF : Keep the Voltage divider within 0.5" of the First GTLREF0 with Z0= 55 ohm trace
Minimize coupling of any switching signals to this net
CPU1_PSI*
"ALL ITP I/F signals"
must have T.P.
PREQ,PRDY,BPM(0:3),TCK,TDI,TDO,TMS,TRST
"Mobile Platform Design Checklist rev. 0.94 page19"
220uF * 4, 10uF *35
B
220uF = 12mohm(Max/4) 3.5nH/4
10uF = 5mohm(typ/35) 0.6nH/4
CPU2_THERMDA CPU2_THERMDC
CPU1_THRMTRIP*
VOS-
TEST3 PSI*
STUFFING OPTION
COMP 0 , 2 <(COMP 1,3) should be connected Z0=27.4 ohm (55 ohm) trace shorter than 1/2 " to their respective Banias Pins
C
B
A
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D
Trace should be 10 mil,20mil spacing.
GMCH1_HYSWING
CPU1_A*(31:3)
3
CPU1_ADS* CPU1_TRDY* CPU1_DRDY* CPU1_DEFER* CPU1_HITM* CPU1_HIT* CPU1_LOCK* CPU1_BREQ* CPU1_BNR* CPU1_BPRI* CPU1_DBSY* CPU1_RS0* CPU1_RS1* CPU1_RS2*
CPU1_D*(63:0)
GMCH1_HAVREF
GMCH1_HCCVREF
12
D
C
GMCH1_HDVREF
C
Trace should be 10 mil,20mil spacing.
GMCH1_HXSWING
CPU1_REQ*(4:0)
CPU1_ADSTB0*
RCOMP reference voltage Routing : 10 mil trace, 20 mil space
CPURST* Length
GMCH-CPU : 1.0" ~ 6.0" GMCH-R-ITP : 12.0" max
A
CPU1_ADSTB1*
CLK_MCH*
CLK_MCH
GMCH1_HYSWING
GMCH1_HXSWING
CPU1_DSTBP0* CPU1_DSTBN0*
CPU1_DBI0* CPU1_DSTBP1* CPU1_DSTBN1*
CPU1_DBI1* CPU1_DSTBP2* CPU1_DSTBN2*
CPU1_DBI2* CPU1_DSTBP3* CPU1_DSTBN3*
CPU1_DBI3*
CPU1_CPURST*
GMCH1_HDVREF
GMCH1_HCCVREF
GMCH1_HAVREF
HUB1_HL(0:10)
HLZCOMP
HUB1_REF_GMCH GMCH1_PSWING
HUB1_STB* HUB1_STB
Checklist rev0.94
GMCH1_PSWING
HUB1_REF_GMCH
800mV +/- 8%
near component
350mV +/- 8%
near component
near divider
near divider
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D
MEM2_MD(63:0)
C
B
MEM2_DQS(7:0)
MEM2_MAA(12:0)
MEM2_CKE0 MEM2_CKE1 MEM2_CKE2
MEM2_CSA0* MEM2_CSA1* MEM2_CSA2*
MEM2_BS0 MEM2_BS1 MEM2_SRASA* MEM2_SCASA* MEM2_SWEA*
CLK2_MCLK0 CLK2_MCLK0* CLK2_MCLK1 CLK2_MCLK1*
CLK2_MCLK3 CLK2_MCLK3* CLK2_MCLK4 CLK2_MCLK4*
MEM2_DM(7:0)
MEM2_MAB(2:1)
MEM2_MAB(5:4)
SODIMM 0 SODIMM 0 On Board : 256MB
SODIMM 0 SODIMM 0 On Board : 256MB
SODIMM0
ON BOARD
GMCH1_SMRCOMP
GMCH1_SMVSWINGL
D
C
B
If ECC support is not implemented,
SDQ[71:64], SDM8, SDQS8 SCK2/2*, SCK5/5*, these signal are NC.
GMCH1_SMRCOMP GMCH1_SMVSWINGL GMCH1_SMVSWINGH
A
Used to measure timing for the read data Both signals should have vias located adjacent to the package
3
24
GMCH1_SMVSWINGH
A
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As short as possible
T-topology
VGA3_HSYNC VGA3_VSYNC
VGA3_DDCC VGA3_DDCD
VGA3_CLK­VGA3_CLK+ VGA3_A0­VGA3_A0+ VGA3_A1­VGA3_A1+ VGA3_A2­VGA3_A2+
CHP3_DCKIN*
DCK_VGA3_BLUE DCK_VGA3_GREEN DCK_VGA3_RED
VGA3_BLUE VGA3_GREEN VGA3_RED
C
DVO1_DPMS
CHP3_SUSCLK
VGA3_BKLTON VGA3_LCDVDDON
CLK3_DREF CLK3_DREFSSCLK
B
Place near GMCH
DVO1_DPMS
AGP3_BUSY*
CLK3_MCH66
-10mil wide
-20mil spacing
CPU1_DPWR* CPU1_DPSLP* PCI3_RST*
IMVP4_PWRGD
D
C
B
GST2
A
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124
D
C
VCCADPLLA VCCADPLLB
VCCADPLLA VCCADPLLB
Place two caps near MGM ACAP
B
D
C
B
VCCASM
VCCQSM
A
4
3
VCCQSM
VCCASM
2
A
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D
MEM2_RMAA(0)
MEM2_MAB(2:1)
MEM2_RMAA(3)
MEM2_MAB(5:4)
MEM2_RMAA(12:6)
3
D0
MEM2_RMD(15:0)
2
MEM2_RMAA(0) MEM2_MAB(2:1)
MEM2_RMAA(3) MEM2_MAB(5:4)
MEM2_RMAA(12:6)
D1
1
MEM2_RMD(31:16)
D
MEM2_RBS0
MEM2_RBS1 MEM2_RSWEA*
MEM2_RSCASA*
MEM2_CSA2* MEM2_RDM(1) MEM2_RDM(0)
MEM2_RDQS(1) MEM2_RDQS(0)
MEM2_CKE2
C
CLK2_MCLK3
CLK2_MCLK3*
Close to memory as you can!
MEM2_RMAA(0)
MEM2_MAB(2:1)
MEM2_RMAA(3)
MEM2_MAB(5:4)
MEM2_RMAA(12:6)
D2
MEM2_RMD(47:32)
B
MEM2_RBS0 MEM2_RBS1
MEM2_RSWEA* MEM2_RSCASA* MEM2_RSRASA*
MEM2_CSA2* MEM2_RDM(5) MEM2_RDM(4)
MEM2_RDQS(5) MEM2_RDQS(4)
MEM2_RBS0 MEM2_RBS1
MEM2_RSWEA* MEM2_RSCASA* MEM2_RSRASA*MEM2_RSRASA*
MEM2_CSA2* MEM2_RDM(3) MEM2_RDM(2)
MEM2_RDQS(3) MEM2_RDQS(2)
MEM2_CKE2
Close to memory as you can!
MEM2_RMAA(0) MEM2_MAB(2:1)
MEM2_RMAA(3) MEM2_MAB(5:4)
MEM2_RMAA(12:6)
MEM2_RBS0 MEM2_RBS1
MEM2_RSWEA* MEM2_RSCASA* MEM2_RSRASA*
MEM2_CSA2* MEM2_RDM(7) MEM2_RDM(6)
MEM2_RDQS(7) MEM2_RDQS(6)
C
D3
MEM2_RMD(63:48)
B
MEM2_CKE2
A
CLK2_MCLK4
CLK2_MCLK4*
4
Close to memory as you can!
3
MEM2_CKE2
Close to memory as you can!
2
A
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MEM2_MAA(0)
MEM2_MAA(2:1)
MEM2_MAA(3)
MEM2_MAA(5:4)
MEM2_MAA(12:6)
MEM2_BS0 MEM2_BS1
MEM2_MD(63:0)
C
CLK2_MCLK0 CLK2_MCLK0* CLK2_MCLK1*
CLK2_MCLK1
MEM2_CKE0 MEM2_CKE1
MEM2_SCASA* MEM2_SRASA*
MEM2_SWEA*
MEM2_CSA0*
MEM2_CSA1*
SMB3_CLK
SMB3_DATA
MEM2_DM(7:0)
B
MEM2_DQS(7:0)
D
C
B
P/N : 3709-001193
SMBUS Addr : 1010000X
A
SAMSUNG
SAMSUNG
ELECTRONICS
ELECTRONICS
4
3
2
1
A
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