SAMSUNG K4B2G0846D Technical data

”YNN MacshbM·Rev. 1.11, Nov. 2010

K4B2G0446D

K4B2G0846D

2Gb D-die DDR3 SDRAM

78FBGA with Lead-Free & Halogen-Free (RoHS compliant)

datasheet

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				Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet		DDR3 SDRAM
K4B2G0446D
Revision History
Revision No.	History	Draft Date	Remark	Editor
1.0	- First SPEC. Release	Aug. 2010	-	S.H.Kim
1.1	- Corrected IDD current spec.(IDD7)	Sep. 2010	-	S.H.Kim
1.11	- Corrected typo.	Nov. 2010	-	S.H.Kim

- 2 -

			Rev. 1.11
		”YNN MacshbM·
K4B2G0846D		datasheet	DDR3 SDRAM
K4B2G0446D
Table Of Contents
2Gb D-die DDR3 SDRAM
1. Ordering Information .....................................................................................................................................................			5
2. Key Features.................................................................................................................................................................			5
3. Package pinout/Mechanical Dimension & Addressing..................................................................................................			6
3.1 x4 Package Pinout (Top view) : 78ball FBGA Package ..........................................................................................			6
3.2 x8 Package Pinout (Top view) : 78ball FBGA Package ..........................................................................................			7
3.3	FBGA Package Dimension (x4/x8)..........................................................................................................................		8
4. Input/Output Functional Description..............................................................................................................................			9
5. DDR3 SDRAM Addressing ...........................................................................................................................................			10
6. Absolute Maximum Ratings ..........................................................................................................................................			11
6.1	Absolute Maximum DC Ratings...............................................................................................................................		11
6.2 DRAM Component Operating Temperature Range ................................................................................................			11
7. AC & DC Operating Conditions.....................................................................................................................................			11
7.1	Recommended DC operating Conditions (SSTL_1.5).............................................................................................		11
8. AC & DC Input Measurement Levels ............................................................................................................................			12
8.1	AC & DC Logic input levels for single-ended signals ..............................................................................................		12
8.2	VREF Tolerances......................................................................................................................................................		13
8.3	AC & DC Logic Input Levels for Differential Signals...............................................................................................		14
8.3.1. Differential signals definition ................................................................		............................................................	14
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) ..................................................			14
8.3.3. Single-ended requirements for differential signals ...........................................................................................			15
8.4	Differential Input Cross Point Voltage......................................................................................................................		16
8.5	Slew rate definition for Differential Input Signals .....................................................................................................		16
8.6	Slew rate definitions for Differential Input Signals ...................................................................................................		16
9. AC & DC Output Measurement Levels .........................................................................................................................			17
9.1	Single-ended AC & DC Output Levels.....................................................................................................................		17
9.2	Differential AC & DC Output Levels.........................................................................................................................		17
9.3	Single-ended Output Slew Rate ..............................................................................................................................		17
9.4	Differential Output Slew Rate ..................................................................................................................................		18
9.5	Reference Load for AC Timing and Output Slew Rate ............................................................................................		18
9.6	Overshoot/Undershoot Specification .......................................................................................................................		19
9.6.1. Address and Control Overshoot and Undershoot specifications......................................................................			19
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ......................................................			19
9.7	34ohm Output Driver DC Electrical Characteristics.................................................................................................		20
9.7.1. Output Drive Temperature and Voltage Sensitivity ..........................................................................................			21
9.8	On-Die Termination (ODT) Levels and I-V Characteristics .....................................................................................		21
9.8.1. ODT DC Electrical Characteristics ...................................................................................................................			22
9.8.2. ODT Temperature and Voltage sensitivity ......................................................................................................			23
9.9	ODT Timing Definitions ...........................................................................................................................................		24
9.9.1. Test Load for ODT Timings..............................................................................................................................			24
9.9.2. ODT Timing Definitions ....................................................................................................................................			24
10. IDD Current Measure Method.....................................................................................................................................			27
10.1 IDD Measurement Conditions ...............................................................................................................................			27
11. 2Gb DDR3 SDRAM D-die IDD Specification Table ....................................................................................................			36
12. Input/Output Capacitance ...........................................................................................................................................			37
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866......................................................................			38
13.1 Clock Specification ................................................................................................................................................			38
13.1.1. Definition for tCK(avg)....................................................................................................................................			38
13.1.2. Definition for tCK(abs)....................................................................................................................................			38
13.1.3. Definition for tCH(avg) and tCL(avg)..............................................................................................................			38
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) .................................................................................................			38
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) .................................................................................................................			38
13.1.6. Definition for tERR(nper)................................................................................................................................			38
13.2 Refresh Parameters by Device Density.................................................................................................................			39
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin .................................................................			39
13.3.1. Speed Bin Table Notes ..................................................................................................................................			43

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			Rev. 1.11
		”YNN MacshbM·
K4B2G0846D		datasheet	DDR3 SDRAM
K4B2G0446D
14. Timing Parameters by Speed Grade ..........................................................................................................................			44
14.1	Jitter Notes ............................................................................................................................................................		50
14.2	Timing Parameter Notes........................................................................................................................................		51
14.3	Address/Command Setup, Hold and Derating : ....................................................................................................		52
14.4	Data Setup, Hold and Slew Rate Derating : ..........................................................................................................		59

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								Rev. 1.11
	K4B2G0846D				”YNN MacshbM·
					datasheet		DDR3 SDRAM
	K4B2G0446D
	1. Ordering Information
	[ Table 1 ] Samsung 2Gb DDR3 D-die ordering information table
	Organization		DDR3-1066 (7-7-7)		DDR3-1333 (9-9-9)4	DDR3-1600 (11-11-11)3	DDR3-1866 (13-13-13)2	Package
	512Mx4		K4B2G0446D-HCF8		K4B2G0446D-HCH9	K4B2G0446D-HCK0	K4B2G0446D-HCMA	78 FBGA
	256Mx8		K4B2G0846D-HCF8		K4B2G0846D-HCH9	K4B2G0846D-HCK0	K4B2G0846D-HCMA	78 FBGA
	NOTE :

1.Speed bin is in order of CL-tRCD-tRP.

2.Backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)

3.Backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

4.Backward compatible to DDR3-1066(7-7-7)

2. Key Features

[ Table 2 ] 2Gb DDR3 D-die Speed bins

	Speed	DDR3-800	DDR3-1066	DDR3-1333	DDR3-1600	DDR3-1866	Unit
		6-6-6	7-7-7	9-9-9	11-11-11	13-13-13
	tCK(min)	2.5	1.875	1.5	1.25	1.07	ns
	CAS Latency	6	7	9	11	13	nCK
	tRCD(min)	15	13.125	13.5	13.75	13.91	ns
	tRP(min)	15	13.125	13.5	13.75	13.91	ns
	tRAS(min)	37.5	37.5	36	35	34	ns
	tRC(min)	52.5	50.625	49.5	48.75	47.91	ns

•JEDEC standard 1.5V ± 0.075V Power Supply

•VDDQ = 1.5V ± 0.075V

•400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin, 900MHz fCK for 1866Mb/sec/pin,

•8 Banks

•Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,12,13

•Programmable Additive Latency: 0, CL-2 or CL-1 clock

•Programmable CAS Write Latency (CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333), 8(DDR3-1600) and 9(DDR3-1866)

•8-bit pre-fetch

•Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]

•Bi-directional Differential Data-Strobe

•Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)

•On Die Termination using ODT pin

•Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C

•Asynchronous Reset

•Package : 78 balls FBGA - x4/x8

•All of Lead-Free products are compliant for RoHS

•All of products are Halogen-free

The 2Gb DDR3 SDRAM D-die is organized as a 64Mbit x 4 I/Os x 8banks or 32Mbit x 8 I/Os x 8banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1866Mb/sec/pin (DDR31866) for general applications.

The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset .

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ.

The 2Gb DDR3 D-die device is available in 78ball FBGAs(x4/x8).

NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing Diagram”.

2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.

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		Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet	DDR3 SDRAM
K4B2G0446D

3. Package pinout/Mechanical Dimension & Addressing

3.1 x4 Package Pinout (Top view) : 78ball FBGA Package

1

2

3

4

5

6

7

8

9

A

VSS

VDD

NC

NC

VSS

VDD

A

B

VSS

VSSQ

DQ0

DM

VSSQ

VDDQ

B

C

VDDQ

DQ2

DQS

DQ1

DQ3

VSSQ

C

D

VSSQ

NC

DQS

VDD

VSS

VSSQ

D

E

VREFDQ

VDDQ

NC

NC

NC

VDDQ

E

F

NC

VSS

RAS

CK

VSS

NC

F

G

ODT

VDD

CAS

CK

VDD

CKE

G

H

NC

CS

WE

A10/AP

ZQ

NC

H

J

VSS

BA0

BA2

NC

VREFCA

VSS

J

K

VDD

A3

A0

BA1

VDD

K

A12/BC

L

VSS

A5

A2

A1

A4

VSS

L

M

VDD

A7

A9

A11

A6

VDD

M

N

VSS

RESET

A13

A14

A8

VSS

N

1

2

3

4

5

6

7

8

9

Ball Locations (x4)				A
				B
				C
			Populated ball	D
			Ball not populated	E
				F
				G
Top view				H
				J
(See the balls through the package)				K
				L
				M
				N

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		Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet	DDR3 SDRAM
K4B2G0446D

3.2 x8 Package Pinout (Top view) : 78ball FBGA Package

1

2

3

4

5

6

7

8

9

A

VSS

VDD

NC

VSS

VDD

NU/TDQS

A

B

VSS

VSSQ

DQ0

DM/TDQS

VSSQ

VDDQ

B

C

VDDQ

DQ2

DQS

DQ1

DQ3

VSSQ

C

D

VSSQ

DQ6

DQS

VDD

VSS

VSSQ

D

E

VREFDQ

VDDQ

DQ4

DQ7

DQ5

VDDQ

E

F

NC

VSS

RAS

CK

VSS

NC

F

G

ODT

VDD

CAS

CK

VDD

CKE

G

H

NC

CS

WE

A10/AP

ZQ

NC

H

J

VSS

BA0

BA2

NC

VREFCA

VSS

J

K

VDD

A3

A0

BA1

VDD

K

A12/BC

L

VSS

A5

A2

A1

A4

VSS

L

M

VDD

A7

A9

A11

A6

VDD

M

N

VSS

RESET

A13

A14

A8

VSS

N

1

2

3

4

5

6

7

8

9

Ball Locations (x8)				A
				B
				C
			Populated ball	D
			Ball not populated	E
				F
				G
Top view				H
				J
(See the balls through the package)				K
				L
				M
				N

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		Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet	DDR3 SDRAM
K4B2G0446D

3.3 FBGA Package Dimension (x4/x8)

7.50 ± 0.10

Units : Millimeters

A

0.80 x 8 =

6.40

(Datum A)

0.80

1.60

3.20

#A1 INDEX MARK

9

8

7

6

5

4

3

2

1

B

A

B

(Datum B)

C

4.80

D

0.80

9.60=

0.10

E

F

G

0.80x 12

11.00±

H

J

K

0.80

L

M

N

78 - 0.45 Solder ball

(0.95)

MOLDING AREA

(Post Reflow 0.50 ± 0.05)

(1.90)

0.2 M

A

B

BOTTOM VIEW

#A1	7.50 ± 0.10
	11.00 ± 0.10

TOP VIEW

0.10MAX

0.35± 0.05

1.10± 0.10

- 8 -

Rev. 1.11

K4B2G0846D

”YNN MacshbM·

datasheet

DDR3 SDRAM

K4B2G0446D

4. Input/Output Functional Description

[ Table 3 ] Input/Output function description

Symbol

Type

Function

Clock: CK and

are differential clock inputs. All address and control input signals are sampled on the crossing of

Input

CK

CK, CK

the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and

output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or

CKE

Input

Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become

stable during the power on and initialization sequence, it must be maintained during all operations (including Self-

Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK,

CK,

ODT

and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.

Chip Select: All commands are masked when

is registered HIGH.

provides for external Rank selection on

Input

CS

CS

CS

systems with multiple Ranks. CS is considered part of the command code.

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When

ODT

Input

enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode

Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is pro-

grammed to disable ODT.

Input

Command Inputs:

and

(along with

define the command being entered.

RAS,

CAS,

WE

RAS,

CAS

WE

CS)

DM

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-

Input

dent with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of

(DMU), (DML)

DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being

BA0 - BA2

Input

applied. Bank address also determines if the mode register or extended mode register is to be accessed during a

MRS cycle.

Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands

have additional functions,

A0 - A14

Input

to select one location out of the memory array in the respective bank. (A10/AP and A12/BC

see below)

The address inputs also provide the op-code during Mode Register Set commands.

Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-

A10 / AP

Input

formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)

A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or

all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.

Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-

A12 / BC

Input

formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details

Active Low Asynchronous Reset: Reset is active when

is LOW, and inactive when

is HIGH.

RESET

RESET

RESET

Input

RESET

must be HIGH during normal operation.

RESET

is a CMOS rail to rail signal with DC high and low at 80% and

20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.

DQ

Input/Output

Data Input/ Output: Bi-directional data bus.

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the

x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data

DQS,

(DQS)

Input/Output

strobe DQS, DQSL and DQSU are paired with differential signals

DQS,

DQSL

and

DQSU,

respectively, to provide dif-

ferential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and

does not support single-ended.

is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in

Termination Data Strobe: TDQS/TDQS

MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When

TDQS, (TDQS)

Output

disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/

x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1.

NC

No Connect: No internal electrical connection is present.

VDDQ

Supply

DQ Power Supply: 1.5V +/- 0.075V

VSSQ

Supply

DQ Ground

VDD

Supply

Power Supply: 1.5V +/- 0.075V

VSS

Supply

Ground

VREFDQ

Supply

Reference voltage for DQ

VREFCA

Supply

Reference voltage for CA

ZQ

Supply

Reference Pin for ZQ calibration

NOTE : Input only pins (BA0-BA2, A0-A14,

CKE, ODT and

do not supply termination.

RAS,

CAS,

WE,

CS,

RESET)

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Rev. 1.11

K4B2G0846D

”YNN MacshbM·

datasheet

DDR3 SDRAM

K4B2G0446D

5. DDR3 SDRAM Addressing

1Gb

Configuration

256Mb x 4

128Mb x 8

64Mb x 16

# of Bank

8

8

8

Bank Address

BA0 - BA2

BA0 - BA2

BA0 - BA2

Auto precharge

A10/AP

A10/AP

A10/AP

Row Address

A0 - A13

A0 - A13

A0 - A12

Column Address

A0 - A9,A11

A0 - A9

A0 - A9

BC switch on the fly

A12

A12

A12

/BC

/BC

/BC

Page size *1

1 KB

1 KB

2 KB

2Gb

Configuration

512Mb x 4

256Mb x 8

128Mb x 16

# of Bank

8

8

8

Bank Address

BA0 - BA2

BA0 - BA2

BA0 - BA2

Auto precharge

A10/AP

A10/AP

A10/AP

Row Address

A0 - A14

A0 - A14

A0 - A13

Column Address

A0 - A9,A11

A0 - A9

A0 - A9

BC switch on the fly

A12

A12

A12

/BC

/BC

/BC

Page size *1

1 KB

1 KB

2 KB

4Gb

Configuration

1Gb x 4

512Mb x 8

256Mb x 16

# of Bank

8

8

8

Bank Address

BA0 - BA2

BA0 - BA2

BA0 - BA2

Auto precharge

A10/AP

A10/AP

A10/AP

Row Address

A0 - A15

A0 - A15

A0 - A14

Column Address

A0 - A9,A11

A0 - A9

A0 - A9

BC switch on the fly

A12

A12

A12

/BC

/BC

/BC

Page size *1

1 KB

1 KB

2 KB

8Gb

Configuration

2Gb x 4

1Gb x 8

512Mb x 16

# of Bank

8

8

8

Bank Address

BA0 - BA2

BA0 - BA2

BA0 - BA2

Auto precharge

A10/AP

A10/AP

A10/AP

Row Address

A0 - A15

A0 - A15

A0 - A15

Column Address

A0 - A9,A11,A13

A0 - A9,A11

A0 - A9

BC switch on the fly

A12

A12

A12

/BC

/BC

/BC

Page size *1

2 KB

2 KB

2 KB

NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG÷8

where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits

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								Rev. 1.11
	K4B2G0846D				”YNN MacshbM·
				datasheet		DDR3 SDRAM
	K4B2G0446D
	6. Absolute Maximum Ratings
	6.1 Absolute Maximum DC Ratings
	[ Table 4 ] Absolute Maximum DC Ratings
	Symbol		Parameter		Rating		Units	NOTE
	VDD		Voltage on VDD pin relative to Vss		-0.4 V ~ 1.975 V		V	1,3
	VDDQ		Voltage on VDDQ pin relative to Vss		-0.4 V ~ 1.975 V		V	1,3
	VIN, VOUT		Voltage on any pin relative to Vss		-0.4 V ~ 1.975 V		V	1
	TSTG		Storage Temperature		-55 to +100		°C	1, 2

NOTE :

1.Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3.VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.

6.2 DRAM Component Operating Temperature Range

[ Table 5 ] Temperature Range

Symbol	Parameter	rating	Unit	NOTE
TOPER	Operating Temperature Range	0 to 95	°C	1, 2, 3

NOTE :

1.Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.

2.The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85°C under all operating conditions

3.Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

a)Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.

b)If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

7. AC & DC Operating Conditions

7.1 Recommended DC operating Conditions (SSTL_1.5)

[ Table 6 ] Recommended DC Operating Conditions

	Symbol	Parameter		Rating		Units	NOTE
			Min.	Typ.	Max.
	VDD	Supply Voltage	1.425	1.5	1.575	V	1,2
	VDDQ	Supply Voltage for Output	1.425	1.5	1.575	V	1,2

NOTE :

1.Under all conditions VDDQ must be less than or equal to VDD.

2.VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

- 11 -

Rev. 1.11

K4B2G0846D

”YNN MacshbM·

datasheet

DDR3 SDRAM

K4B2G0446D

8. AC & DC Input Measurement Levels

8.1 AC & DC Logic input levels for single-ended signals

[ Table 7 ] Single-ended AC & DC input levels for Command and Address

Symbol

Parameter

DDR3-800/1066/1333/1600

DDR3-1866

Unit

NOTE

Min.

Max.

Min.

Max.

VIH.CA(DC100)

DC input logic high

VREF + 100

VDD

VREF + 100

VDD

mV

1,5

VIL.CA(DC100)

DC input logic low

VSS

VREF - 100

VSS

VREF - 100

mV

1,6

VIH.CA(AC175)

AC input logic high

VREF + 175

Note 2

-

-

mV

1,2,7

VIL.CA(AC175)

AC input logic low

Note 2

VREF - 175

-

-

mV

1,2,8

VIH.CA(AC150)

AC input logic high

VREF+150

Note 2

-

-

mV

1,2,7

VIL.CA(AC150)

AC input logic low

Note 2

VREF-150

-

-

mV

1,2,8

VIH.CA(AC135)

AC input logic high

-

-

VREF + 135

Note 2

mV

1,2,7

VIL.CA(AC135)

AC input logic low

-

-

Note 2

VREF - 135

mV

1,2,8

VIH.CA(AC125)

AC input logic high

-

-

VREF+125

Note 2

mV

1,2,7

VIL.CA(AC125)

AC input logic low

-

-

Note 2

VREF-125

mV

1,2,8

VREFCA(DC)

Reference Voltage for

0.49*VDD

0.51*VDD

0.49*VDD

0.51*VDD

V

3,4

ADD, CMD inputs

NOTE :

1.For input only pins except RESET, VREF = VREFCA(DC)

2.See ’Overshoot/Undershoot Specification’ on page 19.

3.The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

4.For reference : approx. VDD/2 ± 15mV

5.VIH(dc) is used as a simplified symbol for VIH.CA(DC100)

6.VIL(dc) is used as a simplified symbol for VIL.CA(DC100)

7.VIH(ac) is used as a simplified symbol for VIH.CA(AC175) and VIH.CA(AC150); VIH.CA(AC175) value is used when VREF + 175mV is referenced and VIH.CA(AC150) value is used when VREF + 150mV is referenced.

8.VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150); VIL.CA(AC175) value is used when VREF - 175mV is referenced and VIL.CA(AC150) value is used when VREF - 150mV is referenced.

[ Table 8 ] Single-ended AC & DC input levels for DQ and DM

	Symbol	Parameter	DDR3-800/1066		DDR3-1333/1600		DDR3-1866		Unit	NOTE
			Min.	Max.	Min.	Max.	Min.	Max.
	VIH.DQ(DC100)	DC input logic high	VREF + 100	VDD	VREF + 100	VDD	VREF + 100	VDD	mV	1,5
	VIL.DQ(DC100)	DC input logic low	VSS	VREF - 100	VSS	VREF - 100	VSS	VREF - 100	mV	1,6
	VIH.DQ(AC175)	AC input logic high	VREF + 175	NOTE 2	-	-	-	-	mV	1,2,7
	VIL.DQ(AC175)	AC input logic low	NOTE 2	VREF - 175	-	-	-	-	mV	1,2,8
	VIH.DQ(AC150)	AC input logic high	VREF + 150	NOTE 2	VREF + 150	NOTE 2	-	-	mV	1,2,7
	VIL.DQ(AC150)	AC input logic low	NOTE 2	VREF - 150	NOTE 2	VREF - 150	-	-	mV	1,2,8
	VIH.DQ(AC135)	AC input logic high	-	-	-	-	VREF + 135	NOTE 2	mV	1,2,7
	VIL.DQ(AC135)	AC input logic low	-	-	-	-	NOTE 2	VREF - 135	mV	1,2,8
	VREFDQ(DC)	Reference Voltage for DQ,	0.49*VDD	0.51*VDD	0.49*VDD	0.51*VDD	0.49*VDD	0.51*VDD	V	3,4
		DM inputs

NOTE :

1.For input only pins except RESET, VREF = VREFDQ(DC)

2.See ’Overshoot/Undershoot Specification’ on page 19.

3.The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

4.For reference : approx. VDD/2 ± 15mV

5.VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)

6.VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)

7.VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150) ; VIH.DQ(AC175) value is used when VREF + 175mV is referenced, VIH.DQ(AC150) value is used when VREF + 150mV is referenced.

8.VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150) ; VIL.DQ(AC175) value is used when VREF - 175mV is referenced, VIL.DQ(AC150) value is used when VREF - 150mV is referenced.

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		Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet	DDR3 SDRAM
K4B2G0446D

8.2 VREF Tolerances

The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).

VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on page 12. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.

voltage

VDD

VSS

time

Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF.

"VREF" shall be understood as VREF(DC), as defined in Figure 1 .

This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

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		Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet	DDR3 SDRAM
K4B2G0446D

8.3 AC & DC Logic Input Levels for Differential Signals

8.3.1 Differential signals definition

tDVAC

CK-CK)

VIH.DIFF.AC.MIN

VIH.DIFF.MIN

DQS-DQS,

0.0

(i.e.

half cycle

Voltage

VIL.DIFF.MAX

Input

Differential

VIL.DIFF.AC.MAX

tDVAC

time

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)

[ Table 9 ] Differential AC & DC Input Levels

	Symbol	Parameter	DDR3-800/1066/1333/1600/1866		unit	NOTE
			min	max
	VIHdiff	differential input high	+0.2	NOTE 3	V	1
	VILdiff	differential input low	NOTE 3	-0.2	V	1
	VIHdiff(AC)	differential input high ac	2 x (VIH(AC) - VREF)	NOTE 3	V	2
	VILdiff(AC)	differential input low ac	NOTE 3	2 x (VIL(AC) - VREF)	V	2

NOTE :

1.Used to define a differential signal slew-rate.

2.for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3.These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max,

VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"

[ Table 10 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

	tDVAC [ps] @ |VIH/Ldiff(AC)|			tDVAC [ps] @ |VIH/Ldiff(AC)|			tDVAC [ps] @ |VIH/Ldiff(AC)|			tDVAC [ps] @ |VIH/Ldiff(AC)|
Slew Rate [V/ns]		= 350mV			= 300mV			= 270mV			= 250mV
	min		max	min		max	min		max	min		max
> 4.0	75		-	175		-	TBD		-	TBD		-
4.0	57		-	170		-	TBD		-	TBD		-
3.0	50		-	167		-	TBD		-	TBD		-
2.0	38		-	163		-	TBD		-	TBD		-
1.8	34		-	162		-	TBD		-	TBD		-
1.6	29		-	161		-	TBD		-	TBD		-
1.4	22		-	159		-	TBD		-	TBD		-
1.2	13		-	155		-	TBD		-	TBD		-
1.0	0		-	150		-	TBD		-	TBD		-
< 1.0	0		-	150		-	TBD		-	TBD		-

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		Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet	DDR3 SDRAM
K4B2G0446D

8.3.3 Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals.

CK and CK have to approximately reach VSEHmin / VSELmax [approximately equal to the ac-levels { VIH(AC) / VIL(AC)} for ADD/CMD signals] in every half-cycle.

DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax [approximately the ac-levels { VIH(AC) / VIL(AC)} for DQ signals] in every half-cycle

proceeding and following a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD sig-

nals, then these ac-levels apply also for the single-ended signals CK and CK .

VDD or VDDQ

VSEH min

VSEH

VDD/2 or VDDQ/2

CK or DQS

VSEL max

VSEL

VSS or VSSQ

time

Figure 3. Single-ended requirement for differential signals

Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.

[ Table 11 ] Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU

Symbol	Parameter					DDR3-1066/1333/1600/1866		Unit	NOTE
						Min	Max
VSEH	Single-ended high-level for strobes					(VDD/2)+0.175	NOTE3	V	1, 2
						(VDD/2)+0.175
	Single-ended high-level for CK, CK						NOTE3	V	1, 2
VSEL	Single-ended low-level for strobes					NOTE3	(VDD/2)-0.175	V	1, 2
							(VDD/2)-0.175
	Single-ended low-level for CK, CK					NOTE3		V	1, 2

NOTE :

1.For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.

2.VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here

3.These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"

- 15 -

		Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet	DDR3 SDRAM
K4B2G0446D

8.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS.

VDD

CK,

DQS

VIX

VDD/2

VIX

VIX

CK, DQS

VSS

Figure 4. VIX Definition

[ Table 12 ] Cross point voltage for differential input signals (CK, DQS)

Symbol

Parameter

DDR3-800/1066/1333/1600/1866

Unit

NOTE

Min

Max

-150

150

mV

VIX

Differential Input Cross Point Voltage relative to VDD/2 for CK,CK

-175

175

mV

1

VIX

Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS

-150

150

mV

NOTE :

1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2

±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. Refer to Table 11 on page 15 for VSEL and VSEH standard values. 2. The relation between VIX Min/Max and VSEL/VSEH should satisfy following.

(VDD/2) + VIX(Min) - VSEL ≥ 25mV VSEH - ((VDD/2) + VIX(Max)) ≥ 25mV

8.5 Slew rate definition for Differential Input Signals

See 14.3 “Address/Command Setup, Hold and Derating :” on page 48 for single-ended slew rate definitions for address and command signals. See 14.4 “Data Setup, Hold and Slew Rate Derating :” on page 54 for single-ended slew rate definitions for data signals.

8.6 Slew rate definitions for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 13 and Figure 5.

[ Table 13 ] Differential input slew rate definition

Description

Measured

Defined by

From

To

VILdiffmax

VIHdiffmin

VIHdiffmin - VILdiffmax

Differential input slew rate for rising edge (CK-CK and DQS-DQS)

Delta TRdiff

VIHdiffmin

VILdiffmax

VIHdiffmin - VILdiffmax

Differential input slew rate for falling edge (CK-CK and DQS-DQS)

Delta TFdiff

NOTE :

The differential signal (i.e. CK -

CK

and DQS -

DQS)

must be linear between these thresholds.

	VIHdiffmin
	0
	VILdiffmax
delta TFdiff	delta TRdiff

Figure 5. Differential Input Slew Rate definition for DQS, DQS, and CK, CK

- 16 -

						Rev. 1.11
	K4B2G0846D	”YNN MacshbM·
		datasheet		DDR3 SDRAM
	K4B2G0446D
	9. AC & DC Output Measurement Levels
	9.1 Single-ended AC & DC Output Levels
	[ Table 14 ] Single-ended AC & DC output levels
	Symbol	Parameter	DDR3-800/1066/1333/1600/1866		Units	NOTE
	VOH(DC)	DC output high measurement level (for IV curve linearity)		0.8 x VDDQ	V
	VOM(DC)	DC output mid measurement level (for IV curve linearity)		0.5 x VDDQ	V
	VOL(DC)	DC output low measurement level (for IV curve linearity)		0.2 x VDDQ	V
	VOH(AC)	AC output high measurement level (for output SR)		VTT + 0.1 x VDDQ	V	1
	VOL(AC)	AC output low measurement level (for output SR)		VTT - 0.1 x VDDQ	V	1

NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2.

9.2 Differential AC & DC Output Levels

[ Table 15 ] Differential AC & DC output levels

Symbol	Parameter	DDR3-800/1066/1333/1600/1866	Units	NOTE
VOHdiff(AC)	AC differential output high measurement level (for output SR)	+0.2 x VDDQ	V	1
VOLdiff(AC)	AC differential output low measurement level (for output SR)	-0.2 x VDDQ	V	1

NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.

9.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 16 and Figure 6.

[ Table 16 ] Single-ended output slew rate definition

Description	Measured			Defined by
	From	To
Single ended output slew rate for rising edge	VOL(AC)	VOH(AC)		VOH(AC)-VOL(AC)
				Delta TRse
Single ended output slew rate for falling edge	VOH(AC)	VOL(AC)		VOH(AC)-VOL(AC)
				Delta TFse

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 17 ] Single-ended output slew rate

Parameter

Symbol

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Single ended output slew rate

SRQse

2.5

5

2.5

5

2.5

5

2.5

5

2.5

51)

V/ns

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

se : Single-ended Signals For Ron = RZQ/7 setting

NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).

- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

VOH(AC)

VTT

VOL(AC)

delta TFse

delta TRse

Figure 6. Single-ended Output Slew Rate Definition

- 17 -

		Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet	DDR3 SDRAM
K4B2G0446D

9.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 18 and Figure 7.

[ Table 18 ] Differential output slew rate definition

Description	Measured			Defined by
	From	To
Differential output slew rate for rising edge	VOLdiff(AC)	VOHdiff(AC)		VOHdiff(AC)-VOLdiff(AC)
				Delta TRdiff
Differential output slew rate for falling edge	VOHdiff(AC)	VOLdiff(AC)		VOHdiff(AC)-VOLdiff(AC)
				Delta TFdiff

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 19 ] Differential output slew rate

Parameter

Symbol

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Differential output slew rate

SRQdiff

5

10

5

10

5

10

5

10

5

12

V/ns

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

diff : Differential Signals For Ron = RZQ/7 setting

VOHdiff(AC)

VTT

VOLdiff(AC)

delta TFdiff

delta TRdiff

Figure 7. Differential Output Slew Rate Definition

9.5 Reference Load for AC Timing and Output Slew Rate

Figure 8 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements.

It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

VDDQ

DQ

CK/CK DUT DQS VTT = VDDQ/2

DQS

25Ω

Reference

Point

Figure 8. Reference Load for AC Timing and Output Slew Rate

- 18 -

		Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet	DDR3 SDRAM
K4B2G0446D

9.6 Overshoot/Undershoot Specification

9.6.1 Address and Control Overshoot and Undershoot specifications

[ Table 20 ] AC overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2. CS. RAS. CAS. WE. CKE, ODT)

	Parameter			Specification			Unit
		DDR3-800	DDR3-1066	DDR3-1333	DDR3-1600	DDR3-1866
	Maximum peak amplitude allowed for overshoot area (See Figure 9)	0.4V	0.4V	0.4V	0.4V	0.4V	V
	Maximum peak amplitude allowed for undershoot area (See Figure 9)	0.4V	0.4V	0.4V	0.4V	0.4V	V
	Maximum overshoot area above VDD (See Figure 9)	0.67V-ns	0.5V-ns	0.4V-ns	0.33V-ns	0.28V-ns	V-ns
	Maximum undershoot area below VSS (See Figure 9)	0.67V-ns	0.5V-ns	0.4V-ns	0.33V-ns	0.28V-ns	V-ns

Maximum Amplitude

Overshoot Area

Volts VDD

(V)

VSS

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 9. Address and Control Overshoot and Undershoot Definition

9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications

[ Table 21 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask (DQ, DQS, DQS, DM, CK, CK)

	Parameter			Specification			Unit
		DDR3-800	DDR3-1066	DDR3-1333	DDR3-1600	DDR3-1866
	Maximum peak amplitude allowed for overshoot area (See Figure 10)	0.4V	0.4V	0.4V	0.4V	0.4V	V
	Maximum peak amplitude allowed for undershoot area (See Figure 10)	0.4V	0.4V	0.4V	0.4V	0.4V	V
	Maximum overshoot area above VDDQ (See Figure 10)	0.25V-ns	0.19V-ns	0.15V-ns	0.13V-ns	0.11V-ns	V-ns
	Maximum undershoot area below VSSQ (See Figure 10)	0.25V-ns	0.19V-ns	0.15V-ns	0.13V-ns	0.11V-ns	V-ns

Maximum Amplitude

Overshoot Area

Volts VDDQ

(V)

VSSQ

Undershoot Area

Maximum Amplitude

Time (ns)

Figure 10. Clock, Data, Strobe and Mask Overshoot and Undershoot Definition

- 19 -

		Rev. 1.11
K4B2G0846D	”YNN MacshbM·
	datasheet	DDR3 SDRAM
K4B2G0446D

9.7 34ohm Output Driver DC Electrical Characteristics

A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ as follows:

RON34 = RZQ/7 (Nominal 34.3ohms +/- 10% with nominal RZQ=240ohm)

The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows

	RONpu =	VDDQ-VOUT	under the condition that RONpd is turned off
		l Iout l
	RONpd =	VOUT	under the condition that RONpu is turned off
		l Iout l

	Output Driver
	VDDQ
	Ipu
To	RONPu
other
circuity	DQ
	Iout
	RONPd
	Vout
	Ipd
	VSSQ

Figure 11. Output Driver : Definition of Voltages and Currents

[ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohms ; entire operating temperature range ; after proper ZQ calibration

RONnom		Resistor	Vout	Min	Nom	Max	Units	NOTE
			VOLdc = 0.2 x VDDQ	0.6	1.0	1.1		1,2,3
		RON34pd	VOMdc = 0.5 x VDDQ	0.9	1.0	1.1		1,2,3
34Ohms			VOHdc = 0.8 x VDDQ	0.9	1.0	1.4	RZQ/7	1,2,3
			VOLdc = 0.2 x VDDQ	0.9	1.0	1.4		1,2,3
		RON34pu	VOMdc = 0.5 x VDDQ	0.9	1.0	1.1		1,2,3
			VOHdc = 0.8 x VDDQ	0.6	1.0	1.1		1,2,3
			VOLdc = 0.2 x VDDQ	0.6	1.0	1.1		1,2,3
		RON40pd	VOMdc = 0.5 x VDDQ	0.9	1.0	1.1		1,2,3
40Ohms			VOHdc = 0.8 x VDDQ	0.9	1.0	1.4	RZQ/6	1,2,3
			VOLdc = 0.2 x VDDQ	0.9	1.0	1.4		1,2,3
		RON40pu	VOMdc = 0.5 x VDDQ	0.9	1.0	1.1		1,2,3
			VOHdc = 0.8 x VDDQ	0.6	1.0	1.1		1,2,3
Mismatch between Pull-up and Pull-down,			VOMdc = 0.5 x VDDQ	-10		10	%	1,2,4
	MMpupd

NOTE :

1.The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity

2.The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS

3.Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X VDDQ. Other calibration schemes may be used to achieve the linearity spec shown

above, e.g. calibration at 0.2 X VDDQ and 0.8 X VDDQ

4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X VDDQ:

MMpupd = RONpu - RONpd x 100

RONnom

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