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‡.25 m five layer metal CMOS Process
‡2.5 V VCC, 2.5/3.3 V Drive Capable I/O
‡4,032 Logic Cells
‡583,008 Max System Gates
‡Up to 506 I/O Pins
(PEHGGHG 'XDO 3RUW 65$0
‡Thirty-six 2,304-bit Dual Port High Performance SRAM Blocks
‡82,900 RAM Bits
‡RAM/ROM/FIFO Wizard for Automatic Configuration
‡Configurable and Cascadable
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‡Programmable Slew Rate Control
‡Programmable I/O Standards:
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ECUs provide integrated Multiply, Add, and Accumulate Functions.
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Memory - Dual Port RAM |
PLL |
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Embedded Computational Units |
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High Speed Logic Cells
583K Gates
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PLL |
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Memory - Dual Port RAM |
PLL |
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‡ LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3 Figure 1: EclipsePlus Block Diagram
‡Eight Independent I/O Banks
‡Three Register Configurations: Input, Output, and Output Enable
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*(at VCC = 2.5 V, TA = 25° C, Typical Corner, Speed Grade = -7 (K = 0.74))
The AC Specifications are provided from 7DEOH to 7DEOH . Logic Cell diagrams and waveforms are provided from to )LJXUH .
Figure 2: EclipsePlus Logic Cell
7DEOH /RJLF &HOOV
6\PERO |
3DUDPHWHU |
9DOXH |
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/RJLF &HOOV |
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0LQ |
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0D[ |
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tPD |
Combinatorial Delay of the longest path: time taken by the combinatorial circuit to |
- |
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0.257 ns |
output |
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tSU |
Setup time: time the synchronous input of the flip-flop must be stable before the |
0.22 ns |
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- |
active clock edge |
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tHL |
Hold time: time the synchronous input of the flip-flop must be stable after the active |
0 ns |
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- |
clock edge |
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tCO |
Clock-to-out delay: the amount of time taken by the flip-flop to output after the |
- |
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0.255 ns |
active clock edge. |
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tCWHI |
Clock High Time: required minimum time the clock stays high |
0.46 ns |
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- |
tCWLO |
Clock Low Time: required minimum time that the clock stays low |
0.46 ns |
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- |
tSET |
Set Delay: time between when the flip-flop is ”set” (high) |
- |
|
0.18 ns |
and when the output is consequently “set” (high) |
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3DUDPHWHU |
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0D[ |
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tRESET |
Reset Delay: time between when the flip-flop is ”reset” (low) and when the output |
- |
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0.09 ns |
is consequently “reset” (low) |
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tSW |
Set Width: time that the SET signal remains high/low |
0.3 ns |
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- |
tRW |
Reset Width: time that the RESET signal remains high/low |
0.3 ns |
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- |
SET
D
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CLK
RESET
Figure 3: Logic Cell Flip-Flop
CLK
tCWHI (min) tCWLO (min)
SET
RESET
Q
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tRESET |
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tSET |
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tRW |
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tSW |
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Figure 4: Logic Cell Flip-Flop Timings—First Waveform
CLK |
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D |
tSU |
tHL |
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tCO
Figure 5: Logic Cell Flip-Flop Timings—Second Waveform
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Figure 6: EclipsePlus Global Clock Structure
7DEOH (FOLSVH3OXV &ORFN 'HOD\
&ORFN 6RXUFH |
3DUDPHWHUV |
&ORFN 3HUIRUPDQFH |
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Logic Cells (Internal) |
Clock signal generated internally |
1.51 ns (max) |
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Clock Pad |
Clock signal generated externally |
2.06 ns (max) |
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1.73 ns (max) |
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7DEOH (FOLSVH3OXV *OREDO &ORFN 'HOD\ |
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&ORFN 6HJPHQW |
3DUDPHWHU |
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9DOXH |
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0LQ |
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0D[ |
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a |
Global clock pin delay to quad net |
- |
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1.34 ns |
tPGCK |
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tBGCK |
Global clock tree delay |
- |
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0.56 ns |
(quad net to flip-flop) |
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a.When using a PLL, tPGCK and tBGCK are effectively zero due to delay adjustment by Phase Locked Loop.
Programmable Clock |
Global Clock Buffer |
External Clock
|
Global Clock |
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Clock |
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Select |
tPGCK |
tBGCK |
Figure 7: Global Clock Structure Schematic
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RE |
WA |
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[17:0] |
RCLK |
WD |
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WE |
[9:0] |
RA |
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[17:0] |
WCLK |
RD |
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ASYNCRD |
QuickRAM |
Module |
Figure 8: RAM Module
7DEOH 5$0 &HOO 6\QFKURQRXV :ULWH 7LPLQJ
6\PERO |
3DUDPHWHU |
9DOXH |
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5$0 &HOO 6\QFKURQRXV :ULWH 7LPLQJ |
0LQ |
0D[ |
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tSWA |
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the |
0.675 ns |
- |
active edge of the WRITE CLOCK |
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tHWA |
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active |
0ns |
- |
edge of the WRITE CLOCK |
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tSWD |
WD setup time to WCLK: time the WRITE DATA must be stable before the active |
0.654 ns |
- |
edge of the WRITE CLOCK |
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tHWD |
WD hold time to WCLK: time the WRITE DATA must be stable after the active edge |
0 ns |
- |
of the WRITE CLOCK |
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tSWE |
WE setup time to WCLK: time the WRITE ENABLE must be stable before the active |
0.623 ns |
- |
edge of the WRITE CLOCK |
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tHWE |
WE hold time to WCLK: time the WRITE ENABLE must be stable after the active |
0 ns |
- |
edge of the WRITE CLOCK |
|||
tWCRD |
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the |
- |
4.38 ns |
time when the data is available at RD |
WCLK
WA
tSWA |
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tHWA |
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WD
tSWD tHWD
WE
tSWE tHWE
RD |
old data |
new data |
tWCRD
Figure 9: RAM Cell Synchronous Write Timing
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6\PERO |
3DUDPHWHU |
9DOXH |
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5$0 &HOO 6\QFKURQRXV 5HDG 7LPLQJ |
0LQ |
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tSRA |
RA setup time to RCLK: time the READ ADDRESS must be stable before the active |
0.686 ns |
- |
edge of the READ CLOCK |
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tHRA |
RA hold time to RCLK: time the READ ADDRESS must be stable after the active |
0 ns |
- |
edge of the READ CLOCK |
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tSRE |
RE setup time to WCLK: time the READ ENABLE must be stable before the active |
0.243 ns |
- |
edge of the READ CLOCK |
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tHRE |
RE hold time to WCLK: time the READ ENABLE must be stable after the active |
0 ns |
- |
edge of the READ CLOCK |
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tRCRD |
RCLK to RD: time between the active READ CLOCK edge and the time when the |
- |
4.38 ns |
data is available at RD |
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5$0 &HOO $V\QFKURQRXV 5HDG 7LPLQJ |
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rPDRD |
RA to RD: time between when the READ ADDRESS is input and when the DATA |
- |
2.06 ns |
is output |
RCLK
RA
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tSRA |
tHRA |
RE |
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tSRE |
tHRE |
RD |
old data |
new data |
tRCRD
rPDRD
Figure 10: RAM Cell Synchronous & Asynchronous Read Timing
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OUTPUT |
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REGISTER |
R |
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OUTPUT ENABLE |
E Q |
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REGISTER |
R |
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Figure 11: EclipsePlus Cell I/O
tISU
+
-
tSID
Q E
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PAD
Figure 12: EclipsePlus Input Register Cell
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6\PERO |
3DUDPHWHU |
9DOXH |
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0LQ |
0D[ |
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tISU |
Input register setup time: time the synchronous input of the flip-flop must be stable |
3.12 ns |
- |
before the active clock edge |
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tIHL |
Input register hold time: time the synchronous input of the flip-flop must be stable |
0 ns |
- |
after the active clock edge |
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tICO |
Input register clock-to-out: time taken by the flip-flop to output after the active clock |
- |
1.08 ns |
edge |
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tIRST |
Input register reset delay: time between when the flip-flop is “reset”(low) and when |
- |
0.99 ns |
the output is consequently “reset” (low) |
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tIESU |
Input register clock enable setup time: time “enable” must be stable before the |
0.37 ns |
- |
active clock edge |
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tIEH |
Input register clock enable hold time: time “enable” must be stable after the active |
0 ns |
- |
clock edge |
7DEOH 6WDQGDUG ,QSXW 'HOD\V
6\PERO |
3DUDPHWHU |
9DOXH |
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tSID (LVTTL) |
LVTTL input delay: Low Voltage TTL for 3.3 V applications |
- |
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0.34 ns |
tSID (LVCMOS2) |
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower |
- |
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0.42 ns |
applications |
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tSID (GTL+) |
GTL+ input delay: Gunning Transceiver Logic |
- |
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0.68 ns |
tSID (SSTL3) |
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V |
- |
|
0.55 ns |
tSID (SSTL2) |
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V |
- |
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0.61 ns |
R
CLK
D
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tICO |
tIRST
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tIESU tIEH
Figure 13: EclipsePlus Input Register Cell Timing
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OUTPUT
REGISTER
Figure 14: EclipsePlus Output Register Cell
7DEOH (FOLSVH3OXV 2XWSXW 5HJLVWHU &HOO
6\PERO |
3DUDPHWHU |
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2XWSXW 5HJLVWHU &HOO 2QO\ |
0LQ |
0D[ |
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tOUTLH |
Output Delay low to high (90% of H) |
- |
0.40 ns |
tOUTHL |
Output Delay high to low (10% of L) |
- |
0.55 ns |
tPZH |
Output Delay tri-state to high (90% of H) |
- |
2.94 ns |
tPZL |
Output Delay tri-state to low (10% of L) |
- |
2.34 ns |
tPHZ |
Output Delay high to tri-State |
- |
3.07 ns |
tPLZ |
Output Delay low to tri-State |
- |
2.53 ns |
tCOP |
Clock-to-out delay (does not include clock tree delays) |
- |
3.15 ns (fast slew) |
10.2 ns (slow slew) |
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tPHZ |
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tPLZ |
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Figure 15: EclipsePlus Output Register Cell Timing
7DEOH 2XWSXW 6OHZ 5DWHV # 9&&,2 9
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6ORZ 6OHZ |
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Rising Edge |
2.8 V/ns |
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1.0 V/ns |
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Falling Edge |
2.86 V/ns |
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1.0 V/ns |
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7DEOH 2XWSXW 6OHZ 5DWHV # 9&&,2 9 |
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6ORZ 6OHZ |
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Rising Edge |
1.7 V/ns |
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0.6 V/ns |
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Falling Edge |
1.9 V/ns |
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0.6 V/ns |
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-0.5 V to 3.6 V |
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±20 mA |
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2.7 V |
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-65° C to + 150° C |
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-55° C to + 125° C |
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±100 mA |
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VCC |
Supply Voltage |
2.3 |
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2.7 |
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2.3 |
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2.7 |
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2.3 |
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2.7 |
V |
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I/O Input Tolerance Voltage |
2.3 |
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3.6 |
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2.3 |
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3.6 |
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2.3 |
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3.6 |
V |
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TA |
Ambient Temperature |
-55 |
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-40 |
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85 |
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70 |
°C |
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TC |
Case Temperature |
- |
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125 |
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- |
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- |
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- |
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- |
°C |
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-4 Speed Grade |
0.42 |
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2.3 |
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0.43 |
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2.16 |
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0.47 |
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2.11 |
n/a |
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K |
Delay Factor |
-5 Speed Grade |
0.42 |
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1.92 |
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0.43 |
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1.80 |
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0.46 |
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1.76 |
n/a |
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-6 Speed Grade |
0.42 |
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1.35 |
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0.43 |
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1.26 |
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0.46 |
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1.23 |
n/a |
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-7 Speed Grade |
0.42 |
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1.27 |
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0.43 |
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1.19 |
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0.46 |
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1.16 |
n/a |
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I or I/O Input Leakage Current |
VI = VCCIO or GND |
-10 |
10 |
µA |
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IOZ |
3-State Output Leakage Current |
VI = VCCIO or GND |
-10 |
10 |
µA |
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CI |
Input Capacitancea |
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- |
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- |
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Output Short Circuit Currentb |
Vo = GND |
-15 |
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mA |
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40 |
210 |
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0.50 (typ) |
2 |
mA |
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D.C. Supply Current on VCCIO |
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- |
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0 |
2 |
mA |
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D.C. Supply Current on VCCIO |
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- |
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- |
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mA |
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for Differential I/O |
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IREF |
D.C. Supply Current on INREF |
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- |
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-10 |
10 |
µA |
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IPD |
Pad Pull-down (programmable) |
VCCIO = 3.6 V |
- |
150 |
µA |
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Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively—these functions require high logic cell usage while garnering only moderate performance results.
The QL7180 architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the QL7180 device can address various arithmetic functions efficiently.
This approach offers greater performance than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in
)LJXUH .
RESET |
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D |
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S1 |
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3-4 |
C |
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S2 |
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B |
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decoder |
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S3 |
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A |
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CIN |
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SIGN1 |
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SIGN2 |
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00 |
Q[0:16] |
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01 |
3-1 |
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mux |
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A[0:7] |
8-bit |
2-1 |
16-bit |
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Q |
10 |
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17 inc. |
17-bit |
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Multiplier |
mux |
Adder |
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A[8:15] |
COUT Register |
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A[0:15] |
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CLK |
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B[0:15] |
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2-1 |
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mux |
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Figure 16: ECU Block Diagram
The 18 QL7180 ECU blocks are placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations.
Eighteen 8-bit MAC functions can be implemented per cycle for a total of 1.8 billion MACs when clocked at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic.
The modes for the ECU block are dynamically re-programmable through the programmable logic.
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0 |
0 |
0 |
Multiply |
6.57 ns |
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max |
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0 |
0 |
1 |
Multiply-Add |
8.84 ns |
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max |
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0 |
1 |
0 |
Accumulatec |
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3.91 ns |
1.16 ns |
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min |
max |
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0 |
1 |
1 |
Add |
3.14 ns |
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max |
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1 |
0 |
0 |
Multiply (registered)d |
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9.61 ns |
1.16 ns |
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min |
max |
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1 |
0 |
1 |
MultiplyAdd (registered) |
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9.61 ns |
1.16 ns |
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min |
max |
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1 |
1 |
0 |
Multiply - Accumulate |
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9.61 ns |
1.16 ns |
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min |
max |
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1 |
1 |
1 |
Add (registered) |
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3.91 ns |
1.16 ns |
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min |
max |
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Instead of requiring extra components, designers simply need to instantiate one of the preconfigured models (described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other PLLs. Also, QuickLogic PLLs can be cascaded to support different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock frequency. Most importantly, they achieve a very short clock-to-out time—generally less than 3 ns. This low clock-to-out time is achieved by the PLL subtracting the clock tree delay through the feedback path, effectively making the clock tree delay zero.
)LJXUH illustrates a typical QuickLogic ESP PLL.
1st Quadrant
2nd Quadrant 3rd Quadrant
FIN |
Frequency Divide |
PLL Bypass |
4th Quadrant |
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Clock |
.1 |
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Tree |
. |
+ |
Filter |
vco |
.2 |
|||
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- |
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.4 |
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Frequency Multiply
.
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.
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FOUT
Figure 17: PLL Block
Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself.
Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in )LJXUH ) can compare the two signals. If the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter ()LJXUH ). The charge pump generates an error voltage to bring the VCO back into alignment and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO signal enters the clock tree to drive the chip's circuitry.
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